Section 23 Gigabit Ethernet Controller (GETHER)
Rev. 1.00 Oct. 01, 2007 Page 947 of 1956
REJ09B0256-0100
Bit
Bit
Name
Initial
Value R/W Description
31
RACT
0
R/W
Receive Descriptor Valid/Invalid
Indicates whether this descriptor is valid or invalid. To make
this bit valid, prepare a receive buffer (user-specified
receive data storage destination) beforehand, then write 1
to this bit. The E-DMAC clears this bit to 0 after data
transfer.
0: Indicates that this receive descriptor is invalid
Indicates the initial setting state, the state after 0 is
written to, or (in case the user writes 1 to this bit) that this
bit is cleared to 0 because the E-DMAC data transfer
processing is completed
If this state is recognized when the E-DMAC reads a
descriptor, the E-DMAC clears the RR bit in EDRRR to
0, and halts transfer operation related to reception by the
E-DMAC
1: Indicates that this receive descriptor is valid
Indicates that data is not transferred yet after the user
writes 1 to this bit, or that data is being transferred
When there is a descriptor row (descriptor list) consisting
of multiple continuous descriptors, the E-DMAC can
continue operation when this bit of the next descriptor is
valid
30
RDLE
0
R/W
Receive Descriptor List End
Indicates whether this descriptor is the last descriptor of the
descriptor row (descriptor list).
0: Not last descriptor
After transfer of this descriptor, the E-DMAC reads the
next one in the list of continuous descriptors
1: Last descriptor
After transfer of this descriptor, the E-DMAC reads the
descriptor placed at the address indicated by RDLAR
Summary of Contents for SH7763
Page 2: ...Rev 1 00 Oct 01 2007 Page ii of lxvi ...
Page 122: ...Section 2 Programming Model Rev 1 00 Oct 01 2007 Page 56 of 1956 REJ09B0256 0100 ...
Page 144: ...Section 3 Instruction Set Rev 1 00 Oct 01 2007 Page 78 of 1956 REJ09B0256 0100 ...
Page 170: ...Section 4 Pipelining Rev 1 00 Oct 01 2007 Page 104 of 1956 REJ09B0256 0100 ...
Page 282: ...Section 7 Caches Rev 1 00 Oct 01 2007 Page 216 of 1956 REJ09B0256 0100 ...
Page 378: ...Section 9 Interrupt Controller INTC Rev 1 00 Oct 01 2007 Page 312 of 1956 REJ09B0256 0100 ...
Page 514: ...Section 12 DDR SDRAM Interface DDRIF Rev 1 00 Oct 01 2007 Page 448 of 1956 REJ09B0256 0100 ...
Page 630: ...Section 13 PCI Controller PCIC Rev 1 00 Oct 01 2007 Page 564 of 1956 REJ09B0256 0100 ...
Page 710: ...Section 16 Clock Pulse Generator CPG Rev 1 00 Oct 01 2007 Page 644 of 1956 REJ09B0256 0100 ...
Page 732: ...Section 17 Watchdog Timer and Reset WDT Rev 1 00 Oct 01 2007 Page 666 of 1956 REJ09B0256 0100 ...
Page 752: ...Section 18 Power Down Mode Rev 1 00 Oct 01 2007 Page 686 of 1956 REJ09B0256 0100 ...
Page 772: ...Section 19 Timer Unit TMU Rev 1 00 Oct 01 2007 Page 706 of 1956 REJ09B0256 0100 ...
Page 824: ...Section 21 Compare Match Timer CMT Rev 1 00 Oct 01 2007 Page 758 of 1956 REJ09B0256 0100 ...
Page 1124: ...Section 26 I 2 C Bus Interface IIC Rev 1 00 Oct 01 2007 Page 1058 of 1956 REJ09B0256 0100 ...
Page 1350: ...Section 30 SIM Card Module SIM Rev 1 00 Oct 01 2007 Page 1284 of 1956 REJ09B0256 0100 ...
Page 1484: ...Section 33 Audio Codec Interface HAC Rev 1 00 Oct 01 2007 Page 1418 of 1956 REJ09B0256 0100 ...
Page 1560: ...Section 35 USB Host Controller USBH Rev 1 00 Oct 01 2007 Page 1494 of 1956 REJ09B0256 0100 ...
Page 1720: ...Section 37 LCD Controller LCDC Rev 1 00 Oct 01 2007 Page 1654 of 1956 REJ09B0256 0100 ...
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Page 2026: ...SH7763 Hardware Manual ...