Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Rev. 1.00 Oct. 01, 2007 Page 1151 of 1956
REJ09B0256-0100
28.4 Operation
28.4.1 Overview
The SCIF can carry out serial communication in asynchronous mode, in which synchronization is
achieved character by character and in synchronous mode, in which synchronization is achieved
with clock pulses. For details on asynchronous mode, see section 28.4.2, Operation in
Asynchronous Mode.
16-stage FIFO buffers are provided for both transmission and reception, reducing the CPU
overhead, and enabling fast and continuous communication to be performed.
The serial transfer format is selected using SCSMR, as shown in Table 28.6. The SCIF clock
source is determined by the combination of the C/
A
bit in SCSMR and the CKE1 and CKE0 bits
in SCSCR, as shown in Table 28.7.
Asynchronous Mode:
•
Data length: Choice of 7 or 8 bits
•
Choice of parity addition and addition of 1 or 2 stop bits (the combination of these parameters
determines the transfer format and character length)
•
Detection of framing errors, parity errors, receive-FIFO-data-full state, overrun errors, receive-
data-ready state, and breaks, during reception
•
Indication of the number of data bytes stored in the transmit and receive FIFO registers
•
Choice of peripheral clock 0 (Pck0) or external clock (SCIF_SCK) as SCIF clock source
When peripheral clock 0 (Pck0) is selected:
The SCIF operates on the baud rate generator
clock and can output a clock with frequency of
16 times the bit rate.
When external clock (SCIF_SCK) is selected: A clock with a frequency of 16 times the bit
rate must be input (the on-chip baud rate
generator is not used).
Summary of Contents for SH7763
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Page 122: ...Section 2 Programming Model Rev 1 00 Oct 01 2007 Page 56 of 1956 REJ09B0256 0100 ...
Page 144: ...Section 3 Instruction Set Rev 1 00 Oct 01 2007 Page 78 of 1956 REJ09B0256 0100 ...
Page 170: ...Section 4 Pipelining Rev 1 00 Oct 01 2007 Page 104 of 1956 REJ09B0256 0100 ...
Page 282: ...Section 7 Caches Rev 1 00 Oct 01 2007 Page 216 of 1956 REJ09B0256 0100 ...
Page 378: ...Section 9 Interrupt Controller INTC Rev 1 00 Oct 01 2007 Page 312 of 1956 REJ09B0256 0100 ...
Page 514: ...Section 12 DDR SDRAM Interface DDRIF Rev 1 00 Oct 01 2007 Page 448 of 1956 REJ09B0256 0100 ...
Page 630: ...Section 13 PCI Controller PCIC Rev 1 00 Oct 01 2007 Page 564 of 1956 REJ09B0256 0100 ...
Page 710: ...Section 16 Clock Pulse Generator CPG Rev 1 00 Oct 01 2007 Page 644 of 1956 REJ09B0256 0100 ...
Page 732: ...Section 17 Watchdog Timer and Reset WDT Rev 1 00 Oct 01 2007 Page 666 of 1956 REJ09B0256 0100 ...
Page 752: ...Section 18 Power Down Mode Rev 1 00 Oct 01 2007 Page 686 of 1956 REJ09B0256 0100 ...
Page 772: ...Section 19 Timer Unit TMU Rev 1 00 Oct 01 2007 Page 706 of 1956 REJ09B0256 0100 ...
Page 824: ...Section 21 Compare Match Timer CMT Rev 1 00 Oct 01 2007 Page 758 of 1956 REJ09B0256 0100 ...
Page 1124: ...Section 26 I 2 C Bus Interface IIC Rev 1 00 Oct 01 2007 Page 1058 of 1956 REJ09B0256 0100 ...
Page 1350: ...Section 30 SIM Card Module SIM Rev 1 00 Oct 01 2007 Page 1284 of 1956 REJ09B0256 0100 ...
Page 1484: ...Section 33 Audio Codec Interface HAC Rev 1 00 Oct 01 2007 Page 1418 of 1956 REJ09B0256 0100 ...
Page 1560: ...Section 35 USB Host Controller USBH Rev 1 00 Oct 01 2007 Page 1494 of 1956 REJ09B0256 0100 ...
Page 1720: ...Section 37 LCD Controller LCDC Rev 1 00 Oct 01 2007 Page 1654 of 1956 REJ09B0256 0100 ...
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