Section 37 LCD Controller (LCDC)
Rev. 1.00 Oct. 01, 2007 Page 1615 of 1956
REJ09B0256-0100
Bit
Bit Name
Initial Value R/W
Description
6
VCPE
0
R/W
LCD_VCPWC Pin Enable
Sets whether or not to enable a power-supply
control sequence using the LCD_VCPWC pin.
0: Disabled: LCD_VCPWC pin is masked and fixed
low
1: Enabled: LCD_VCPWC pin output is asserted
and negated according to the power-on or power-
off sequence
5
VEPE
0
R/W
LCD_VEPWC Pin Enable
Sets whether or not to enable a power-supply
control sequence using the LCD_VEPWC pin.
0: Disabled: LCD_VEPWC pin is masked and fixed
low
1: Enabled: LCD_VEPWC pin output is asserted
and negated according to the power-on or power-
off sequence
4 DONE
1
R/W
LCD_DON
Pin
Enable
Sets whether or not to enable a power-supply
control sequence using the LCD_DON pin.
0: Disabled: LCD_DON pin is masked and fixed low
1: Enabled: LCD_DON pin output is asserted and
negated according to the power-on or power-off
sequence
3, 2
All
0 R
Reserved
These bits are always read as 0. The write value
should always be 0.
1, 0
LPS[1:0]
00
R
LCD Module Power-Supply Input State
Indicates the power-supply input state of the LCD
module when using the power-supply control
function.
0: LCD module power off
1: LCD module power on
Summary of Contents for SH7763
Page 2: ...Rev 1 00 Oct 01 2007 Page ii of lxvi ...
Page 122: ...Section 2 Programming Model Rev 1 00 Oct 01 2007 Page 56 of 1956 REJ09B0256 0100 ...
Page 144: ...Section 3 Instruction Set Rev 1 00 Oct 01 2007 Page 78 of 1956 REJ09B0256 0100 ...
Page 170: ...Section 4 Pipelining Rev 1 00 Oct 01 2007 Page 104 of 1956 REJ09B0256 0100 ...
Page 282: ...Section 7 Caches Rev 1 00 Oct 01 2007 Page 216 of 1956 REJ09B0256 0100 ...
Page 378: ...Section 9 Interrupt Controller INTC Rev 1 00 Oct 01 2007 Page 312 of 1956 REJ09B0256 0100 ...
Page 514: ...Section 12 DDR SDRAM Interface DDRIF Rev 1 00 Oct 01 2007 Page 448 of 1956 REJ09B0256 0100 ...
Page 630: ...Section 13 PCI Controller PCIC Rev 1 00 Oct 01 2007 Page 564 of 1956 REJ09B0256 0100 ...
Page 710: ...Section 16 Clock Pulse Generator CPG Rev 1 00 Oct 01 2007 Page 644 of 1956 REJ09B0256 0100 ...
Page 732: ...Section 17 Watchdog Timer and Reset WDT Rev 1 00 Oct 01 2007 Page 666 of 1956 REJ09B0256 0100 ...
Page 752: ...Section 18 Power Down Mode Rev 1 00 Oct 01 2007 Page 686 of 1956 REJ09B0256 0100 ...
Page 772: ...Section 19 Timer Unit TMU Rev 1 00 Oct 01 2007 Page 706 of 1956 REJ09B0256 0100 ...
Page 824: ...Section 21 Compare Match Timer CMT Rev 1 00 Oct 01 2007 Page 758 of 1956 REJ09B0256 0100 ...
Page 1124: ...Section 26 I 2 C Bus Interface IIC Rev 1 00 Oct 01 2007 Page 1058 of 1956 REJ09B0256 0100 ...
Page 1350: ...Section 30 SIM Card Module SIM Rev 1 00 Oct 01 2007 Page 1284 of 1956 REJ09B0256 0100 ...
Page 1484: ...Section 33 Audio Codec Interface HAC Rev 1 00 Oct 01 2007 Page 1418 of 1956 REJ09B0256 0100 ...
Page 1560: ...Section 35 USB Host Controller USBH Rev 1 00 Oct 01 2007 Page 1494 of 1956 REJ09B0256 0100 ...
Page 1720: ...Section 37 LCD Controller LCDC Rev 1 00 Oct 01 2007 Page 1654 of 1956 REJ09B0256 0100 ...
Page 2025: ......
Page 2026: ...SH7763 Hardware Manual ...