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Section 26 I

C Bus Interface (IIC)

Rev. 1.00 Oct. 01, 2007 Page 1034 of 1956

REJ09B0256-0100

26.3.3 Slave

Interrupt Enable Register (ICSIER)

BIt:

Initial value:

R/W:

R/W

SSRE

SDEE

SDTE

SDRE

SARE

−

Bit

Bit Name

Initial Value

R/W

Description

7 to 5

—

All 0

Reserved

The write value should always be 0.

SSRE

R/W

Slave Stop Received Interrupt Enable

0: Disables the SSR interrupt.

1: Enables the SSR interrupt.

SDEE

R/W

Slave Data Empty Interrupt Enable

0: Disables the SDE interrupt.

1: Enables the SDE interrupt.

SDTE

R/W

Slave Data Transmitted Interrupt Enable

0: Disables the SDT interrupt.

1: Enables the SDT interrupt.

SDRE

R/W

Slave Data Received Interrupt Enable

0: Disables the SDR interrupt.

1: Enables the SDR interrupt.

SARE

R/W

Slave Address Received Interrupt Enable

0: Disables the SAR interrupt.

1: Enables the SAR interrupt.

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Summary of Contents for SH7763

Page 1: ...Revision Date Oct 01 2007 32 SH7763 Hardware Manual Renesas 32 Bit RISC Microcomputer SuperHTM RISC Engine Family SH 4A Series R5S77630 Rev 1 00 REJ09B0256 0100 ...

Page 2: ...Rev 1 00 Oct 01 2007 Page ii of lxvi ...

Page 3: ...ity and reliability such as safety systems or equipment or systems for transportation and traffic healthcare combustion control aerospace and aeronautics nuclear power or undersea communication transmission If you are considering the use of our products for such purposes please contact a Renesas sales office beforehand Renesas shall have no liability for damages arising out of the uses set forth a...

Page 4: ...e register settings and the output state of each pin are also undefined Design your system so that it does not malfunction because of processing while it is in this undefined state For those products which have a reset function reset the LSI immediately after the power supply has been turned on 4 Prohibition of Access to Undefined or Reserved Addresses Note Access to undefined or reserved addresse...

Page 5: ...ules The configuration of the functional description of each module differs according to the module However the generic style includes the following items i Feature ii Input Output Pin iii Register Description iv Operation v Usage Note When designing an application system that includes this LSI take notes into account Each section includes notes in relation to the descriptions given and usage note...

Page 6: ...s logical circuits and microcomputers Objective This manual was written to explain the hardware functions and electrical characteristics of this LSI to the above users Notes on reading this manual In order to understand the overall functions of the chip Read the manual according to the contents This manual can be roughly categorized into parts on the CPU system control functions peripheral functio...

Page 7: ...nit DDR Double Data Rate DDRIF DDR SDRAM Interface DMA Direct Memory Access DMAC Direct Memory Access Controller FIFO First In First Out FPU Floating point Unit HAC Audio Codec H UDI User Debugging Interface INTC Interrupt Controller JTAG Joint Test Action Group LBSC Local Bus State Controller LRAM L Memory LRU Least Recently Used LSB Least Significant Bit MMCIF Multimedia Card Interface MMU Memor...

Page 8: ...nstruction Set Computer RTC Realtime Clock SCIF Serial Communication Interface with FIFO SIOF Serial Interface with FIFO SSI Serial Sound Interface TAP Test Access Port TLB Translation Lookaside Buffer TMU Timer Unit UART Universal Asynchronous Receiver Transmitter UBC User Break Controller WDT Watchdog Timer All trademarks and registered trademarks are the property of their respective owners ...

Page 9: ...Formats in Registers 52 2 5 Data Formats in Memory 52 2 6 Processing States 53 2 7 Usage Note 55 2 7 1 Notes on Self Modified Codes 55 Section 3 Instruction Set 57 3 1 Execution Environment 57 3 2 Addressing Modes 59 3 3 Instruction Set 64 Section 4 Pipelining 79 4 1 Pipelines 79 4 2 Parallel Executability 90 4 3 Issue Rates and Execution Cycles 94 Section 5 Exception Handling 105 5 1 Summary of E...

Page 10: ... Entry High Register PTEH 147 6 2 2 Page Table Entry Low Register PTEL 148 6 2 3 Translation Table Base Register TTB 149 6 2 4 TLB Exception Address Register TEA 149 6 2 5 MMU Control Register MMUCR 149 6 2 6 Physical Address Space Control Register PASCR 152 6 2 7 Instruction Re Fetch Inhibit Control Register IRMCR 153 6 3 TLB Functions 156 6 3 1 Unified TLB UTLB Configuration 156 6 3 2 Instructio...

Page 11: ...ration 182 6 7 6 Notes on Using 32 Bit Address Extended Mode 184 6 8 Usage Notes 186 Section 7 Caches 187 7 1 Features 187 7 2 Register Descriptions 190 7 2 1 Cache Control Register CCR 191 7 2 2 Queue Address Control Register 0 QACR0 193 7 2 3 Queue Address Control Register 1 QACR1 194 7 2 4 On Chip Memory Control Register RAMCR 195 7 3 Operand Cache Operation 197 7 3 1 Read Operation 197 7 3 2 P...

Page 12: ...e Address Register 1 LSA1 223 8 2 4 L Memory Transfer Destination Address Register 0 LDA0 225 8 2 5 L Memory Transfer Destination Address Register 1 LDA1 227 8 3 Operation 229 8 3 1 Access from the CPU and FPU 229 8 3 2 Access from the SuperHyway Bus Master Module 229 8 3 3 Block Transfer 229 8 4 L Memory Protective Functions 231 8 5 Usage Notes 232 8 5 1 Page Conflict 232 8 5 2 L Memory Coherency...

Page 13: ...r 11 Mask State is affected INT2A11 274 9 3 18 Interrupt Mask Register INT2MSKR 276 9 3 19 Interrupt Mask Register 1 INT2MSKR1 277 9 3 20 Interrupt Mask Clear Register INT2MSKCR 279 9 3 21 Interrupt Mask Clear Register 1 INT2MSKCR1 281 9 3 22 On chip Module Interrupt Source Registers INT2B0 to INT2B7 and INT2B9 to INT2B11 283 9 3 23 GPIO Interrupt Set Register INT2GPIC 289 9 4 Interrupt Sources 29...

Page 14: ...1 3 4 PCMCIA Support 329 11 4 Register Descriptions 333 11 4 1 Memory Address Map Select Register MMSELR 334 11 4 2 Bus Control Register BCR 336 11 4 3 CSn Bus Control Register CSnBCR 340 11 4 4 CSn Wait Control Register CSnWCR 346 11 4 5 CSn PCMCIA Control Register CSnPCR 351 11 5 Operation 356 11 5 1 Endian Access Size and Data Alignment 356 11 5 2 Areas 361 11 5 3 SRAM interface 365 11 5 4 Burs...

Page 15: ...Registers that Set DDR SDRAM Timing Restrictions 434 12 5 7 Operating Frequency 435 12 5 8 Note on Clock Stop 435 12 5 9 Using SCR to Issue REFA Commands Outside the Initialization Sequence 435 12 5 10 Note on Timing of Connected DDR SDRAM 435 12 5 11 Note on Setting Auto Refresh Interval 436 12 5 12 Address Multiplexing 436 12 5 13 DDR SDRAM Access Arbitration 436 12 5 14 Coherency When Accessing...

Page 16: ...R0 to TCR5 574 14 3 6 DMA Transfer Count Registers TCRB0 to TCRB3 575 14 3 7 DMA Channel Control Registers CHCR0 to CHCR5 576 14 3 8 DMA Operation Register DMAOR 584 14 3 9 DMA Extended Resource Selectors DMARS0 to DMARS2 587 14 4 Operation 591 14 4 1 DMA Transfer Requests 591 14 4 2 Channel Priority 595 14 4 3 DMA Transfer Types 598 14 4 4 DMA Transfer Flow 606 14 4 5 Repeat Mode Transfer 608 14 ...

Page 17: ...R 641 16 5 Notes on Board Design 642 Section 17 Watchdog Timer and Reset WDT 645 17 1 Features 645 17 2 Input Output Pins 647 17 3 Register Descriptions 648 17 3 1 Watchdog Timer Stop Time Register WDTST 649 17 3 2 Watchdog Timer Control Status Register WDTCSR 650 17 3 3 Watchdog timer Base Stop Time Register WDTBST 652 17 3 4 Watchdog Timer Counter WDTCNT 653 17 3 5 Watchdog Timer Base Counter WD...

Page 18: ... 18 7 DDR SDRAM Power Supply Backup 681 18 7 1 Control of Self Refresh and Initialization 681 18 7 2 DDR SDRAM Backup Sequence when Turning Off System Power Supply 682 18 8 RTC Power Supply Backup 684 18 8 1 Transition to RTC Power Supply Backup Mode 684 18 8 2 Canceling RTC Power Supply Backup Mode 684 18 9 STATUS Pin Signal Change Timing 685 18 9 1 Timing at Reset 685 18 9 2 Timing at Sleep Mode...

Page 19: ...mer General Registers TGR 727 20 3 8 Timer Start Register TSTR 728 20 4 Operation 729 20 4 1 Overview 729 20 4 2 Basic Functions 730 20 4 3 Buffer Operation 734 20 4 4 PWM Modes 737 20 4 5 Phase Counting Mode 740 20 5 Usage Notes 746 Section 21 Compare Match Timer CMT 747 21 1 Features 747 21 2 Register Descriptions 749 21 2 1 Compare Match Timer Start Register CMSTR 751 21 2 2 Compare Match Timer...

Page 20: ...12 Day of Week Alarm Register RWKAR 770 22 4 13 Day Alarm Register RDAYAR 771 22 4 14 Month Alarm Register RMONAR 772 22 4 15 RTC Control Register 1 RCR1 772 22 4 16 RTC Control Register 2 RCR2 774 22 4 17 RTC Control Register RCR3 and Year Alarm Register RYRAR 777 22 5 Operation 778 22 5 1 Time Setting Procedures 778 22 5 2 Time Reading Procedures 779 22 5 3 Alarm Function 780 22 6 Interrupts 781...

Page 21: ...SE Frame Register MPR 835 23 3 24 Automatic PAUSE Frame Retransmit Count Register TPAUSER 836 23 3 25 PAUSE Frame Transmit Counter Register PFTCR 837 23 3 26 PAUSE Frame Receive Counter Register PFRCR 838 23 3 27 GETHER Mode Register GECMR 839 23 3 28 Burst Cycle Count Upper Limit Register BCULR 840 23 3 29 TSU Counter Reset Register TSU_CTRST 841 23 3 30 Relay Enable Register Port 0 to 1 TSU_FWEN...

Page 22: ...roneous Transmission TXALCR0 892 23 3 58 Receive Frame Counter Register Port 0 Normal Reception Only RXNLCR0 893 23 3 59 Receive Frame Counter Register Port 0 Normal and Erroneous Reception RXALCR0 894 23 3 60 Relay Frame Counter Register Port 1 to 0 Normal Relay Only FWNLCR0 895 23 3 61 Relay Frame Counter Register Port 1 to 0 Normal and Erroneous Transmission FWALCR0 896 23 3 62 Transmit Frame C...

Page 23: ...r Finished Address Register TDFXR 931 23 3 86 Transmit Descriptor Final Flag Register TDFFR 932 23 3 87 Overflow Alert FIFO Threshold Register FCFTR 933 23 3 88 Receive Data Padding Insert Register RPADIR 935 23 4 Operation 936 23 4 1 Descriptors and Descriptor List 939 23 4 2 Transmission 956 23 4 3 Reception 962 23 4 4 Relay 968 23 4 5 CAM Function 969 23 4 6 Transmit Receive Processing of Multi...

Page 24: ...figuration for Stream Data Transmission Reception 1015 25 3 11 Stream Data Receive Operation 1016 25 3 12 Stream Data Transmit Operation 1020 Section 26 I 2 C Bus Interface IIC 1025 26 1 Features 1025 26 2 Input Output Pins 1026 26 3 Register Descriptions 1026 26 3 1 Slave Control Register ICSCR 1029 26 3 2 Slave Status Register ICSSR 1031 26 3 3 Slave Interrupt Enable Register ICSIER 1034 26 3 4 ...

Page 25: ... 1070 27 3 6 Serial Control Register SCSCR 1073 27 3 7 Serial Status Register SCFSR 1077 27 3 8 Bit Rate Register SCBRR 1083 27 3 9 FIFO Control Register SCFCR 1084 27 3 10 Transmit FIFO Data Count Register SCTFDR 1086 27 3 11 Receive FIFO Data Count Register SCRFDR 1086 27 3 12 Serial Port Register SCSPTR 1087 27 3 13 Line Status Register SCLSR 1090 27 3 14 Serial Error Register SCRER 1091 27 4 O...

Page 26: ...locked Synchronous Mode 1165 28 4 4 SCIF Interrupt Sources and the DMAC 1174 28 4 5 Usage Notes 1176 28 5 Infrared Data Communication Interface 1179 28 5 1 Infrared Data Communication Format 1179 28 5 2 Operation of Infrared Data Communication Interface 1180 28 6 Baud Rate Generator for External Clock BRG 1181 28 6 1 BRG Block Diagram 1181 28 6 2 Restrictions on the BRG 1182 Section 29 Serial I O ...

Page 27: ...put Output Pins 1243 30 3 Register Descriptions 1244 30 3 1 Serial Mode Register SCSMR 1246 30 3 2 Bit Rate Register SCBRR 1247 30 3 3 Serial Control Register SCSCR 1248 30 3 4 Transmit Shift Register SCTSR 1250 30 3 5 Transmit Data Register SCTDR 1251 30 3 6 Serial Status Register SCSSR 1252 30 3 7 Receive Shift Register SCRSR 1258 30 3 8 Receive Data Register SCRDR 1258 30 3 9 Smart Card Mode Re...

Page 28: ...nd 1 INTCR0 INTCR1 1310 31 3 13 Interrupt Status Registers 0 and 1 INTSTR0 INTSTR1 1312 31 3 14 Transfer Clock Control Register CLKON 1316 31 3 15 VDD Open Drain Control Register VDCNT 1317 31 3 16 Data Register DR 1318 31 3 17 FIFO Pointer Clear Register FIFOCLR 1318 31 3 18 DMA Control Register DMACR 1319 31 3 19 Interrupt Control Register 2 INTCR2 1320 31 3 20 Interrupt Status Register 2 INTSTR...

Page 29: ...Status Register HACCR 1394 33 3 2 Command Status Address Register HACCSAR 1396 33 3 3 Command Status Data Register HACCSDR 1398 33 3 4 PCM Left Channel Register HACPCML 1399 33 3 5 PCM Right Channel Register HACPCMR 1401 33 3 6 TX Interrupt Enable Register HACTIER 1402 33 3 7 TX Status Register HACTSR 1403 33 3 8 RX Interrupt Enable Register HACRIER 1405 33 3 9 RX Status Register HACRSR 1406 33 3 ...

Page 30: ...HcCommandStatus Register USBHCS 1465 35 3 4 HcInterruptStatus Register USBHIS 1466 35 3 5 HcInterruptEnable Register USBHIE 1468 35 3 6 HcInterruptDisable Register USBHID 1469 35 3 7 HcHCCA Register USBHHCCA 1471 35 3 8 HcPeriodCurrentED Register USBHPCED 1471 35 3 9 HcControlHeadED Register USBHCHED 1472 35 3 10 HcControlCurrentED Register USBHCCED 1472 35 3 11 HcBulkHeadED Register USBHBHED 1473...

Page 31: ...er 4 IFR4 1514 36 3 6 Interrupt Select Register 0 ISR0 1515 36 3 7 Interrupt Select Register 1 ISR1 1516 36 3 8 Interrupt Select Register 2 ISR2 1517 36 3 9 Interrupt Select Register 3 ISR3 1518 36 3 10 Interrupt Select Register 4 ISR4 1519 36 3 11 Interrupt Enable Register 0 IER0 1520 36 3 12 Interrupt Enable Register 1 IER1 1521 36 3 13 Interrupt Enable Register 2 IER2 1522 36 3 14 Interrupt Ena...

Page 32: ...able Disconnection 1560 36 4 3 EP1 Bulk Out Transfer Dual FIFOs 1566 36 4 4 EP2 Bulk In Transfer Dual FIFOs 1567 36 4 5 EP3 Interrupt In Transfer 1569 36 5 EP4 Isochronous Out Transfer 1570 36 6 EP5 Isochronous In Transfer 1573 36 7 Processing of USB Standard Commands and Class Vendor Commands 1576 36 7 1 Processing of Commands Transmitted by Control Transfer 1576 36 8 Stall Operations 1577 36 8 1...

Page 33: ...ster LDVTLNR 1608 37 3 14 LCDC Vertical Sync Signal Register LDVSYNR 1609 37 3 15 LCDC AC Modulation Signal Toggle Line Number Register LDACLNR 1610 37 3 16 LCDC Interrupt Control Register LDINTR 1611 37 3 17 LCDC Power Management Mode Register LDPMMR 1614 37 3 18 LCDC Power Supply Sequence Period Register LDPSPR 1616 37 3 19 LCDC Control Register LDCNTR 1618 37 3 20 LCDC User Specified Interrupt ...

Page 34: ...ltage 1671 38 7 2 Processing of Analog Input Pins 1671 38 7 3 Pck0 Clock and Clock Division Ratio Settings 1672 38 7 4 A D Conversion Stop 1672 Section 39 D A Converter DAC 1673 39 1 Features 1673 39 2 Input Output Pins 1674 39 3 Register Descriptions 1674 39 3 1 D A Data Registers 0 and 1 DADR0 DADR1 1675 39 3 2 D A Control Register DACR 1676 39 4 Operation 1677 39 5 Usage Notes 1678 Section 40 G...

Page 35: ...JDR 1730 40 2 26 Port K Data Register PKDR 1731 40 2 27 Port L Data Register PLDR 1732 40 2 28 Port M Data Register PMDR 1733 40 2 29 Port N Data Register PNDR 1734 40 2 30 Port O Data Register PODR 1735 40 2 31 Port I Pull Up Control Register PIPUPR 1736 40 2 32 Port J Pull Up Control Register PJPUPR 1737 40 2 33 Port K Pull Up Control Register PKPUPR 1738 40 2 34 Port L Pull Up Control Register ...

Page 36: ...ration Description 1781 41 3 1 Definition of Words Related to Accesses 1781 41 3 2 User Break Operation Sequence 1782 41 3 3 Instruction Fetch Cycle Break 1784 41 3 4 Operand Access Cycle Break 1785 41 3 5 Sequential Break 1787 41 3 6 Program Counter Value to be Saved 1788 41 4 User Break Debugging Support Function 1789 41 5 User Break Examples 1791 41 6 Usage Notes 1795 Section 42 User Debugging ...

Page 37: ...gnal Timing 1865 43 4 8 DMAC Module Signal Timing 1867 43 4 9 TMU Module Signal Timing 1868 43 4 10 16 bit Timer Pulse Unit TPU Timing 1869 43 4 11 GETHER Module Signal Timing 1870 43 4 12 Stream Interface Module Timing 1876 43 4 13 I2 C Bus Interface Timing 1880 43 4 14 SCIF Module Signal Timing 1882 43 4 15 SIOF Module Signal Timing 1884 43 4 16 SIM Module Signal Timing 1888 43 4 17 MMCIF Module...

Page 38: ...tion for Subroutine Return 1906 D List of Mode Control Pins and Schematic Diagram of External Cicuits 1907 E Notes on Board Design 1909 F Package Dimensions 1912 G Pin States 1913 H Handling of Unused Pins 1931 I Version Registers 1943 J Heat Radiation 1944 J 1 Heat Resistance Simulation Conditions 1944 J 2 Analysis Results of Heat Resistance Simulation 1945 Index 1947 ...

Page 39: ...atterns 2 82 Figure 4 2 Instruction Execution Patterns 3 83 Figure 4 2 Instruction Execution Patterns 4 84 Figure 4 2 Instruction Execution Patterns 5 85 Figure 4 2 Instruction Execution Patterns 6 86 Figure 4 2 Instruction Execution Patterns 7 87 Figure 4 2 Instruction Execution Patterns 8 88 Figure 4 2 Instruction Execution Patterns 9 89 Section 5 Exception Handling Figure 5 1 Instruction Execut...

Page 40: ...d IC Address Array 207 Figure 7 6 Memory Mapped IC Data Array 208 Figure 7 7 Memory Mapped OC Address Array 210 Figure 7 8 Memory Mapped OC Data Array 211 Figure 7 9 Store Queue Configuration 212 Section 9 Interrupt Controller INTC Figure 9 1 Block Diagram of INTC 234 Figure 9 2 Example of IRL Interrupt Connection 293 Figure 9 3 On chip Module Interrupt Priority 296 Figure 9 4 Interrupt Operation ...

Page 41: ...te Cycle IW 0 No External Wait 389 Figure 11 25 MPX Interface Timing 4 Single Write Cycle IW 1 One External Wait Inserted 390 Figure 11 26 MPX Interface Timing 5 Burst Read Cycle IW 0 No External Wait 391 Figure 11 27 MPX Interface Timing 6 Burst Read Cycle IW 0 External Wait Control 392 Figure 11 28 MPX Interface Timing 7 Burst Write Cycle IW 0 No External Wait 393 Figure 11 29 MPX Interface Timi...

Page 42: ...RIF Timing Precharge all Banks PREALL to Bank Activate ACT 444 Figure 12 12 Basic DDRIF Timing Mode Register Set MRS 445 Figure 12 13 Basic DDRIF Timing Auto Refresh REFA Enter Exit to Bank Activate ACT 446 Figure 12 14 Basic DDRIF Timing Self Refresh Entry from IDLE REFS Self Refresh Exit REFSX to Any Command Input 447 Section 13 PCI Controller PCIC Figure 13 1 PCIC Block Diagram 451 Figure 13 2 ...

Page 43: ...y Write Cycle in Host Bus Bridge Mode Burst 559 Figure 13 25 Master Write Cycle in Host Bus Bridge Mode Burst with stepping 560 Figure 13 26 Target Memory Read Cycle in Host Bus Bridge Mode Burst with stepping 561 Figure 13 27 Timing Example of Device REQm Not Executing REQ Negation and FRAME Assertion Simultaneously 562 Section 14 Direct Memory Access Controller DMAC Figure 14 1 Block Diagram of ...

Page 44: ...Using PLL or DLL Oscillator Circuit 643 Section 17 Watchdog Timer and Reset WDT Figure 17 1 System Block Diagram 646 Figure 17 2 WDT Counting Up Operation 657 Figure 17 3 STATUS Output during Power on 660 Figure 17 4 STATUS Output by Reset input during Normal Operation 661 Figure 17 5 STATUS Output by Reset input during Sleep Mode 661 Figure 17 6 STATUS Output by Watchdog timer overflow Power On R...

Page 45: ... 20 9 Example of Buffer Operation Setting Procedure 735 Figure 20 10 Example of Buffer Operation 736 Figure 20 11 Example of PWM Mode Setting Procedure 738 Figure 20 12 Example of PWM Mode Operation 1 739 Figure 20 13 Examples of PWM Mode Operation 2 739 Figure 20 14 Example of Phase Counting Mode Setting Procedure 741 Figure 20 15 Example of Phase Counting Mode 1 Operation 742 Figure 20 16 Exampl...

Page 46: ...th Qtag 983 Figure 23 17 MII Frame Transmit Timing Normal Transmission 984 Figure 23 18 MII Frame Transmit Timing Collision 984 Figure 23 19 MII Frame Transmit Timing Transmit Error 985 Figure 23 20 MII Frame Receive Timing Normal Reception 985 Figure 23 21 MII Frame Receive Timing Reception Error 1 985 Figure 23 22 MII Fame Receive Timing Reception Error 2 985 Figure 23 23 GMII MII Fame Receive T...

Page 47: ... 26 8 10 Bit Address Transmit Receive Combined Format 1049 Figure 26 9 Data Transmit Mode Operation Timing 1051 Figure 26 10 Data Receive Mode Operation Timing 1053 Section 27 Serial Communication Interface with FIFO SCIF Figure 27 1 Block Diagram of SCIF 1061 Figure 27 2 SCIFn_RTS Pin n 0 1 1062 Figure 27 3 SCIFn_CTS Pin n 0 1 1063 Figure 27 4 SCIFn_SCK Pin n 0 1 1064 Figure 27 5 SCIFn_TXD Pin n ...

Page 48: ...hronous Communication Example with 8 Bit Data Parity and Two Stop Bits 1155 Figure 28 6 Sample SCIF Initialization Flowchart 1158 Figure 28 7 Sample Serial Transmission Flowchart 1159 Figure 28 8 Sample SCIF Transmission Operation Example with 8 Bit Data Parity One Stop Bit 1161 Figure 28 9 Sample Serial Reception Flowchart 1 1162 Figure 28 10 Sample Serial Reception Flowchart 2 1163 Figure 28 11 ...

Page 49: ...38 Figure 29 17 Transmit and Receive Timing 16 Bit Stereo Data 2 1238 Figure 29 18 Transmit and Receive Timing 16 Bit Stereo Data 3 1239 Figure 29 19 Transmit and Receive Timing 16 Bit Stereo Data 4 1239 Figure 29 20 Transmit and Receive Timing 16 Bit Stereo Data 1240 Section 30 SIM Card Module SIM Figure 30 1 Smart Card Interface 1242 Figure 30 2 Data Format Used by Smart Card Interface 1266 Figu...

Page 50: ... Operational Flow for Commands with Read Data Open ended Multiblock Transfer 1339 Figure 31 12 1 Example of Operational Flow for Commands with Read Data Pre defined Multiblock Transfer 1340 Figure 31 12 2 Example of Operational Flow for Commands with Read Data Pre defined Multiblock Transfer 1341 Figure 31 13 Example of Command Sequence for Commands with Write Data Block Size FIFO Size 1343 Figure...

Page 51: ... Figure 32 9 Dynamic Bus Sizing Timing for PCMCIA I O Card Interface 1388 Section 33 Audio Codec Interface HAC Figure 33 1 Block Diagram 1392 Figure 33 2 AC97 Frame Slot Structure 1409 Figure 33 3 Initialization Sequence 1412 Figure 33 4 Sample Flowchart for Off Chip Codec Register Write 1413 Figure 33 5 Sample Flowchart for Off Chip Codec Register Read 1 1414 Figure 33 6 Sample Flowchart for Off ...

Page 52: ...troller USBF Figure 36 1 Block Diagram of USBF 1496 Figure 36 2 Example of Endpoint Configuration 1554 Figure 36 3 Cable Connection Operation 1559 Figure 36 4 Cable Disconnection Operation 1560 Figure 36 5 Setup Stage Operation 1561 Figure 36 6 Data Stage Control In Operation 1562 Figure 36 7 Data Stage Control Out Operation 1563 Figure 36 8 Status Stage Control In Operation 1564 Figure 36 9 Statu...

Page 53: ...7 15 Clock and LCD Data Signal Example STN Color 16 Bit Data Bus Module 1644 Figure 37 16 Clock and LCD Data Signal Example DSTN Monochrome 8 Bit Data Bus Module 1645 Figure 37 17 Clock and LCD Data Signal Example DSTN Monochrome 16 Bit Data Bus Module 1646 Figure 37 18 Clock and LCD Data Signal Example DSTN Color 8 Bit Data Bus Module 1647 Figure 37 19 Clock and LCD Data Signal Example DSTN Color...

Page 54: ...ing Time on Return from Standby NMI or IRQ 1837 Figure 43 8 Reset Input Timing 1837 Figure 43 9 Control Signal Timing 1838 Figure 43 10 Pin Drive Timing in Standby Mode 1839 Figure 43 11 SRAM Bus Cycle Basic Bus Cycle No Wait 1841 Figure 43 12 SRAM Bus Cycle Basic Bus Cycle One Wait only by Software 1842 Figure 43 13 SRAM Bus Cycle Basic Bus Cycle One Wait by Software One Wait by RDY RDY Signal is...

Page 55: ... Timing 1869 Figure 43 40 TPU Clock Input Timing 1869 Figure 43 41 MII Transmit Timing normal operation 1871 Figure 43 42 MII Receive Timing normal operation 1871 Figure 43 43 MII Receive Timing When an Error is Detected 1872 Figure 43 44 WOL Output Timing 1872 Figure 43 45 GMII Transmit Timing normal operation 1873 Figure 43 46 GMII Receive Timing normal operation 1873 Figure 43 47 GMII Receive T...

Page 56: ...ck Input Timing 1892 Figure 43 72 HAC Interface Module Signal Timing 1892 Figure 43 73 SSI Clock Input Output Timing 1893 Figure 43 74 SSI Transmit Timing 1 1893 Figure 43 75 SSI Transmit Timing 2 1894 Figure 43 76 SSI Receive Timing 1 1894 Figure 43 77 SSI Receive Timing 2 1894 Figure 43 78 USB Clock Timing 1895 Figure 43 79 LCDC Module Signal Timing 1897 Figure 43 80 GPIO Timing 1897 Figure 43 8...

Page 57: ...Table 3 8 Branch Instructions 72 Table 3 9 System Control Instructions 72 Table 3 10 Floating Point Single Precision Instructions 75 Table 3 11 Floating Point Double Precision Instructions 76 Table 3 12 Floating Point Control Instructions 76 Table 3 13 Floating Point Graphics Acceleration Instructions 77 Section 4 Pipelining Table 4 1 Representations of Instruction Execution Patterns 80 Table 4 2 ...

Page 58: ...g Sequence of IRQ7 IRL7 to IRQ0 IRL0 Pin Function 156 Section 10 SuperHyway Bus Bridge SBR Table 10 1 Register Configuration 316 Table 10 2 Register State in Each Operating Mode 316 Section 11 Local Bus State Controller LBSC Table 11 1 Pin Configuration 324 Table 11 2 LBSC External Memory Space Map 327 Table 11 3 Setting of bus width for area 0 330 Table 11 4 Correspondence between External Pin MD...

Page 59: ...in Configuration 81 Table 14 2 Register Configuration of DMAC 83 Table 14 3 State of Registers in Each Operating Mode 85 Table 14 4 Transfer Request Sources 103 Table 14 5 Setting External Request Mode with RS bit 105 Table 14 6 Selecting External Request Detection with DL DS Bits 106 Table 14 7 Selecting External Request Detection with DO Bit 106 Table 14 8 Selecting On Chip Peripheral Module Req...

Page 60: ... Operating Mode 656 Table 18 5 Pin Configuration 670 Section 19 Timer Unit TMU Table 19 1 Pin Configuration 675 Table 19 2 Register Configuration 676 Table 19 3 Register States in Each Operating Mode 677 Table 19 4 TMU Interrupt Sources 690 Section 20 16 Bit Timer Pulse Unit TPU Table 20 1 TPU Functions 694 Table 20 2 TPU Pin Configurations 696 Table 20 3 Register Configuration 697 Table 20 4 Regi...

Page 61: ...Table 23 6 Relay Frame Process With CAM 266 Table 23 7 List of GETHER Interrupts 271 Section 25 Stream Interface STIF Table 25 1 Pin Configuration 985 Table 25 2 Register Configuration 986 Table 25 3 Register States in Each Operating Mode 987 Section 26 I2 C Bus Interface IIC Table 26 1 Pin Configuration 80 Table 26 2 Register Configuration 80 Table 26 3 Register State in Each Operating Mode 82 Ta...

Page 62: ...07 Table 29 7 Frame Length 1207 Table 29 8 Audio Mode Specification for Transmit Data 1209 Table 29 9 Audio Mode Specification for Receive Data 1210 Table 29 10 Setting Number of Channels in Control Data 1211 Table 29 11 Conditions to Issue Transmit Request 1214 Table 29 12 Conditions to Issue Receive Request 1214 Table 29 13 Transmit and Receive Reset 1219 Table 29 14 SIOF Interrupt Sources 1220 ...

Page 63: ...ble 34 1 Pin Configuration 81 Table 34 2 Register Configuration 82 Table 34 3 Register State in Each Operating Mode 83 Table 34 4 Bus Formats of SSI Module 97 Table 34 5 Number of Padding Bits for Each Valid Configuration 101 Section 35 USB Host Controller USBH Table 35 1 USB Host Pin Assignment 1445 Table 35 2 Register Configuration 1446 Table 35 3 Register State in Each Operating Mode 1447 Secti...

Page 64: ...figuration 1660 Table 39 2 Register Configuration 1660 Table 39 3 Register State in Each Operating Mode 1660 Section 40 General Purpose I O GPIO Table 40 1 Multiplexed Pins Controlled by Port Control Registers 80 Table 40 2 Register Configuration 1 90 Table 40 3 Register States in Each Operating Mode 92 Section 41 User Break Controller UBC Table 41 1 Register Configuration 1747 Table 41 2 Register...

Page 65: ...hernet Controller Signal Timing GMII 126 Table 43 21 Ethernet Controller Signal Timing RMII 128 Table 43 22 STIF Clock Valid Reception Signal Timing 130 Table 43 23 STIF Clock Valid Transmission Signal Timing 131 Table 43 24 STIF Strobe Reception Signal Timing 132 Table 43 25 STIF Strobe Transmission Signal Timing 133 Table 43 26 I2 C Bus Interface Timing 134 Table 43 27 SCIF Module Signal Timing ...

Page 66: ...Rev 1 00 Oct 01 2007 Page lxvi of lxvi Table G 1 Pin States 89 Table H 1 Handling of Unused Pins 107 Table I 1 Register Configuration 119 Table J 1 Heat Resistance Simulation Results 121 ...

Page 67: ...With this LSI the on chip DMAC direct memory access controller permits high speed data transfer and the external memory access support function permits direct connection to various types of memory device Furthermore the LSI also incorporates powerful peripheral functions which are optimal for system configuration such as the LCD controller USB full speed host controller function controller PCI con...

Page 68: ...sters Four 32 bit system registers RISC type instruction set upward compatible with the SH 1 SH 2 SH 3 and SH 4 microcomputers Instruction length 16 bit fixed length for improved code efficiency Load store architecture Delayed branch instructions Instructions executed with conditions Instruction set based on the C language Super scalar which executes two instructions simultaneously including the F...

Page 69: ...ion register FPUL Supports FMAC multiply and accumulate instruction Supports FDIV divide and FSQRT square root instructions Supports FLDI0 FLDI1 load constant 0 1 instructions Instruction execution times Latency FADD FSUB 3 cycles single precision 5 cycles double precision Latency FMAC FMUL 5 cycles single precision 7 cycles double precision Pitch FADD FSUB 1 cycle single precision double precisio...

Page 70: ...replacement algorithms Contents of TLB are directly accessible through address mapping Cache memory Instruction cache IC 32 Kbyte 4 way set associative 32 byte block length Operand cache OC 32 Kbyte 4 way set associative 32 byte block length Selectable write method copy back or write through Storage queue 32 bytes 2 entries LRAM High speed memory 16 Kbytes Two independent read write ports 8 16 32 ...

Page 71: ...pheral bus 0 frequency 1 4 times the CPU clock 66 MHz max Peripheral bus 1 frequency 1 8 times the CPU clock 33 MHz max Support of power down modes Sleep mode Software standby mode Module standby mode RTC power supply backup mode DDR SDRAM power supply backup mode Single channel watchdog timer Interrupt controller INTC Direct jump mode SH4 compatible External interrupt pins NMI IRL7 to IRL0 IRQ7 t...

Page 72: ...ported bus width 8 16 or 32 bits Supported space Areas 0 to 2 and areas 4 to 6 Burst ROM interface Wait cycle insertion by register setting Number of bursts is specified by register setting Supported bus width 8 16 or 32 bits Supported space Areas 0 5 and 6 Interface for SRAM with byte selection Supports direct connection to SRAM with byte selection Supported space Areas 1 and 4 PCMCIA interface o...

Page 73: ...lel connection 1 Gbit DDR SDRAM 16 two chips in parallel connection PCI controller PCIC PCI controller Rev 2 2 compatible 32 bit bus 33 MHz 66 MHz Supports PCI master slave Supports the PCI host function Built in bus arbiter External input pin for clock exclusively used by the PCI bus Interrupt requests can be sent to CPU Direct memory access controller DMAC Six channels four channels support exte...

Page 74: ...nterface SCIF Each channel includes 64 byte transmit receive FIFOs Three channels SCIF0 SCIF1 SCIF2 Full duplex communication Modem control function RTS CTS available in asynchronous mode channels 0 and 1 Transmit receive clock source is selectable as either the internal clock from the baud rate generator or the clock externally input from the SCK pin Channel 2 includes an IrDA 1 0 compliant inter...

Page 75: ...Class Vector commands are processed on the microcomputer s firmware Transfer rate Full speed 12 Mbps only Audio codec interface HAC Digital interface for audio codec single channel Supports transmission reception for slot 1 to slot 4 Choice of 16 or 20 bit DMA transfer in transmission reception Supports various sampling rates by adjusting slot data Generates data ready data request overflow and un...

Page 76: ...ternal clock PC card controller PCC Supports control signals for one slot Compatible with the SH7709 when PCC operation is disabled two slots SIM card interface SIM One channel Conforms to the ISO 7816 3 data protocol T 0 T 1 Asynchronous half duplex character transmission protocol Data length 8 bits Parity bit generation and check Selectable output clock cycles per etu elementary time unit Select...

Page 77: ...rame and multi descriptors for one frame multi buffer transfer methods Transfer data width 32 bits Includes FIFOs 2 Kbytes for transmission 8 Kbytes for reception MAC Media Access Control Two channels GETHER0 GETHER1 Data frame composition decomposition IEEE802 3 2000 Edition compliant frame format Changeable transfer rate 10 100 or 1000 Mbps Full duplex half duplex transmission reception IEEE802 ...

Page 78: ...dicated DMAC for data transfer Interrupt requests to the CPU Package P FBGA2121 449 BGA 449 pin 21 21 mm Power supply voltage 3 3 V 0 3 V 1 25 V 0 1 V 2 5 V 0 2 V for DDR SDRAM Temperature range 20 to 75 C 2 Process 0 13 µm CMOS 5 metal layers Product lineup Abbrev Power Supply Operating Frequency Product Type Package R5S77630 R5S77630Y266BGV R5S77631 3 3 V 0 3 V 1 25 V 0 1 V 2 5 V 0 2 V 133 MHz R...

Page 79: ...rnal CPU interface RTC Realtime clock UBC User break controller H UDI User debugging interface GETHER Gigabit Ethernet controller SECURITY Security accelerator USBH USB host controller CPG WDT TPU CMT H UDI INTC DMAC 6 channels Internal bus for cache and RAM SuperHyway bus Peripheral bus 0 USBF USB function controller SCIF Serial communication interface with FIFO SIOF Serial I O with FIFO SSI Seri...

Page 80: ...Section 1 Overview Rev 1 00 Oct 01 2007 Page 14 of 1956 REJ09B0256 0100 1 3 Pin Arrangement Figure 1 2 shows the pin arrangement and table 1 2 lists the pin configuration of this LSI ...

Page 81: ... M_A5 VCCQ DDR VCCQ DDR VDD PTB2 AD11 PINT10 LCDM_D7 PTB3 AD9 PINT11 LCDM_D6 PTC0 AD10 MMC_DAT LCDM_D5 PTC3 AD8 MMC_ODMOD LCDM_D4 XTAL2 EXTAL2 XRTCSTBI VDD RTC Vss RTC VCCQ PTB6 CBE0 PINT14 LCDM_D3 PTB7 AD6 PINT15 LCDM_D2 PTC4 AD7 MMC_CMD LCDM_CL2 PTC6 AD5 LCDM_CL1 USBP USBM VCCQ VSSQ VSS VSSQ VCCQ PTC1 AD4 LCDM_D1 PTC2 AD2 LCDM_D0 PTC7 AD3 MMC_CLK PTA6 AD1 MMC_VDDON PTI2 ST0M_STARTI IIC0_SCL SIOF...

Page 82: ...s VCCQ_ DDR A12 XTAL2 O Crystal resonator for RTC VDD_RTC A13 USBM IO D VCCQ A14 PTI2 ST0M_STARTI IIC0_SCL SIOF1_RXD USB_OVRCRT USBF_VBUS I I IO I I I Port ST data sync IIC serial clock SIOF receive data USB over current detection USB cable connection monitor pin VCCQ A15 PTI0 STATUS0 ST1_CLK RMII0_MDC IO O IO O Port status 0 ST data clock RMII management data clock VCCQ A16 PTK4 ST1_D4 GET0_ERXD4...

Page 83: ...INT4 IO IO IO IO I I I Port data bus address and data bus ST data PHY interrupt RMII receive data port interrupt input VCCQ A23 CS0 O Chip select VCCQ A24 VSSQ I O GND A25 VSSQ I O GND B1 VCCQ DDR DDR SDRAM I O VCC B2 VSSQ DDR DDR SDRAM I O GND B3 M_BKPRST I DDR SDRAM power supply backup reset VCCQ_ DDR B4 M_CKE O DDR SDRAM clock enable VCCQ_ DDR B5 M_A13 O DDR SDRAM address bus VCCQ_ DDR B6 M_CAS...

Page 84: ... data LCD shift clock VCCQ B19 RDY EX_RDY PCC_WAIT I O I Ready external CPU ready PCMCIA hardware wait request VCCQ B20 CS2 EX_CS1 O I Chip select VCCQ B21 PTM7 D31 EX_AD31 ST0_D7 ET0_RX DV RMII0_TXD0 PINT7 IO IO IO IO I O I Port data bus address and data bus ST data ETHER receive data valid RMII transmit data port interrupt input VCCQ B22 PTM5 D29 EX_AD29 ST0_D5 ET0_RX ER RMII0_TXD_EN PINT5 IO IO...

Page 85: ...IO VCCQ C15 PTK6 ST1_D6 GET0_ERXD6 SIOF2_SCK LCD_VEPWC IO IO I IO O Port ST data ETHER receive data SIOF serial clock LCD power supply control VCCQ C16 PTI4 MD8 ST1_START ET1_PHY INT RMII0M0_MDC USB_PWREN USBF_UPLUP IO I IO I O O O Port mode control clock input mode ST data sync PHY interrupt RMII management data clock USB power supply enable USB Pull up control output pin VCCQ C17 PTJ7 INTB ST0M_...

Page 86: ... SDRAM data bus VCCQ_ DDR D3 VCCQ DDR DDR SDRAM I O VCC D4 VSSQ DDR DDR SDRAM I O GND D5 VSSQ DDR DDR SDRAM I O GND D6 VSSQ DDR DDR SDRAM I O GND D7 VCCQ DDR DDR SDRAM I O VCC D8 VCCQ DDR DDR SDRAM I O VCC D9 VSSQ DDR DDR SDRAM I O GND D10 VSSQ DDR DDR SDRAM I O GND D11 VCCQ DDR DDR SDRAM I O VCC D12 VDD RTC RTC VDD D13 VSSQ I O GND D14 VSSQ I O GND D15 PTK5 ST1_D5 GET0_ERXD5 SIOF2_RXD LCD_D7 IO I...

Page 87: ...EX_AD23 ST0_VALID ET0_TX EN TEND1 LCD_D15 IO IO IO IO O O O Port data bus address and data bus ST data valid ETHER transmit enable DMA transfer end LCD data VCCQ E1 M_D2 IO DDR SDRAM data bus VCCQ_ DDR E2 M_D17 IO DDR SDRAM data bus VCCQ_ DDR E3 M_D18 IO DDR SDRAM data bus VCCQ_ DDR E4 VCCQ DDR DDR SDRAM I O VCC E5 VCCQ DDR DDR SDRAM I O VCC E6 VSSQ DDR DDR SDRAM I O GND E7 VCCQ DDR DDR SDRAM I O ...

Page 88: ...ata bus ST data clock ETHER transmit data DMA transfer request LCD data VCCQ F1 M_D3 IO DDR SDRAM data bus VCCQ_ DDR F2 M_D19 IO DDR SDRAM data bus VCCQ_ DDR F3 M_D20 IO DDR SDRAM data bus VCCQ_ DDR F4 VSSQ DDR DDR SDRAM I O GND F5 VSSQ DDR DDR SDRAM I O GND F21 VSS Internal GND F22 PTK1 ST1_D1 GET0_ETXD5 SIOF1_TXD LCD_D3 IO IO O O O Port ST data ETHER transmit data SIOF transmit data LCD data VCC...

Page 89: ...ransfer end LCD data VCCQ G24 WE3 IOWR O O Data enable PCMCIA IOWR VCCQ G25 WE2 IORD O O Data enable PCMCIA IORD VCCQ H1 M_D5 IO DDR SDRAM data bus VCCQ_ DDR H2 M_D23 IO DDR SDRAM data bus VCCQ_ DDR H3 M_DQS2 IO DDR SDRAM data strobe VCCQ_ DDR H4 VSSQ DDR DDR SDRAM I O GND H5 VSSQ DDR DDR SDRAM I O GND H21 VCCQ I O VCC H22 PTL0 D16 EX_AD16 IRQ4 IRL4 ET0_COL DREQ0 LCD_D8 IO IO IO I I I I O Port dat...

Page 90: ...ress and data bus VCCQ J25 D12 EX_AD12 IO IO Data bus address and data bus VCCQ K1 M_DQM0 O DDR SDRAM data mask VCCQ_ DDR K2 M_DQS0 IO DDR SDRAM data strobe VCCQ_ DDR K3 M_DQS3 IO DDR SDRAM data strobe VCCQ_ DDR K4 VCCQ DDR DDR SDRAM I O VCC K5 VCCQ DDR DDR SDRAM I O VCC K10 VSS Internal GND K11 VSS Internal GND K12 VSS Internal GND K13 VSS Internal GND K14 VSS Internal GND K15 VSS Internal GND K1...

Page 91: ... L14 VSS Internal GND L15 VSS Internal GND L16 VSS Internal GND L21 VCCQ I O VCC L22 D3 EX_AD3 IO IO Data bus address and data bus VCCQ L23 D2 EX_AD2 IO IO Data bus address and data bus VCCQ L24 D9 EX_AD9 IO IO Data bus address and data bus VCCQ L25 D8 EX_AD8 IO IO Data bus address and data bus VCCQ M1 M_D8 IO DDR SDRAM data bus VCCQ_ DDR M2 M_D24 IO DDR SDRAM data bus VCCQ_ DDR M3 M_D25 IO DDR SD...

Page 92: ... bus VCCQ_ DDR N2 M_D26 IO DDR SDRAM data bus VCCQ_ DDR N3 M_D27 IO DDR SDRAM data bus VCCQ_ DDR N4 VCCQ DDR DDR SDRAM I O VCC N5 VCCQ DDR DDR SDRAM I O VCC N10 VSS Internal GND N11 VSS Internal GND N12 VSS Internal GND N13 VSS Internal GND N14 VSS Internal GND N15 VSS Internal GND N16 VSS Internal GND N21 VDD Internal VDD N22 RD FRAME EX_FRAME O O I Access cycle VCCQ N23 WE0 PCC_REG O O Data enab...

Page 93: ... P21 VSSQ I O GND P22 A9 O Address bus VCCQ P23 A8 O Address bus VCCQ P24 A3 O Address bus VCCQ P25 A2 O Address bus VCCQ R1 M_D11 IO DDR SDRAM data bus VCCQ_ DDR R2 M_D30 IO DDR SDRAM data bus VCCQ_ DDR R3 M_D31 IO DDR SDRAM data bus VCCQ_ DDR R4 VCCQ DDR DDR SDRAM I O VCC R5 VCCQ DDR DDR SDRAM I O VCC R10 VSS Internal GND R11 VSS Internal GND R12 VSS Internal GND R13 VSS Internal GND R14 VSS Int...

Page 94: ... VSS Internal GND T11 VSS Internal GND T12 VSS Internal GND T13 VSS Internal GND T14 VSS Internal GND T15 VSS Internal GND T16 AVss Analog GND T21 VSS Internal GND T22 A17 O Address bus VCCQ T23 A16 O Address bus VCCQ T24 A7 O Address bus VCCQ T25 A6 O Address bus VCCQ U1 M_D15 IO DDR SDRAM data bus VCCQ_ DDR U2 M_D14 IO DDR SDRAM data bus VCCQ_ DDR U3 VSSQ DDR DDR SDRAM I O GND U4 VSSQ DDR DDR SD...

Page 95: ...EQ3 ET1_ETXD2 IO I O Port PCI bus request ETHER transmit data VCCQ W4 PTF0 GNT0 GNTIN SIM_D ET1_ETXD3 DREQ3 IO IO I IO O I Port PCI bus grant SIM data ETHER transmit data DMA transfer request VCCQ W5 VDD Internal VDD W21 VDD Internal VDD W22 A25 EX_SIZE2 O I Address bus access size VCCQ W23 A24 EX_SIZE1 O I Address bus access size VCCQ W24 A23 EX_SIZE0 O I Address bus access size VCCQ W25 A22 O Ad...

Page 96: ...cc Y25 DA0 O Analog output AVcc AA1 PTF1 REQ0 REQOUT SIM_CLK ET1_MDC DACK3 IO IO O O O O Port PCI bus mastership request host PCI bus mastership request output SIM clock output ETHER management data clock DMA transfer request acknowledge VCCQ AA2 PTF2 AD31 SIM_RST ET1_MDIO TEND3 IO IO O IO O Port PCI address and data bus SIM reset ETHER management data IO DMA transfer end VCCQ AA3 PTG0 GNT1 ET1_WO...

Page 97: ... IO IO O Port PCI address and data bus ETHER transmit error VCCQ AB4 VSSQ I O GND AB5 VCCQ I O VCC AB6 PTE4 AD22 SCIF2_RXD GET1_ERXD4 SSI0_SDATA IO IO I I IO Port PCI address and data bus SCIF receive data GMII receive data SSI serial data IO VCCQ AB7 PTD5 AD18 PCC_CD2 GET1_ERXD6 SSI1_SDATA LCDM_D14 IO IO I I IO O Port PCI address and data bus PCMCIA CD2 GMII receive data SSI serial data IO LCD da...

Page 98: ...ror pin mode control endian switching VCCQ AB18 PTO2 AUDATA1 RMII0M1_MDC IO O O Port AUD data RMII management data clock VCCQ AB19 VSSQ I O GND AB20 TDO O H UDI data output VCCQ AB21 VSSQ I O GND AB22 VSSQ I O GND AB23 VCCQ I O VCC AB24 AN3 I Analog input AVcc AB25 AN2 I Analog input AVcc AC1 PTH6 AD27 TPU_TO2 ET1_CRS RMII1M_TXD_EN IO IO O I O Port PCI address and data bus TPU clock output ETHER c...

Page 99: ...CI address and data bus port interrupt input LCD data mirror pin VCCQ AC12 PTB7 AD6 PINT15 LCDM_D2 IO IO I O Port PCI address and data bus port interrupt input LCD data mirror pin VCCQ AC13 PTC2 AD2 LCDM_D0 IO IO O Port PCI address and data bus LCD data mirror pin VCCQ AC14 PTC5 AD0 MMC_CD LCDM_FLM IO IO I O Port PCI address and data bus MMC card detection LCD line marker mirror pin VCCQ AC15 PTN2...

Page 100: ...O IO I IO I O Port PCI initiator ready PCMCIA VS1 SIOF frame sync HAC serial data input LCD data mirror pin VCCQ AD8 PTA2 LOCK SCIF1_TXD IO IO O Port PCI lock SCIF transmit data VCCQ AD9 PTB1 SERR PINT9 LCDM_D9 IO IO I O Port PCI parity error port interrupt input LCD data mirror pin VCCQ AD10 PTB5 AD14 PINT13 LCDM_M_DISP IO IO I O Port PCI address and data bus port interrupt input LCD liquid cryst...

Page 101: ...5 AD23 TPU_TO1 ET1_ERXD1 RMII1M_TXD0 IO IO O I O Port PCI address and data bus TPU clock output ETHER receive data RMII transmit data mirror pin VCCQ AE5 PTH4 AD19 TPU_TO0 ET1_ERXD3 RMII1M_RXD0 IO IO O I I Port PCI address and data bus TPU clock output ETHER receive data RMII receive data mirror pin VCCQ AE6 PTD1 CBE2 PCC_VS2 SIOF0_TXD HAC_SD_OUT LCDM_D15 IO IO I O O O Port PCI command and byte en...

Page 102: ...XD MD3 IO I I Port SCIF receive data mode control bus width for area 0 VCCQ AE15 PTN4 SCIF0_RTS MD2 IO IO I Port SCIF modem control RTS mode control clock operating mode VCCQ AE16 PRESET I Power on reset VCCQ AE17 PTO1 AUDATA0 RMII1_MDIO SSI2_SDATA IO O IO IO Port AUD data RMII management data IO SSI serial data IO VCCQ AE18 PTO5 AUDCK DREQ1M SSI3_SDATA IO O I IO Port AUD clock DMA transfer reques...

Page 103: ... LSI has registers and data formats as shown below 2 1 Data Formats The data formats supported in this LSI are shown in figure 2 1 Byte 8 bits Word 16 bits Longword 32 bits Single precision floating point 32 bits Double precision floating point 64 bits 0 7 0 15 0 31 0 31 30 22 s e f 0 63 62 51 s e f Legend s e f Sign field Exponent field Fraction field Figure 2 1 Data Formats ...

Page 104: ... accessed only through the load control register LDC and store control register STC instructions When the RB bit is 1 that is when bank 1 is selected the 16 registers comprising bank 1 general registers R0_BANK1 to R7_BANK1 and non banked general registers R8 to R15 can be accessed as general registers R0 to R15 In this case the eight registers comprising bank 0 general registers R0_BANK0 to R7_BA...

Page 105: ...sters does not depend on the processing mode 5 Floating Point Registers and System Registers Related to FPU There are thirty two floating point registers FR0 FR15 and XF0 XF15 FR0 FR15 and XF0 XF15 can be assigned to either of two banks FPR0_BANK0 FPR15_BANK0 or FPR0_BANK1 FPR15_BANK1 FR0 FR15 can be used as the eight registers DR0 2 4 6 8 10 12 14 double precision floating point registers or pair...

Page 106: ...SK B 1111 reserved bits 0 others undefined GBR SSR SPC SGR DBR Undefined Control registers VBR H 00000000 MACH MACL PR Undefined System registers PC H A0000000 FR0 to FR15 XF0 to XF15 FPUL Undefined Floating point registers FPSCR H 00040001 Note Initialized by a power on reset and manual reset The CPU register configuration in each processing mode is shown in figure 2 2 User mode and privileged mo...

Page 107: ...2_BANK1 3 R3_BANK1 3 R4_BANK1 3 R5_BANK1 3 R6_BANK1 3 R7_BANK1 3 R8 R9 R10 R11 R12 R13 R14 R15 R0_BANK0 1 4 R1_BANK0 4 R2_BANK0 4 R3_BANK0 4 R4_BANK0 4 R5_BANK0 4 R6_BANK0 4 R7_BANK0 4 c Register configuration in privileged mode RB 0 GBR MACH MACL VBR PR SR SSR PC SPC SGR DBR SGR DBR R0 is used as the index register in indexed register indirect addressing mode and indexed GBR indirect addressing m...

Page 108: ...to R7 in user mode SR MD 0 Allocated to R0 to R7 when SR RB 0 in privileged mode SR MD 1 R0_BANK1 to R7_BANK1 Cannot be accessed in user mode Allocated to R0 to R7 when SR RB 1 in privileged mode SR MD 0 or SR MD 1 SR RB 0 R0_BANK0 R1_BANK0 R2_BANK0 R3_BANK0 R4_BANK0 R5_BANK0 R6_BANK0 R7_BANK0 R0_BANK0 R1_BANK0 R2_BANK0 R3_BANK0 R4_BANK0 R5_BANK0 R6_BANK0 R7_BANK0 R0_BANK1 R1_BANK1 R2_BANK1 R3_BAN...

Page 109: ... FPR15_BANK1 2 Single precision floating point registers FRi 16 registers When FPSCR FR 0 FR0 to FR15 are assigned to FPR0_BANK0 to FPR15_BANK0 when FPSCR FR 1 FR0 to FR15 are assigned to FPR0_BANK1 to FPR15_BANK1 3 Double precision floating point registers or single precision floating point registers DRi 8 registers A DR register comprises two FR registers DR0 FR0 FR1 DR2 FR2 FR3 DR4 FR4 FR5 DR6 ...

Page 110: ...XF8 XF9 XF10 XF11 XF12 XF13 XF14 XF15 FR0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11 FR12 FR13 FR14 FR15 DR0 DR2 DR4 DR6 DR8 DR10 DR12 DR14 FV0 FV4 FV8 FV12 XD0 XMTRX XD2 XD4 XD6 XD8 XD10 XD12 XD14 FPR0_BANK1 FPR1_BANK1 FPR2_BANK1 FPR3_BANK1 FPR4_BANK1 FPR5_BANK1 FPR6_BANK1 FPR7_BANK1 FPR8_BANK1 FPR9_BANK1 FPR10_BANK1 FPR11_BANK1 FPR12_BANK1 FPR13_BANK1 FPR14_BANK1 FPR15_BANK1 XF0 XF1 XF2 XF3 X...

Page 111: ...processing mode 0 User mode Some instructions cannot be executed and some resources cannot be accessed 1 Privileged mode This bit is set to 1 by an exception or interrupt 29 RB 1 R W Privileged Mode General Register Bank Specification Bit 0 R0_BANK0 to R7_BANK0 are accessed as general registers R0 to R7 and R0_BANK1 to R7_BANK1 can be accessed using LDC STC instructions 1 R0_BANK1 to R7_BANK1 are ...

Page 112: ...ing this bit see General Precautions on Handling of Product 9 M 0 R W M Bit Used by the DIV0S DIV0U and DIV1 instructions 8 Q 0 R W Q Bit Used by the DIV0S DIV0U and DIV1 instructions 7 to 4 IMASK All 1 R W Interrupt Mask Level Bits An interrupt whose priority is equal to or less than the value of the IMASK bits is masked It can be chosen by CPU operation mode register CPUOPM whether the level of ...

Page 113: ...g 6 Saved General Register 15 SGR 32 bits Privileged Mode Initial Value Undefined The contents of R15 are saved to SGR in the event of an exception or interrupt 7 Debug Base Register DBR 32 bits Privileged Mode Initial Value Undefined When the user break debugging function is enabled CBCR UBDE 1 DBR is referenced as the branch destination address of the user break handler instead of VBR 2 2 5 Syst...

Page 114: ...t Register Bank 0 FPR0_BANK0 to FPR15_BANK0 are assigned to FR0 to FR15 and FPR0_BANK1 to FPR15_BANK1 are assigned to XF0 to XF15 1 FPR0_BANK0 to FPR15_BANK0 are assigned to XF0 to XF15 and FPR0_BANK1 to FPR15_BANK1 are assigned to FR0 to FR15 20 SZ 0 R W Transfer Size Mode 0 Data size of FMOV instruction is 32 bits 1 Data size of FMOV instruction is a 32 bit register pair 64 bits For relationship...

Page 115: ...ag Field Each time an FPU operation instruction is executed the FPU exception cause field is cleared to 0 When an FPU exception occurs the bits corresponding to FPU exception cause field and flag field are set to 1 The FPU exception flag field remains set to 1 until it is cleared to 0 by software For bit allocations of each field see table 2 2 1 0 RM 01 R W Rounding Mode These bits select the roun...

Page 116: ... can not be used 2 The bit location of DR register is used for double precision format when PR 1 In the case of 2 it is used when PR is changed from 0 to 1 Figure 2 5 Relationship between SZ bit and Endian Table 2 2 Bit Allocation for FPU Exception Handling Field Name FPU Error E Invalid Operation V Division by Zero Z Overflow O Underflow U Inexact I Cause FPU exception cause field Bit 17 Bit 16 B...

Page 117: ...of the TLB enables access to a memory mapped register The operation of an access to this area without using the address translation function of the MMU is not guaranteed H FC00 0000 to H FFFF FFFF Access to area H FC00 0000 to H FFFF FFFF in user mode will cause an address error Memory mapped registers can be referenced in user mode by means of access that involves address translation Note Do not ...

Page 118: ...gn extended before being loaded into a register A word operand must be accessed starting from a word boundary even address of a 2 byte unit address 2n and a longword operand starting from a longword boundary even address of a 4 byte unit address 4n An address error will result if this rule is not observed A byte operand can be accessed from any address Big endian or little endian byte order can be...

Page 119: ... state the CPU is reset The reset state is divided into the power on reset state and the manual reset In the power on reset state the internal state of the CPU and the on chip peripheral module registers are initialized In the manual reset state the internal state of the CPU and some registers of on chip peripheral modules are initialized For details see register descriptions for each section 2 In...

Page 120: ...6 0100 From any state when reset manual reset input Reset state Instruction execution state Sleep instruction execution Power down state Interrupt occurence Reset manual reset clearance Reset manual reset input Reset manual reset input Figure 2 8 Processing State Transitions ...

Page 121: ... address within the range where no address error exception occurs 2 In case the modified codes are in cacheable area write through SYNCO ICBI Rn The all instruction cache area corresponding to the modified codes should be invalidated by the ICBI instruction The ICBI instruction should be issued to each cache line One cache line is 32 bytes 3 In case the modified codes are in cacheable area copy ba...

Page 122: ...Section 2 Programming Model Rev 1 00 Oct 01 2007 Page 56 of 1956 REJ09B0256 0100 ...

Page 123: ...r bit manipulation operations such as logical AND that are executed directly in memory operands in an operation that requires memory access are loaded into registers and the operation is executed between the registers Delayed Branches Except for the two branch instructions BF and BT this LSI s branch instructions and RTE are delayed branches In a delayed branch the instruction following the branch...

Page 124: ...ification and in data access the MD bit is accessed after modification The other bits S T M Q FD BL and RB after modification are used for delay slot instruction execution The STC and STC L SR instructions access all SR bits after modification Constant Values An 8 bit constant value can be specified by the instruction code and an immediate value 16 bit and 32 bit constant values can be defined as ...

Page 125: ...Management Unit MMU Table 3 2 Addressing Modes and Effective Addresses Addressing Mode Instruction Format Effective Address Calculation Method Calculation Formula Register direct Rn Effective address is register Rn Operand is register Rn contents Register indirect Rn Effective address is register Rn contents Rn Rn Rn EA EA effective address Register indirect with post increment Rn Effective addres...

Page 126: ... Rn 1 2 4 8 Rn 1 2 4 8 Rn 1 2 4 8 Byte Rn 1 Rn Word Rn 2 Rn Longword Rn 4 Rn Quadword Rn 8 Rn Rn EA Instruction executed with Rn after calculation Register indirect with displacement disp 4 Rn Effective address is register Rn contents with 4 bit displacement disp added After disp is zero extended it is multiplied by 1 byte 2 word or 4 longword according to the operand size Rn Rn disp 1 2 4 1 2 4 d...

Page 127: ...disp 1 2 4 disp zero extended Byte GBR disp EA Word GBR disp 2 EA Longword GBR disp 4 EA Indexed GBR indirect R0 GBR Effective address is sum of register GBR and R0 contents GBR R0 GBR R0 GBR R0 EA PC relative with displacement disp 8 PC Effective address is PC 4 with 8 bit displacement disp added After disp is zero extended it is multiplied by 2 word or 4 longword according to the operand size Wi...

Page 128: ...with 8 bit displacement disp added after being sign extended and multiplied by 2 2 disp sign extended 4 PC PC 4 disp 2 PC 4 disp 2 Branch Target PC relative disp 12 Effective address is PC 4 with 12 bit displacement disp added after being sign extended and multiplied by 2 2 disp sign extended 4 PC PC 4 disp 2 PC 4 disp 2 Branch Target Rn Effective address is sum of PC 4 and Rn PC 4 Rn PC 4 Rn PC 4...

Page 129: ... immediate data imm of TRAPA instruction is zero extended and multiplied by 4 Note For the addressing modes below that use a displacement disp the assembler descriptions in this manual show the value before scaling 1 2 or 4 is performed according to the operand size This is done to clarify the operation of the LSI Refer to the relevant assembler notation rules for the actual assembler descriptions...

Page 130: ...m Immediate data disp Displacement Operation notation Transfer direction xx Memory operand M Q T SR flag bits Logical AND of individual bits Logical OR of individual bits Logical exclusive OR of individual bits Logical NOT of individual bits n n n bit shift Instruction code MSB LSB mmmm Register number Rm FRm nnnn Register number Rn FRn 0000 R0 FR0 0001 R1 FR1 1111 R15 FR15 mmm Register number DRm...

Page 131: ...tion Privileged mode Privileged means the instruction can only be executed in privileged mode T bit Value of T bit after instruction execution No change New New means the instruction which is newly added in this LSI Note Scaling 1 2 4 or 8 is executed according to the size of the instruction operand ...

Page 132: ...Rm Rn Rm Rn 0110nnnnmmmm0010 MOV B Rm Rn Rn 1 Rn Rm Rn 0010nnnnmmmm0100 MOV W Rm Rn Rn 2 Rn Rm Rn 0010nnnnmmmm0101 MOV L Rm Rn Rn 4 Rn Rm Rn 0010nnnnmmmm0110 MOV B Rm Rn Rm sign extension Rn Rm 1 Rm 0110nnnnmmmm0100 MOV W Rm Rn Rm sign extension Rn Rm 2 Rm 0110nnnnmmmm0101 MOV L Rm Rn Rm Rn Rm 4 Rm 0110nnnnmmmm0110 MOV B R0 disp Rn R0 disp Rn 10000000nnnndddd MOV W R0 disp Rn R0 disp 2 Rn 10000001...

Page 133: ...OV L disp GBR R0 disp 4 GBR R0 11000110dddddddd MOVA disp PC R 0 disp 4 PC H FFFF FFFC 4 R0 11000111dddddddd MOVCO L R0 Rn LDST T If T 1 R0 Rn 0 LDST 0000nnnn01110011 LDST New MOVLI L Rm R0 1 LDST Rm R0 When interrupt exception occurred 0 LDST 0000mmmm01100011 New MOVUA L Rm R0 Rm R0 Load non boundary alignment data 0100mmmm10101001 New MOVUA L Rm R0 Rm R0 Rm 4 Rm Load non boundary alignment data ...

Page 134: ...0 T 0011nnnnmmmm0010 Comparison result CMP GE Rm Rn When Rn Rm signed 1 T Otherwise 0 T 0011nnnnmmmm0011 Comparison result CMP HI Rm Rn When Rn Rm unsigned 1 T Otherwise 0 T 0011nnnnmmmm0110 Comparison result CMP GT Rm Rn When Rn Rm signed 1 T Otherwise 0 T 0011nnnnmmmm0111 Comparison result CMP PZ Rn When Rn 0 1 T Otherwise 0 T 0100nnnn00010001 Comparison result CMP PL Rn When Rn 0 1 T Otherwise ...

Page 135: ...mmmm1100 EXTU W Rm Rn Rm zero extended from word Rn 0110nnnnmmmm1101 MAC L Rm Rn Signed Rn Rm MAC MAC Rn 4 Rn Rm 4 Rm 32 32 64 64 bits 0000nnnnmmmm1111 MAC W Rm Rn Signed Rn Rm MAC MAC Rn 2 Rn Rm 2 Rm 16 16 64 64 bits 0100nnnnmmmm1111 MUL L Rm Rn Rn Rm MACL 32 32 32 bits 0000nnnnmmmm0111 MULS W Rm Rn Signed Rn Rm MACL 16 16 32 bits 0010nnnnmmmm1111 MULU W Rm Rn Unsigned Rn Rm MACL 16 16 32 bits 00...

Page 136: ...nnnmmmm1011 OR imm R0 R0 imm R0 11001011iiiiiiii OR B imm R0 GBR R0 GBR imm R0 GBR 11001111iiiiiiii TAS B Rn When Rn 0 1 T Otherwise 0 T In both cases 1 MSB of Rn 0100nnnn00011011 Test result TST Rm Rn Rn Rm when result 0 1 T Otherwise 0 T 0010nnnnmmmm1000 Test result TST imm R0 R0 imm when result 0 1 T Otherwise 0 T 11001000iiiiiiii Test result TST B imm R0 GBR R0 GBR imm when result 0 1 T Otherw...

Page 137: ...n00100101 LSB SHAD Rm Rn When Rm 0 Rn Rm Rn When Rm 0 Rn Rm MSB Rn 0100nnnnmmmm1100 SHAL Rn T Rn 0 0100nnnn00100000 MSB SHAR Rn MSB Rn T 0100nnnn00100001 LSB SHLD Rm Rn When Rm 0 Rn Rm Rn When Rm 0 Rn Rm 0 Rn 0100nnnnmmmm1101 SHLL Rn T Rn 0 0100nnnn00000000 MSB SHLR Rn 0 Rn T 0100nnnn00000001 LSB SHLL2 Rn Rn 2 Rn 0100nnnn00001000 SHLR2 Rn Rn 2 Rn 0100nnnn00001001 SHLL8 Rn Rn 8 Rn 0100nnnn00011000 ...

Page 138: ...n Delayed branch Rn PC 4 PC 0000nnnn00100011 BSR label Delayed branch PC 4 PR disp 2 PC 4 PC 1011dddddddddddd BSRF Rn Delayed branch PC 4 PR Rn PC 4 PC 0000nnnn00000011 JMP Rn Delayed branch Rn PC 0100nnnn00101011 JSR Rn Delayed branch PC 4 PR Rn PC 0100nnnn00001011 RTS Delayed branch PR PC 0000000000001011 Table 3 9 System Control Instructions Instruction Operation Instruction Code Privileged T B...

Page 139: ... LDC L Rm DBR Rm DBR Rm 4 Rm 0100mmmm11110110 Privileged LDC L Rm Rn_BANK Rm Rn_BANK Rm 4 Rm 0100mmmm1nnn0111 Privileged LDS Rm MACH Rm MACH 0100mmmm00001010 LDS Rm MACL Rm MACL 0100mmmm00011010 LDS Rm PR Rm PR 0100mmmm00101010 LDS L Rm MACH Rm MACH Rm 4 Rm 0100mmmm00000110 LDS L Rm MACL Rm MACL Rm 4 Rm 0100mmmm00010110 LDS L Rm PR Rm PR Rm 4 Rm 0100mmmm00100110 LDTLB PTEH PTEL TLB 000000000011100...

Page 140: ...Rn Rn 4 Rn GBR Rn 0100nnnn00010011 STC L VBR Rn Rn 4 Rn VBR Rn 0100nnnn00100011 Privileged STC L SSR Rn Rn 4 Rn SSR Rn 0100nnnn00110011 Privileged STC L SPC Rn Rn 4 Rn SPC Rn 0100nnnn01000011 Privileged STC L SGR Rn Rn 4 Rn SGR Rn 0100nnnn00110010 Privileged STC L DBR Rn Rn 4 Rn DBR Rn 0100nnnn11110010 Privileged STC L Rm_BANK Rn Rn 4 Rn Rm_BANK Rn m 0 to 7 0100nnnn1mmm0011 Privileged STS MACH Rn ...

Page 141: ... DRn 1111nnn0mmmm0110 FMOV Rm DRn Rm DRn Rm 8 Rm 1111nnn0mmmm1001 FMOV DRm Rn DRm Rn 1111nnnnmmm01010 FMOV DRm Rn Rn 8 Rn DRm Rn 1111nnnnmmm01011 FMOV DRm R0 Rn DRm R0 Rn 1111nnnnmmm00111 FLDS FRm FPUL FRm FPUL 1111mmmm00011101 FSTS FPUL FRn FPUL FRn 1111nnnn00001101 FABS FRn FRn H 7FFF FFFF FRn 1111nnnn01011101 FADD FRm FRn FRn FRm FRn 1111nnnnmmmm0000 FCMP EQ FRm FRn When FRn FRm 1 T Otherwise 0...

Page 142: ...FPUL DRn float_to_ double FPUL DRn 1111nnn010101101 FLOAT FPUL DRn float FPUL DRn 1111nnn000101101 FMUL DRm DRn DRn DRm DRn 1111nnn0mmm00010 FNEG DRn DRn H 8000 0000 0000 0000 DRn 1111nnn001001101 FSQRT DRn DRn DRn 1111nnn001101101 FSUB DRm DRn DRn DRm DRn 1111nnn0mmm00001 FTRC DRm FPUL long DRm FPUL 1111mmm000111101 Table 3 12 Floating Point Control Instructions Instruction Operation Instruction ...

Page 143: ...1111nnn1mmmm1001 FMOV R0 Rm XDn R0 Rm XDn 1111nnn1mmmm0110 FMOV XDm Rn XDm Rn 1111nnnnmmm11010 FMOV XDm Rn Rn 8 Rn XDm Rn 1111nnnnmmm11011 FMOV XDm R0 Rn XDm R0 Rn 1111nnnnmmm10111 FIPR FVm FVn inner_product FVm FVn FR n 3 1111nnmm11101101 FTRV XMTRX FVn transform_vector XMTRX FVn FVn 1111nn0111111101 FRCHG FPSCR FR FPSCR FR 1111101111111101 FSCHG FPSCR SZ FPSCR SZ 1111001111111101 FPCHG FPSCR PR ...

Page 144: ...Section 3 Instruction Set Rev 1 00 Oct 01 2007 Page 78 of 1956 REJ09B0256 0100 ...

Page 145: ...Address calculation I1 I2 ID E1 E2 E3 WB 2 General Load Store Pipeline 3 Special Pipeline 4 Special Load Store Pipeline 5 Floating Point Pipeline 6 Floating Point Extended Pipeline Instruction fetch Instruction decode Issue Operation Write back Operation Operation Register read Forwarding I1 I2 ID FS1 FS2 FS4 FS3 FS Operation Instruction fetch Instruction decode Issue Register read Forwarding Oper...

Page 146: ...tation Description E1 E2 E3 WB CPU EX pipe is occupied S1 S2 S3 WB CPU LS pipe is occupied with memory access s1 s2 s3 WB CPU LS pipe is occupied without memory access E1 S1 Either CPU EX pipe or CPU LS pipe is occupied E1S1 E1s1 Both CPU EX pipe and CPU LS pipe are occupied M2 M3 MS CPU MULT operation unit is occupied FE1 FE2 FE3 FE4 FE5 FE6 FS FPU EX pipe is occupied FS1 FS2 FS3 FS4 FS FPU LS pi...

Page 147: ... issue cycles I1 ID I2 Branch destination instruction Branch destination instruction I1 ID I2 Branch destination instruction Note Note I1 I2 ID s1 s2 s3 WB E2s2 ID E3s3 ID WB ID I1 ID I2 E1s1 I1 I2 ID S1 S2 S3 WB E1s1 E3s3 E2s2 E1s1 E1s1 E1s1 E1s1 E2s2 E2s2 E2s2 E2s2 E3s3 E3s3 E3s3 E3s3 WB WB WB WB E2s2 E3s3 WB E2s2 E3s3 WB E1s1 E1s1 I1 ID I2 ID ID ID ID ID ID ID WB I1 I2 ID S1 S2 S3 WB E1s1 E2s2 ...

Page 148: ...3 E1 s1 E2 s2 E3 S3 WB 2 2 1 step operation LS type 1 issue cycle 2 3 1 step operation MT type 1 issue cycle 2 4 MOV MT type 1 issue cycle EXT SU BW MOVT SWAP XTRCT ADD CMP DIV DT NEG SUB AND AND NOT OR OR TST TST XOR XOR ROT SHA SHL CLRS CLRT SETS SETT MOV NOP MOVA MOV Note Except for AND OR TST and XOR instructions using GBR relative addressing mode Figure 4 2 Instruction Execution Patterns 2 ...

Page 149: ...REFI 5 issue cycles 5 cycles 3 branch cycle 3 8 MOVLI L 1 issue cycle I1 I2 ID S1 S2 S3 WB 3 9 MOVCO L 1 issue cycle I1 I2 ID S1 S2 S3 WB 3 10 MOVUA L 2 issue cycles I1 I2 ID S1 S2 S3 WB S1 S2 S3 WB Branch to the next instruction of ICBI E2S2 E3S3 WB E1S1 ID ID E2S2 E3S3 WB E1S1 E2S2 E3S3 WB E1S1 ID ID ID I1 I2 ID s1 s2 s3 WB E1s1 E1s1 E1s1 E2s2 E2s2 E2s2 E3s3 E3s3 E3s3 WB WB WB I1 ID I2 ID ID ID ...

Page 150: ...es ID ID ID I1 I2 ID s1 s2 s3 WB I1 I2 ID S1 S2 S3 WB 4 5 LDC L to Rp_BANK SSR SPC VBR 1 issue cycle I1 I2 ID E1s1 E2s2 E3s3 WB ID ID ID 4 6 LDC L to DBR SGR 4 issue cycles 4 7 LDC L to GBR 1 issue cycle I1 I2 ID S1 S2 S3 WB ID ID ID I1 I2 ID E1S1 E2S2 E3S3 WB ID ID ID ID ID I1 I2 ID S1 S2 S3 WB 4 8 LDC L to SR 6 issue cycles 3 branch cycles I1 ID I2 Branch to the next instruction Branch to the ne...

Page 151: ...LDS to PR 1 issue cycle I1 I2 ID WB I1 I2 ID S1 S2 S3 E1S1 E2S2 E3S3 WB I1 I2 ID s1 s2 s3 WB 4 14 LDS L to PR 1 issue cycle I1 I2 ID s1 s2 s3 WB 4 15 STS from PR 1 issue cycle I1 I2 ID S1 S2 S3 WB 4 16 STS L from PR 1 issue cycle I1 I2 ID 1 2 3 WB 4 17 BSRF BSR JSR delay slot instructions PR set 0 issue cycle The value of PR is changed in the E3 stage of delay slot instruction When the STS and STS...

Page 152: ...ycle I1 I2 ID E1 M2 M3 E1 M2 M3 MS E1 M2 M3 MS M2 M3 MS 5 5 MULS W MULU W 1 issue cycle 5 6 DMULS L DMULU L MUL L 1 issue cycle 5 7 CLRMAC 1 issue cycle I1 I2 ID I1 I2 ID S1 S2 S3 WB S1 S2 S3 WB I1 I2 ID 5 8 MAC W 2 issue cycle 5 9 MAC L 2 issue cycle I1 I2 ID s1 s2 s3 WB MS I1 I2 ID S1 S2 S3 WB MS I1 I2 ID S1 S2 S3 WB MS M2 M3 MS M2 M3 MS M2 M3 I1 I2 ID S1 S2 S3 WB S1 S2 S3 WB ID ID Figure 4 2 In...

Page 153: ... to FPUL 1 issue cycle 6 4 STS L from FPUL 1 issue cycle 6 5 LDS to FPSCR 1 issue cycle 6 6 STS from FPSCR 1 issue cycle 6 7 LDS L to FPSCR 1 issue cycle 6 8 STS L from FPSCR 1 issue cycle 6 9 FPU load store instruction FMOV 1 issue cycle I1 I2 ID I1 I2 ID S1 S2 S3 WB S1 S2 S3 S1 S2 S3 WB I1 I2 ID s1 s2 s3 I1 I2 ID WB S1 S2 S3 WB FS3 S1 S2 S3 WB FS1 FS2 FS3 FS4 FS s1 s2 s3 WB I1 I2 ID 6 10 FLDS 1 ...

Page 154: ...nt computation 1 issue cycle 6 18 Double precision FDIV FSQRT 1 issue cycle I1 I2 ID s1 s2 s3 FS1 FS2 FS3 FS4 I1 I2 ID FE1 FE2 FE3 FE4 FE5 FE6 FS FEDS Divider occupied cycle FS FCMP EQ FCMP GT FADD FLOAT FMAC FMUL FSUB FTRC FRCHG FSCHG FPCHG FCMP EQ FCMP GT FADD FLOAT FSUB FTRC FCNVSD FCNVDS FMUL FEDS Divider occupied cycle I1 I2 ID FE1 FE2 FE3 FE4 FE5 FE6 FS I1 I2 ID FE1 FE2 FE3 FE4 FE5 FE6 FS FE...

Page 155: ...unit occupied cycle Function computing unit occupied cycle I1 I2 ID FE1 FE2 FE3 FE4 FE5 FE6 FS I1 I2 ID FE1 FE2 FE1 FE2 FE3 FE4 FE5 FE6 FS FE3 FE4 FE5 FE6 FS FE1 FE2 FE3 FE4 FE5 FE6 FS FE1 FE2 FE3 FE4 FE5 FE6 FS I1 I2 ID FE1 FE2 FE3 FEPL FE4 FE5 FE6 FS FEPL I1 I2 ID FE1 FE2 FE1 FE2 FE3 FE4 FE5 FE6 FS FE3 FE4 FE5 FE6 FS FE1 FE2 FE3 FE4 FE5 FE6 FS Figure 4 2 Instruction Execution Patterns 9 ...

Page 156: ... EX group and BRA in the BR group can be executed in parallel Table 4 2 Instruction Groups Instruction Group Instruction EX ADD ADDC ADDV AND imm R0 AND Rm Rn CLRMAC CLRS CLRT CMP DIV0S DIV0U DIV1 DMUS L DMULU L DT EXTS EXTU MOVT MUL L MULS W MULU W NEG NEGC NOT OR imm R0 OR Rm Rn ROTCL ROTCR ROTL ROTR SETS SETT SHAD SHAL SHAR SHLD SHLL SHLL2 SHLL8 SHLL16 SHLR SHLR2 SHLR8 SHLR16 SUB SUBC SUBV SWAP...

Page 157: ...BWB PREF STC CR2 Rn STC L CR2 Rn STS SR2 Rn STS L SR2 Rn STS SR1 Rn STS L SR1 Rn FE FADD FSUB FCMP S D FCNVDS FCNVSD FDIV FIPR FLOAT FMAC FMUL FRCHG FSCHG FSQRT FTRC FTRV FSCA FSRRA FPCHG CO AND B imm R0 GBR ICBI LDC Rm DBR LDC Rm SGR LDC Rm SR LDC L Rm DBR LDC L Rm SGR LDC L Rm SR LDTLB MAC L MAC W MOVCO MOVLI OR B imm R0 GBR PREFI RTE SLEEP STC SR Rn STC L SR Rn SYNCO TAS B TRAPA TST B imm R0 GB...

Page 158: ...owing instruction are specified within the minimum page size 1 Kbyte 2 The execution of these two instructions is supported in table 4 3 Combination of Preceding and Following Instructions 3 Data used by an instruction of addr does not conflict with data used by a previous instruction 4 Data used by an instruction of addr 2 does not conflict with data used by a previous instruction 5 Both instruct...

Page 159: ...I It is different from table 4 3 Preceding Instruction addr EX MT BR LS FLSR FLSM FE CO EX No Yes Yes Yes Yes Yes Yes No MT Yes Yes Yes Yes Yes Yes Yes No Following Instruction addr 2 BR Yes Yes No Yes Yes Yes Yes No LS Yes Yes Yes No Yes No Yes No FLSR Yes Yes Yes Yes No No No No FLSM Yes Yes Yes No No No Yes No FE Yes Yes Yes Yes No Yes No No CO No No No No No No No No Legend FLSR FABS FNEG FLDI...

Page 160: ...ion E1S1 I1 I2 ID S1 S2 S3 WB MS S2 S3 WB S1 ID ID ID I1 ID I2 Next instruction M3 M2 Issue rate 2 I1 ID I2 E g MAC W instruction Execution cycles indicates the cycle counts an instruction occupied the pipeline based on the next rules CPU instruction E g AND B instruction I1 I2 ID S1 S2 S3 WB Execution Cycles 3 E2S2 E3S3 WB E1S1 ID ID I1 I2 ID S1 S2 S3 WB MS S2 S3 WB S1 ID M3 M2 E g MAC W instruct...

Page 161: ... 3 1 9 MOV L disp PC Rn LS 1 1 3 1 10 MOV B Rm Rn LS 1 1 3 1 11 MOV W Rm Rn LS 1 1 3 1 12 MOV L Rm Rn LS 1 1 3 1 13 MOV B Rm Rn LS 1 1 3 1 14 MOV W Rm Rn LS 1 1 3 1 15 MOV L Rm Rn LS 1 1 3 1 16 MOV B disp Rm R0 LS 1 1 3 1 17 MOV W disp Rm R0 LS 1 1 3 1 18 MOV L disp Rm Rn LS 1 1 3 1 19 MOV B R0 Rm Rn LS 1 1 3 1 20 MOV W R0 Rm Rn LS 1 1 3 1 21 MOV L R0 Rm Rn LS 1 1 3 1 22 MOV B disp GBR R0 LS 1 1 3...

Page 162: ...sp GBR LS 1 1 3 1 39 MOV L R0 disp GBR LS 1 1 3 1 40 MOVCA L R0 Rn LS 1 1 3 4 41 MOVCO L R0 Rn CO 1 1 3 9 42 MOVLI L Rm R0 CO 1 1 3 8 43 MOVUA L Rm R0 LS 2 2 3 10 44 MOVUA L Rm R0 LS 2 2 3 10 45 MOVT Rn EX 1 1 2 1 46 OCBI Rn LS 1 1 3 4 47 OCBP Rn LS 1 1 3 4 48 OCBWB Rn LS 1 1 3 4 49 PREF Rn LS 1 1 3 4 50 SWAP B Rm Rn EX 1 1 2 1 51 SWAP W Rm Rn EX 1 1 2 1 Data transfer instructions 52 XTRCT Rm Rn E...

Page 163: ...LS L Rm Rn EX 1 2 5 6 70 DMULU L Rm Rn EX 1 2 5 6 71 DT Rn EX 1 1 2 1 72 MAC L Rm Rn CO 2 5 5 9 73 MAC W Rm Rn CO 2 4 5 8 74 MUL L Rm Rn EX 1 2 5 6 75 MULS W Rm Rn EX 1 1 5 5 76 MULU W Rm Rn EX 1 1 5 5 77 NEG Rm Rn EX 1 1 2 1 78 NEGC Rm Rn EX 1 1 2 1 79 SUB Rm Rn EX 1 1 2 1 80 SUBC Rm Rn EX 1 1 2 1 Fixed point arithmetic instructions 81 SUBV Rm Rn EX 1 1 2 1 82 AND Rm Rn EX 1 1 2 1 83 AND imm R0 E...

Page 164: ...CR Rn EX 1 1 2 1 100 SHAD Rm Rn EX 1 1 2 1 101 SHAL Rn EX 1 1 2 1 102 SHAR Rn EX 1 1 2 1 103 SHLD Rm Rn EX 1 1 2 1 104 SHLL Rn EX 1 1 2 1 105 SHLL2 Rn EX 1 1 2 1 106 SHLL8 Rn EX 1 1 2 1 107 SHLL16 Rn EX 1 1 2 1 108 SHLR Rn EX 1 1 2 1 109 SHLR2 Rn EX 1 1 2 1 110 SHLR8 Rn EX 1 1 2 1 Shift instructions 111 SHLR16 Rn EX 1 1 2 1 112 BF disp BR 1 0 to 2 1 1 1 113 BF S disp BR 1 0 to 2 1 1 1 114 BT disp ...

Page 165: ...O 5 5 3 10 3 7 131 SYNCO Rn CO Undefined Undefined 3 4 132 TRAPA imm CO 8 5 1 13 1 5 133 RTE CO 4 1 4 1 4 134 SLEEP CO Undefined Undefined 1 6 135 LDTLB CO 1 1 3 5 136 LDC Rm DBR CO 4 4 4 2 137 LDC Rm SGR CO 4 4 4 2 138 LDC Rm GBR LS 1 1 4 3 139 LDC Rm Rp_BANK LS 1 1 4 1 140 LDC Rm SR CO 4 3 4 4 4 141 LDC Rm SSR LS 1 1 4 1 142 LDC Rm SPC LS 1 1 4 1 143 LDC Rm VBR LS 1 1 4 1 144 LDC L Rm DBR CO 4 4...

Page 166: ...GR Rn LS 1 1 4 9 160 STC GBR Rn LS 1 1 4 9 161 STC Rp_BANK Rn LS 1 1 4 9 162 STC SR Rn CO 1 1 4 10 163 STC SSR Rn LS 1 1 4 9 164 STC SPC Rn LS 1 1 4 9 165 STC VBR Rn LS 1 1 4 9 166 STC L DBR Rn LS 1 1 4 11 167 STC L SGR Rn LS 1 1 4 11 168 STC L GBR Rn LS 1 1 4 11 169 STC L Rp_BANK Rn LS 1 1 4 11 170 STC L SR Rn CO 1 1 4 12 171 STC L SSR Rn LS 1 1 4 11 172 STC L SPC Rn LS 1 1 4 11 173 STC L VBR Rn ...

Page 167: ... FRm FPUL LS 1 1 6 10 190 FSTS FPUL FRn LS 1 1 6 11 191 FABS FRn LS 1 1 6 12 192 FADD FRm FRn FE 1 1 6 14 193 FCMP EQ FRm FRn FE 1 1 6 14 194 FCMP GT FRm FRn FE 1 1 6 14 195 FDIV FRm FRn FE 1 14 6 15 196 FLOAT FPUL FRn FE 1 1 6 14 197 FMAC FR0 FRm FRn FE 1 1 6 14 198 FMUL FRm FRn FE 1 1 6 14 199 FNEG FRn LS 1 1 6 12 200 FSQRT FRn FE 1 30 6 15 201 FSUB FRm FRn FE 1 1 6 14 202 FTRC FRm FPUL FE 1 1 6...

Page 168: ...1 30 6 18 221 FSUB DRm DRn FE 1 1 6 16 Double precision floating point instructions 222 FTRC DRm FPUL FE 1 1 6 16 223 LDS Rm FPUL LS 1 1 6 1 224 LDS Rm FPSCR LS 1 1 6 5 225 LDS L Rm FPUL LS 1 1 6 3 226 LDS L Rm FPSCR LS 1 1 6 7 227 STS FPUL Rn LS 1 1 6 2 228 STS FPSCR Rn LS 1 1 6 6 229 STS L FPUL Rn LS 1 1 6 4 FPU system control instructions 230 STS L FPSCR Rn LS 1 1 6 8 231 FMOV DRm XDn LS 1 1 6 ...

Page 169: ...ional Category No Instruction Instruction Group Issue Rate Execution Cycles Execution Pattern 241 FRCHG FE 1 1 6 14 242 FSCHG FE 1 1 6 14 243 FPCHG FE 1 1 6 14 244 FSRRA FRn FE 1 1 6 21 245 FSCA FPUL DRn FE 1 3 6 22 Graphics acceleration instructions 246 FTRV XMTRX FVn FE 1 4 6 20 ...

Page 170: ...Section 4 Pipelining Rev 1 00 Oct 01 2007 Page 104 of 1956 REJ09B0256 0100 ...

Page 171: ...handling in this LSI is of three kinds resets general exceptions and interrupts 5 2 Register Descriptions Table 5 1 lists the configuration of registers related exception handling Table 5 1 Register Configuration Register Name Abbr R W P4 Address Area 7 Address Access Size TRAPA exception register TRA R W H FF00 0020 H 1F00 0020 32 Exception event register EXPEVT R W H FF00 0024 H 1F00 0024 32 Int...

Page 172: ...6 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value R R R R R R R R R R R R R R R R R W R W R W TRACODE R W R W R W R R R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 R R R R R R R W R W Bit Bit Name Initial Value R W Description 31 to 10 All 0 R Reserved For details on reading writing this bit see General Precautions on Handling of Product 9 to 2 TRACODE Undefined...

Page 173: ...ware 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 Initial value R R R R R R R R R R R R R R R R R W R W EXPCODE R W R W R W R W R W R W R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 R R R R R W R W R W R W Bit Bit Name Initial Value R W Description 31 to 12 All 0 R Reserved For details on reading writing thi...

Page 174: ...27 26 25 24 23 22 21 20 19 18 17 16 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value R R R R R R R R R R R R R R R R R W INTCODE R W R W R W R W R W R W R W R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 R R R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 31 to 14 All 0 R Reserved For details on reading writing this bit see General Precautions on Handling o...

Page 175: ... Programming Model 1 The PC SR and R15 contents are saved in SPC SSR and SGR respectively 2 The block bit BL in SR is set to 1 3 The mode bit MD in SR is set to 1 4 The register bank bit RB in SR is set to 1 5 In a reset the FPU disable bit FD in SR is cleared to 0 6 The exception code is written to bits 11 to 0 of the exception event register EXPEVT or interrupt event register INTEVT 7 The CPU br...

Page 176: ...re instruction execution 1 2 0 VBR DBR H 100 H 1E0 Instruction address error 2 1 VBR H 100 H 0E0 Instruction TLB miss exception 2 2 VBR H 400 H 040 Instruction TLB protection violation exception 2 3 VBR H 100 H 0A0 General illegal instruction exception 2 4 VBR H 100 H 180 Slot illegal instruction exception 2 4 VBR H 100 H 1A0 General FPU disable exception 2 4 VBR H 100 H 800 Slot FPU disable excep...

Page 177: ...ak after instruction execution 1 2 10 VBR DBR H 100 H 1E0 Nonmaskable interrupt 3 VBR H 600 H 1C0 Interrupt Completion type General interrupt request 4 VBR H 600 Notes 1 When UBDE in CBCR 1 PC DBR In other cases PC VBR H 100 2 Priority is first assigned by priority level then by priority order within each level the lowest number represents the highest priority 3 Control passes to H A000 0000 in a ...

Page 178: ...ive priority order of the different kinds of exceptions reset general exception and interrupt Register settings in the event of an exception are shown only for SSR SPC SGR EXPEVT INTEVT SR and PC However other registers may be set automatically by hardware depending on the exception For details see section 5 6 Description of Exceptions Also see section 5 6 4 Priority Order with Multiple Exceptions...

Page 179: ... SGR R15 EXPEVT INTEVT exception code SR MD RB BL 111 SR IMASK received interuupt level PC CBCR UBDE 1 User_Break DBR VBR Offset Interrupt requested General exception requested Reset requested EXPEVT exception code SR MD RB BL FD IMASK 11101111 PC H A000 0000 Note When the exception of the highest priority is an interrupt Whether IMASK is updated or not can be set by software Figure 5 1 Instructio...

Page 180: ... an earlier instruction is accepted before that for a later instruction An example of the order of acceptance for general exceptions is shown in figure 5 2 I1 I1 ID ID E3 WB WB TLB miss data access Pipeline flow Order of detection Instruction n Instruction n 1 General illegal instruction exception instruction n 1 and TLB miss instruction n 2 are detected simultaneously Order of exception handling ...

Page 181: ...e interrupt request is held pending and is accepted after the BL bit has been cleared to 0 by software If a nonmaskable interrupt NMI occurs it can be held pending or accepted according to the setting made by software Thus normally SPC and SSR are saved and then the BL bit in SR is cleared to 0 to enable multiple exception state acceptance 5 5 4 Return from Exception Handling The RTE instruction i...

Page 182: ...ns A power on reset should be executed when power is supplied 2 Manual Reset Condition Manual reset request Operations Exception code H 020 is set in EXPEVT initialization of the CPU and on chip peripheral module is carried out and then a branch is made to the branch vector H A0000000 The registers initialized by a power on reset and manual reset are different For details see the register descript...

Page 183: ...pheral module initialization is performed in the same way as in a manual reset For details see the register descriptions in the relevant sections 5 Data TLB Multiple Hit Exception Source Multiple UTLB address matches Transition address H A0000000 Transition operations The virtual address 32 bits at which this exception occurred is set in TEA and the corresponding virtual page number 22 bits is set...

Page 184: ...s the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 040 for a read access or H 060 for a write access is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0400 To speed up TLB miss processing the offset is sep...

Page 185: ... 31 10 ASID in PTEH indicates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 40 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0400 To speed up TLB miss processing the offset is separate from that of ...

Page 186: ...irtual page number 22 bits is set in PTEH 31 10 ASID in PTEH indicates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 080 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 Initial_write_exception TE...

Page 187: ...ns The virtual address 32 bits at which this exception occurred is set in TEA and the corresponding virtual page number 22 bits is set in PTEH 31 10 ASID in PTEH indicates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 0A0 for a read access or ...

Page 188: ...s at which this exception occurred is set in TEA and the corresponding virtual page number 22 bits is set in PTEH 31 10 ASID in PTEH indicates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 0A0 is set in EXPEVT The BL MD and RB bits are set to ...

Page 189: ...ess VBR H 0000100 Transition operations The virtual address 32 bits at which this exception occurred is set in TEA and the corresponding virtual page number 22 bits is set in PTEH 31 10 ASID in PTEH indicates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Excep...

Page 190: ...eption occurred is set in TEA and the corresponding virtual page number 22 bits is set in PTEH 31 10 ASID in PTEH indicates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in the SPC and SSR The R15 contents at this time are saved in SGR Exception code H 0E0 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a b...

Page 191: ...truction following the TRAPA instruction are saved in SPC The value of SR and R15 when the TRAPA instruction is executed are saved in SSR and SGR The 8 bit immediate value in the TRAPA instruction is multiplied by 4 and the result is set in TRA 9 0 Exception code H 160 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 TRAPA_exception SPC PC 2 SSR SR SG...

Page 192: ...TC RTE LDTLB SLEEP but excluding LDC STC instructions that access GBR Transition address VBR H 00000100 Transition operations The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 180 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 Operation...

Page 193: ... delay slot Privileged instructions LDC STC RTE LDTLB SLEEP but excluding LDC STC instructions that access GBR Decoding of a PC relative MOV instruction or MOVA instruction in a delay slot Transition address VBR H 000 0100 Transition operations The PC contents for the preceding delayed branch instruction are saved in SPC The SR and R15 contents when this exception occurred are saved in SSR and SGR...

Page 194: ...d are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 800 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 Note FPU instructions are instructions in which the first 4 bits of the instruction code are F but excluding undefined instruction H FFFD and the LDS STS LDS L and STS L instructions corresponding to FPUL and ...

Page 195: ...100 Transition operations The PC contents for the preceding delayed branch instruction are saved in SPC The SR and R15 contents when this exception occurred are saved in SSR and SGR Exception code H 820 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 Slot_fpu_disable_exception SPC PC 2 SSR SR SGR R15 EXPEVT H 0000 0820 SR MD 1 SR RB 1 SR BL 1 PC VBR ...

Page 196: ...set are set in SPC In the case of a pre execution break the PC contents for the instruction at which the breakpoint is set are set in SPC The SR and R15 contents when the break occurred are saved in SSR and SGR Exception code H 1E0 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 It is also possible to branch to PC DBR For details of PC etc when a dat...

Page 197: ...0000100 Transition operations The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 120 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 FPU_exception SPC PC SSR SR SGR R15 EXPEVT H 0000 0120 SR MD 1 SR RB 1 SR BL 1 PC VBR H 0000 0100 ...

Page 198: ...d in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 1C0 is set in INTEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0600 When the BL bit in SR is 0 this interrupt is not masked by the interrupt mask bits in SR and is accepted at the highest priority level When the BL bit in SR is 1 a software setting can specify whether this interrupt is ...

Page 199: ...SR and SGR The code corresponding to the each interrupt source is set in INTEVT The BL MD and RB bits are set to 1 in SR and a branch is made to VBR H 0600 Module_interruption SPC PC SSR SR SGR R15 INTEVT H 0000 0400 H 0000 3FE0 SR MD 1 SR RB 1 SR BL 1 if cond SR IMASK level_of accepted_interrupt PC VBR H 0000 0600 5 6 4 Priority Order with Multiple Exceptions With some instructions such as instru...

Page 200: ...ruction has only one data transfer 1 A check is performed for the interrupt type and re execution type exceptions of priority levels 1 and 2 in the delayed branch instruction 2 A check is performed for the interrupt type and re execution type exceptions of priority levels 1 and 2 in the delay slot instruction 3 A check is performed for the completion type exception of priority level 2 in the delay...

Page 201: ...standby mode however an interrupt is accepted even if the BL bit in SR is set to 1 3 SPC when an exception occurs 1 Re execution type exception The PC value for the instruction at which the exception occurred is set in SPC and the instruction is re executed after returning from the exception handling routine If an exception occurs in a delay slot instruction however the PC value for the delayed br...

Page 202: ...egister value and accepting exception 1 When the MD or BL bit in the SR register is changed by the LDC instruction the acceptance of the exception is determined by the changed SR value starting from the next instruction In the completion type exception an exception is accepted after the next instruction has been executed However an interrupt of completion type exception is accepted before the next...

Page 203: ...sion arises 1 in figure 6 1 Having this mapping onto physical memory executed consciously by the process itself imposes a heavy burden on the process The virtual memory system was devised as a means of handling all physical memory mapping to reduce this burden 2 in figure 6 1 With a virtual memory system the size of the available virtual memory is much larger than the actual physical memory and pr...

Page 204: ...on lookaside buffer TLB is provided by hardware and frequently used address translation information is placed here The TLB can be described as a cache for address translation information However unlike a cache if address translation fails that is if an exception occurs switching of the address translation information is normally performed by software Thus memory management can be performed in a fl...

Page 205: ...9 of 1956 REJ09B0256 0100 MMU MMU Process 1 Physical Memory 1 0 2 3 4 Physical Memory Physical Memory Physical Memory Virtual Memory Virtual Memory Physical Memory Process 1 Process 1 Process 2 Process 3 Process 1 Process 1 Process 2 Process 3 Figure 6 1 Role of MMU ...

Page 206: ...rea and on chip memory area in user mode will cause an address error When the AT bit in MMUCR is set to 1 and the MMU is enabled the P0 P3 and U0 areas can be mapped onto any physical address space in 1 4 or 64 Kbyte or 1 Mbyte page units By using an 8 bit address space identifier the P0 P3 and U0 areas can be increased to a maximum of 256 Mapping from the virtual address space to the 29 bit physi...

Page 207: ...queue area P0 area Cacheable Address translation possible User mode Privileged mode P1 area Cacheable Address translation not possible P2 area Non cacheable Address translation not possible P3 area Cacheable Address translation possible P4 area Non cacheable Address translation not possible H 0000 0000 H 8000 0000 H E000 0000 H E400 0000 H E500 0000 H E600 0000 H FFFF FFFF H FFFF FFFF H 0000 0000 ...

Page 208: ...When the P0 P3 and U0 areas are mapped onto the control register area which is allocated in the area 7 in physical address space by means of the TLB the C bit for the corresponding page must be cleared to 0 P1 Area The P1 area does not allow address translation using the TLB but can be accessed using the cache Regardless of whether the MMU is enabled or disabled clearing the upper 3 bits of an add...

Page 209: ...ueues SQs In user mode the access right is specified by the SQMD bit in MMUCR For details see section 7 7 Store Queues The area from H E500 0000 to H E5FF FFFF comprises addresses for accessing the on chip memory In user mode the access right is specified by the RMD bit in RAMCR For details see section 8 L Memory The area from H F000 0000 to H F0FF FFFF is used for direct access to the instruction...

Page 210: ...ction 6 7 5 Memory Mapped PMB Configuration The area from H F710 0000 to H F71F FFFF is used for direct access to the PMB data array For details see section 6 7 5 Memory Mapped PMB Configuration The area from H FC00 0000 to H FFFF FFFF is the on chip peripheral module control register area For details see register descriptions in each section Physical Address Space This LSI supports a 29 bit physi...

Page 211: ...recorded in the TLB After the return from the exception handling routine the instruction which caused the TLB miss exception is re executed Single Virtual Memory Mode and Multiple Virtual Memory Mode There are two virtual memory systems single virtual memory and multiple virtual memory either of which can be selected with the SV bit in MMUCR In the single virtual memory system a number of processe...

Page 212: ...ibit control register IRMCR R W H FF00 0078 H 1F00 0078 32 Note These P4 addresses are for the P4 area in the virtual address space These area 7 addresses are accessed from area 7 in the physical address space by means of the TLB Table 6 2 Register States in Each Processing State Register Name Abbreviation Power on Reset Manual Reset Sleep Standby Page table entry high register PTEH Undefined Unde...

Page 213: ...nch using the RTE instruction In this case the branch destination may be the P0 P3 or U0 area 2 Execute the ICBI instruction for any address including non cacheable area 3 If the R2 bit in IRMCR is 0 initial value before updating the ASID field the specific instruction does not need to be executed However note that the CPU processing performance will be lowered because the instruction fetch is per...

Page 214: ...R1 PR0 SZ0 C D SH WT R W R W R W R W R W R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R R W R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 31 to 29 All 0 R Reserved For details on reading from or writing to these bits see description in General Precautions on Handling of Product 28 to 10 PPN R W Physical Page Number 9 0 R Reserved For details on reading from ...

Page 215: ...al address at which MMU exception or address error occurred 23 22 21 20 19 18 17 16 Bit Initial value R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W R W R W R W R W R W R W R W TEA TEA 6 2 5 MMU Control Register MMUCR The individual bits perform MMU settings as shown below Therefore...

Page 216: ...ed ITLB These bits indicate the ITLB entry to be replaced The LRU least recently used method is used to decide the ITLB entry to be replaced in the event of an ITLB miss The entry to be purged from the ITLB can be confirmed using the LRUI bits LRUI is updated by means of the algorithm shown below x means that updating is not performed 000xxx ITLB entry 0 is used 1xx00x ITLB entry 1 is used x1x1x0 ...

Page 217: ...formed with an LDTLB instruction This bit is incremented each time the UTLB is accessed If URB 0 URC is cleared to 0 when the condition URC URB is satisfied Also note that if a value is written to URC by software which results in the condition of URC URB incrementing is first performed in excess of URB until URC H 3F URC is not incremented by an LDTLB instruction 9 SQMD 0 R W Store Queue Mode Bit ...

Page 218: ... exceptions are not generated when the AT bit is 0 In the case of software that does not use the MMU the AT bit should be cleared to 0 6 2 6 Physical Address Space Control Register PASCR PASCR controls the operation in the physical address space 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value R R R R R R R R R R R R R R R R R W UB R W R...

Page 219: ...ea 3 UB 2 Corresponding to area 2 UB 1 Corresponding to area 1 UB 0 Corresponding to area 0 6 2 7 Instruction Re Fetch Inhibit Control Register IRMCR When the specific resource is changed IRMCR controls whether the instruction fetch is performed again for the next instruction The specific resource means the part of control registers TLB and cache In the initial state the instruction fetch is perfo...

Page 220: ...his bit controls whether re fetch is performed for the next instruction 0 Re fetch is performed 1 Re fetch is not performed 3 R1 0 R W Re Fetch Inhibit 1 after Register Change When a register allocated in addresses H FF200000 to H FF2FFFFF is changed this bit controls whether re fetch is performed for the next instruction 0 Re fetch is performed 1 Re fetch is not performed 2 LT 0 R W Re Fetch Inhi...

Page 221: ...it Bit Name Initial Value R W Description 0 MC 0 R W Re Fetch Inhibit after Writing Memory Mapped IC This bit controls whether re fetch is performed for the next instruction after writing memory mapped IC while the ICE bit in CCR is set to 1 0 Re fetch is performed 1 Re fetch is not performed ...

Page 222: ...onfiguration The UTLB consists of 64 fully associative type entries Figure 6 7 shows the relationship between the page size and address format PPN 28 10 PPN 28 10 PPN 28 10 SZ 1 0 SZ 1 0 SZ 1 0 SH SH SH C C C PR 1 0 PR 1 0 PR 1 0 ASID 7 0 ASID 7 0 ASID 7 0 VPN 31 10 VPN 31 10 VPN 31 10 V V V Entry 0 Entry 1 Entry 2 D D D WT WT WT PPN 28 10 SZ 1 0 SH C PR 1 0 ASID 7 0 VPN 31 10 V Entry 63 D WT Figu...

Page 223: ...age number Upper 22 bits of the physical address of the physical page number With a 1 Kbyte page PPN 28 10 are valid With a 4 Kbyte page PPN 28 12 are valid With a 64 Kbyte page PPN 28 16 are valid With a 1 Mbyte page PPN 28 20 are valid The synonym problem must be taken into account when setting the PPN see section 6 4 5 Avoiding Synonym Problems PR 1 0 Protection key data 2 bit data expressing t...

Page 224: ...rmed 1 Write has been performed WT Write through bit Specifies the cache write mode 0 Copy back mode 1 Write through mode 31 1 Kbyte page 10 9 0 Virtual address 31 4 Kbyte page 12 11 0 Virtual address 31 64 Kbyte page 16 15 0 Virtual address 31 1 Mbyte page 20 19 0 Virtual address VPN Offset VPN Offset VPN Offset VPN Offset 28 10 9 0 Physical address 28 12 11 0 Physical address 28 16 15 0 Physical...

Page 225: ...s cached into the ITLB Figure 6 8 shows the ITLB configuration The ITLB consists of four fully associative type entries PPN 28 10 PPN 28 10 PPN 28 10 PPN 28 10 SZ 1 0 SZ 1 0 SZ 1 0 SZ 1 0 SH SH SH SH C C C C PR PR PR PR ASID 7 0 ASID 7 0 ASID 7 0 ASID 7 0 VPN 31 10 VPN 31 10 VPN 31 10 VPN 31 10 V V V V Entry 0 Entry 1 Entry 2 Entry 3 Notes 1 The D and WT bits are not supported 2 There is only one ...

Page 226: ...CR OCE No Data access to virtual address VA VA is in P4 area VA is in P2 area VA is in P1 area VA is in P0 U0 or P3 area MMUCR AT 1 SH 0 and MMUCR SV 0 or SR MD 0 VPNs match ASIDs match and V 1 Only one entry matches 1 Privileged Data TLB multiple hit exception Data TLB protection violation exception Data TLB miss exception 0 User VPNs match and V 1 Data TLB protection violation exception Initial ...

Page 227: ...4 area VA is in P2 area VA is in P1 area VA is in P0 U0 or P3 area MMUCR AT 1 SH 0 and MMUCR SV 0 or SR MD 0 VPNs match and V 1 VPNs match ASIDs match and V 1 Only one entry matches SR MD Instruction TLB multiple hit exception 0 User 1 Privileged PR C 1 and CCR ICE 1 Cache access Memory access Non cacheable Instruction TLB protection violation exception Instruction TLB miss exception Hardware ITLB...

Page 228: ...rded in the ITLB in an instruction access the MMU searches the UTLB If the necessary address translation information is recorded in the UTLB the MMU copies this information into the ITLB in accordance with the LRUI bit setting in MMUCR 6 4 2 MMU Software Management Software processing for the MMU consists of the following 1 Setting of MMU related registers Some registers are also partially updated...

Page 229: ...ethods before an access include an instruction fetch the area where TLB is used to translate the address is performed 1 Execute a branch using the RTE instruction In this case the branch destination may be the area where TLB is used to translate the address 2 Execute the ICBI instruction for any address including non cacheable area 3 If the LT bit in IRMCR is 0 initial value before executing the L...

Page 230: ...PN 10 PPN Entry specification 31 26252423 18171615 10 9 8 7 3 2 1 0 LRUI URB URC SV TI AT SQMD Figure 6 11 Operation of LDTLB Instruction 6 4 4 Hardware ITLB Miss Handling In an instruction access this LSI searches the ITLB If it cannot find the necessary address translation information ITLB miss occurred the UTLB is searched by hardware and if the necessary address translation information is pres...

Page 231: ...differ from bits 12 to 10 of the virtual address Consequently the following restrictions apply to the recording of address translation information in UTLB entries When address translation information whereby a number of 1 Kbyte page UTLB entries are translated into the same physical address is recorded in the UTLB ensure that the VPN 12 10 values are the same When address translation information w...

Page 232: ...ual address to which an instruction access has been made If multiple hits occur when the UTLB is searched by hardware in hardware ITLB miss handling an instruction TLB multiple hit exception will result When an instruction TLB multiple hit exception occurs a reset is executed and cache coherency is not guaranteed Hardware Processing In the event of an instruction TLB multiple hit exception hardwar...

Page 233: ... saved in SGR 6 Sets the MD bit in SR to 1 and switches to privileged mode 7 Sets the BL bit in SR to 1 and masks subsequent exception requests 8 Sets the RB bit in SR to 1 9 Branches to the address obtained by adding offset H 0000 0400 to the contents of VBR and starts the instruction TLB miss exception handling routine Software Processing Instruction TLB Miss Exception Handling Routine Software ...

Page 234: ... code H 0A0 in EXPEVT 4 Sets the PC value indicating the address of the instruction at which the exception occurred in SPC If the exception occurred at a delay slot sets the PC value indicating the address of the delayed branch instruction in SPC 5 Sets the SR contents at the time of the exception in SSR The R15 contents at this time are saved in SGR 6 Sets the MD bit in SR to 1 and switches to pr...

Page 235: ...6 5 5 Data TLB Miss Exception A data TLB miss exception occurs when address translation information for the virtual address to which a data access is made is not found in the UTLB entries The data TLB miss exception processing carried out by hardware and software is shown below Hardware Processing In the event of a data TLB miss exception hardware carries out the following processing 1 Sets the VP...

Page 236: ...struction should be issued at least one instruction after the LDTLB instruction 6 5 6 Data TLB Protection Violation Exception A data TLB protection violation exception occurs when even though a UTLB entry contains address translation information matching the virtual address to which a data access is made the actual access type is not permitted by the access right specified by the PR bit The data T...

Page 237: ...dware Processing In the event of an initial page write exception hardware carries out the following processing 1 Sets the VPN of the virtual address at which the exception occurred in PTEH 2 Sets the virtual address at which the exception occurred in TEA 3 Sets exception code H 080 in EXPEVT 4 Sets the PC value indicating the address of the instruction at which the exception occurred in SPC If the...

Page 238: ...ng three methods before an access including an instruction fetch to an area other than the P2 area is performed 1 Execute a branch using the RTE instruction In this case the branch destination may be an area other than the P2 area 2 Execute the ICBI instruction for any address including non cacheable area 3 If the MT bit in IRMCR is 0 initial value before accessing the memory mapped TLB the specif...

Page 239: ...its 9 8 As only longword access is used 0 should be specified for address field bits 1 0 In the data field bits 31 10 indicate VPN bit 8 indicates V and bits 7 0 indicate ASID The following two kinds of operation can be used on the ITLB address array 1 ITLB address array read VPN V and ASID are read into the data field from the ITLB entry corresponding to the entry set in the address field 2 ITLB ...

Page 240: ... indicate PPN bit 8 indicates V bits 7 and 4 indicate SZ bit 6 indicates PR bit 3 indicates C and bit 1 indicates SH The following two kinds of operation can be used on ITLB data array 1 ITLB data array read PPN V SZ PR C and SH are read into the data field from the ITLB entry corresponding to the entry set in the address field 2 ITLB data array write PPN V SZ PR C and SH specified in the data fie...

Page 241: ...ponding to the entry set in the address field In a read associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0 2 UTLB address array write non associative VPN D V and ASID specified in the data field are written to the UTLB entry corresponding to the entry set in the address field The A bit in the address field should be cleared to ...

Page 242: ...when writing Information for selecting the entry to be accessed is specified in the address field and PPN V SZ PR C D SH and WT to be written to data array are specified in the data field In the address field bits 31 20 have the value H F70 indicating UTLB data array and the entry is specified by bits 13 8 In the data field bits 28 10 indicate PPN bit 8 indicates V bits 7 and 4 indicate SZ bits 6 ...

Page 243: ...0 0 0 0 E 19 20 8 7 14 13 0 0 Figure 6 15 Memory Mapped UTLB Data Array 6 7 32 Bit Address Extended Mode Setting the SE bit in PASCR to 1 changes mode from 29 bit address mode which handles the 29 bit physical address space to 32 bit address extended mode which handles the 32 bit physical address space P1 0 5GB P1 P2 1GB 0 5GB 4GB U0 P0 2GB U0 P0 2GB P2 0 5GB P3 0 5GB P3 0 5GB P4 0 5GB P4 0 5GB Vi...

Page 244: ...ting the SE bit in PASCR to 1 In 32 bit address extended mode the MMU operates as follows 1 When the AT bit in MMUCR is 0 virtual addresses in the U0 P0 or P3 area become 32 bit physical addresses Addresses in the P1 or P2 area are translated according to the PMB mapping information B 10 should be set to the upper 2 bits of virtual page number VPN 31 30 in the PMB in order to indicate P1 or P2 are...

Page 245: ...y 1 Entry 2 WT WT WT PPN 31 24 SZ 1 0 C UB VPN 31 24 V Entry 15 WT Figure 6 17 PMB Configuration Legend VPN Virtual page number For 16 Mbyte page Upper 8 bits of virtual address For 64 Mbyte page Upper 6 bits of virtual address For 128 Mbyte page Upper 5 bits of virtual address For 512 Mbyte page Upper 3 bits of virtual address Note B 10 should be set to the upper 2 bits of VPN in order to indicat...

Page 246: ...re valid With a 512 Mbyte page PPN 31 29 are valid C Cacheability bit Indicates whether a page is cacheable 0 Not cacheable 1 Cacheable WT Write through bit Specifies the cache write mode 0 Copy back mode 1 Write through mode UB Buffered write bit Specifies whether a buffered write is performed 0 Buffered write Data access of subsequent processing proceeds without waiting for the write to complete...

Page 247: ...the TEA and code H 140 in the EXPEVT 3 This LSI does not guarantee the operation when multiple hit occurs in the PMB Special care should be taken when the PMB mapping information is recorded by software 4 The PMB does not have an associative write function 5 Since there is no PR field in the PMB read write protection cannot be preformed The address translation target of the PMB is the P1 or P2 add...

Page 248: ...in the data field as V 2 PMB address array write When memory writing is performed while bits 31 to 20 in the address field are specified as H F61 which indicates the PMB address array and bits 11 to 8 in the address field as an entry and bits 31 to 24 in the data field are specified as VPN and bit 8 in the data field as V data is written to the specified entry 3 PMB data array read When memory rea...

Page 249: ... 1 0 0 E 23 24 12 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6 18 Memory Mapped PMB Address Array Address field Data field PPN V E SZ Physical page number Validity bit Entry Page size bits UB C WT Buffered write bit Cacheability bit Write through bit Reserved bits write value should be 0 and read value is undefined 31 2 1 0 V UB 10 9 8 7 4 3 6 5 C PPN 31 0 1 1 1 1 0 1 1 1 0 0 0 1 E 23 24 19 20 8 7 12 1...

Page 250: ...ed as a buffered write Bit Bit Name Initial Value R W Description 31 SE 0 R W 0 29 bit address mode 1 32 bit address extended mode 30 to 8 All 0 R Reserved For details on reading from or writing to these bits see description in General Precautions on Handling of Product 7 to 0 UB All 0 R W Buffered Write Control for Each Area 64 Mbytes When writing is performed without using the cache or in the ca...

Page 251: ...A0 LSA1 LDA0 LDA1 L0SADR L1SADR L0DADR and L1DADR fields are extended to bits 31 to 10 See section 8 2 2 L Memory Transfer Source Address Register 0 LSA0 section 8 2 3 L Memory Transfer Source Address Register 1 LSA1 section 8 2 4 L Memory Transfer Destination Address Register 0 LDA0 and section 8 2 5 L Memory Transfer Destination Address Register 1 LDA1 When using 32 bit address mode the followin...

Page 252: ...truction that has caused the TLB miss exception and records the page in which the TLB miss exception has occurred in the UTLB Specifies the protection key data that does not cause a protection violation exception in the protection violation exception handling routine to record the page in the UTLB and re executes the instruction that has caused the protection violation exception b Exclude the page...

Page 253: ...Capacity 32 Kbyte cache 32 Kbyte cache Type 4 way set associative virtual address index physical address tag 4 way set associative virtual address index physical address tag Line size 32 bytes 32 bytes Entries 256 entries way 256 entries way Write method Copy back write through selectable Replacement method LRU least recently used algorithm LRU least recently used algorithm Table 7 2 Store Queue F...

Page 254: ...y is comprising 256 cache lines Figure 7 2 shows the configuration of the instruction cache Comparison 31 5 4 2 LW0 32 bits LW1 32 bits LW2 32 bits LW3 32 bits LW4 32 bits LW5 32 bits LW6 32 bits LW7 32 bits 6 bits MMU 12 5 255 19 bits 1 bit 1 bit Tag U V Address array way 0 to way 3 Data array way 0 to way3 LRU Entry selection Longword LW selection Virtual address 3 8 22 19 0 Write data Read data...

Page 255: ...tialized by a power on or manual reset V bit validity bit Indicates that valid data is stored in the cache line When this bit is 1 the cache line data is valid The V bit is initialized to 0 by a power on reset but retains its value in a manual reset U bit dirty bit The U bit is set to 1 if data is written to the cache line while the cache is being used in copy back mode That is the U bit indicates...

Page 256: ... registers are related to cache Table 7 3 Register Configuration Register Name Abbreviation R W P4 Address Area 7 Address Size Cache control register CCR R W H FF00 001C H 1F00 001C 32 Queue address control register 0 QACR0 R W H FF00 0038 H 1F00 0038 32 Queue address control register 1 QACR1 R W H FF00 003C H 1F00 003C 32 On chip memory control register RAMCR R W H FF00 0074 H 1F00 0074 32 Note T...

Page 257: ... the CPU processing performance will be lowered because the instruction fetch is performed again for the next instruction after CCR has been updated Note that the method 3 may not be guaranteed in the future SuperH Series Therefore it is recommended that the method 1 or 2 should be used for being compatible with the future SuperH Series 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit 0 0 0 0 0...

Page 258: ...so 1 0 IC not used 1 IC used 7 to 4 All 0 R Reserved For details on reading from or writing to these bits see description in General Precautions on Handling of Product 3 OCI 0 R W OC Invalidation Bit When 1 is written to this bit the V and U bits of all OC entries are cleared to 0 This bit is always read as 0 2 CB 0 R W Copy Back Bit Indicates the P1 area cache write mode 0 Write through mode 1 Co...

Page 259: ...27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R W R W R W R R R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AREA0 Bit Bit Name Initial Value R W Description 31 to 5 All 0 R Reserved For details on reading from or writing to these bits see description in General ...

Page 260: ...0 0 0 0 0 0 0 R R R R R R R R R R R R W R W R W R R R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AREA1 Bit Bit Name Initial Value R W Description 31 to 5 All 0 R Reserved For details on reading from or writing to these bits see description in General Precautions on Handling of Product 4 to 2 AREA1 Undefined R W When the MMU is disabled these bits generate physical address bits 2...

Page 261: ... be executed However note that the CPU processing performance will be lowered because the instruction fetch is performed again for the next instruction after RAMCR has been updated Note that the method 3 may not be guaranteed in the future SuperH Series Therefore it is recommended that the method 1 or 2 should be used for being compatible with the future SuperH Series 31 30 29 28 27 26 25 24 23 22...

Page 262: ...tions 7 IC2W 0 R W IC Two Way Mode bit 0 IC is a four way operation 1 IC is a two way operation For details see section 7 4 3 IC Two Way Mode 6 OC2W 0 R W OC Two Way Mode bit 0 OC is a four way operation 1 OC is a two way operation For details see section 7 3 6 OC Two Way Mode 5 to 0 All 0 R Reserved For details on reading from or writing to these bits see description in General Precautions on Han...

Page 263: ...to replace using the LRU bits is 1 see No 5 3 Cache hit The data indexed by virtual address bits 4 0 is read from the data field of the cache line on the hitted way in accordance with the access size Then the LRU bits are updated to indicate the hitted way is the latest one 4 Cache miss no write back Data is read into the cache line on the way which is selected to replace from the physical address...

Page 264: ... bits on each way are read from the cache line indexed by virtual address bits 12 5 2 The tag read from each way is compared with bits 28 10 of the physical address resulting from virtual address translation by the MMU If there is a way whose tag matches and its V bit is 1 see No 3 If there is no way whose tag matches and the V bit is 1 and the U bit of the way which is selected to replace using t...

Page 265: ...ts 12 5 2 The tag read from each way is compared with bits 28 10 of the physical address resulting from virtual address translation by the MMU If there is a way whose tag matches and its V bit is 1 see No 3 for copy back and No 4 for write through I If there is no way whose tag matches and its V bit is 1 and the U bit of the way which is selected to replace using the LRU bits is 0 see No 5 for cop...

Page 266: ... data field of the cache line on the way which is selected to replace are saved in the write back buffer Then a data write in accordance with the access size is performed for the data field on the hit way which is indexed by virtual address bits 4 0 Then the data excluding the cache missed data which is written already is read into the cache line on the way which is selected to replace from the ph...

Page 267: ...te through mode or writing to a non cacheable area This allows the CPU to proceed to the next operation as soon as the write to the write through buffer is completed without waiting for completion of the write to external memory Physical address bits 28 0 LW1 LW0 Figure 7 4 Configuration of Write Through Buffer 7 3 6 OC Two Way Mode When the OC2W bit in RAMCR is set to 1 OC two way mode which only...

Page 268: ...exed by virtual address bits 4 2 is read as an instruction from the data field on the hit way The LRU bits are updated to indicate the way is the latest one 4 Cache miss Data is read into the cache line on the way which selected using LRU bits to replace from the physical address space corresponding to the virtual address Data reading is performed using the wraparound method in order from the quad...

Page 269: ...corresponding to the virtual address Data reading is performed using the wraparound method in order from the quad word data 8 bytes including the cache missed data In the prefetch opreration the CPU doesn t wait the data arrived While the one cache line of data is being read the CPU can execute the next processing When reading of one line of data is completed the tag corresponding to the physical ...

Page 270: ...e instruction OCBP Rn Operand cache invalidation with write back Operand cache write back instruction OCBWB Rn Operand cache write back Operand cache allocate instruction MOVCA L R0 Rn Operand cache allocation Instruction cache invalidate instruction ICBI Rn Instruction cache invalidation Operand access synchronization instruction SYNCO Wait for data transfer completion The operand cache can recei...

Page 271: ...try is not dirty it is no operation 7 5 2 Prefetch Operation This LSI supports a prefetch instruction to reduce the cache fill penalty incurred as the result of a cache miss If it is known that a cache miss will result from a read or write operation it is possible to fill the cache with data beforehand by means of the prefetch instruction to prevent a cache miss due to the read or write operation ...

Page 272: ...he future SuperH Series In privileged mode the OC contents can be read from or written to by a program in the P1 or P2 area by means of a MOV instruction Operation is not guaranteed if access is made from a program in another area The IC and OC are allocated to the P4 area in the virtual address space Only data accesses can be used on both the IC address array and data array and the OC address arr...

Page 273: ...he A bit in the address field set to 1 the tag in each way stored in the entry specified in the address field is compared with the tag specified in the data field The way numbers of bits 14 13 in the address field are not used If the MMU is enabled at this time comparison is performed after the virtual address specified by data field bits 31 10 has been translated to a physical address using the I...

Page 274: ...the entry As only longword access is used 0 should be specified for address field bits 1 0 The data field is used for the longword data specification The following two kinds of operation can be used on the IC data array 1 IC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the IC entry corresponding to the ...

Page 275: ...bit 1 and the V bit by bit 0 As the OC address array tag is 19 bits in length data field bits 31 29 are not used in the case of a write in which association is not performed Data field bits 31 29 are used for the virtual address specification only in the case of a write in which association is performed The following three kinds of operation can be used on the OC address array 1 OC address array r...

Page 276: ...med and the write is not executed Note This function may not be supported in the future SuperH Series Therefore it is recommended that the OCBI OCBP or OCBWB instruction should be used to operate the OC definitely by reporting data TLB miss exception Address field 31 23 5 4 3 2 1 0 1 1 1 1 0 1 0 0 Entry A Data field 31 10 9 1 0 V Tag 24 1312 14 15 2 U V U A Validity bit Dirty bit Association bit R...

Page 277: ... entry corresponding to the way and entry set in the address field 2 OC data array write The longword data specified in the data field is written for the data specified by the longword specification bits in the address field in the OC entry corresponding to the way and entry set in the address field This write does not set the U bit to 1 on the address array side Address field 31 23 5 4 3 2 1 0 1 ...

Page 278: ... 7 SQ1 SQ1 0 SQ1 1 SQ1 2 SQ1 3 SQ1 4 SQ1 5 SQ1 6 SQ1 7 4B 4B 4B 4B 4B 4B 4B 4B Figure 7 9 Store Queue Configuration 7 7 2 Writing to SQ A write to the SQs can be performed using a store instruction for addresses H E000 0000 to H E3FF FFFC in the P4 area A longword or quadword access size can be used The meanings of the address bits are as follows 31 26 111000 Store queue specification 25 6 Don t c...

Page 279: ...the same meaning as for normal address translation but the C and WT bits have no meaning with regard to this page When a prefetch instruction is issued for the SQ area address translation is performed and physical address bits 28 10 are generated in accordance with the SZ bit specification For physical address bits 9 5 the address prior to address translation is generated in the same way as when t...

Page 280: ...nd read type exception judgment for transfer from the SQs to external memory using a PREF instruction As a result a TLB miss exception or protection violation exception is generated as required However if SQ access is enabled in privileged mode only by the SQMD bit in MMUCR an address error will occur even if address translation is successful in user mode When MMU is disabled AT 0 in MMUCR Operati...

Page 281: ...follows 1 The tag bits 28 10 19 bits in the IC and OC are extended to bits 31 10 22 bits 2 An instruction which operates the IC a memory mapped IC access and writing to the ICI bit in CCR should be located in the P1 or P2 area The cacheable bit C bit in the corresponding entry in the PMB should be 0 3 Bits 4 2 3 bits for the AREA0 bit in QACR0 and the AREA1 bit in QACR1 are extended to bits 7 2 6 ...

Page 282: ...Section 7 Caches Rev 1 00 Oct 01 2007 Page 216 of 1956 REJ09B0256 0100 ...

Page 283: ... Size Two Pages Total Page 16 Kbytes Page 0 of L memory H E500E000 to H E500FFFF Page 1 of L memory H E5010000 to H E5011FFF Ports Each page has three independent read write ports and is connected to each bus The instruction bus is used when L memory is accessed through instruction fetch The operand bus is used when L memory is accessed through operand access The SuperHyway bus is used for L memor...

Page 284: ...ory transfer source address register 0 LSA0 R W H FF000050 H 1F000050 32 L memory transfer source address register 1 LSA1 R W H FF000054 H 1F000054 32 L memory transfer destination address register 0 LDA0 R W H FF000058 H 1F000058 32 L memory transfer destination address register 1 LDA1 R W H FF00005C H 1F00005C 32 Note The P4 address is the address used when using P4 area in the virtual address s...

Page 285: ...gister RAMCR H 00000000 H 00000000 Retained Retained L memory transfer source address register 0 LSA0 Undefined Undefined Retained Retained L memory transfer source address register 1 LSA1 Undefined Undefined Retained Retained L memory transfer destination address register 0 LDA0 Undefined Undefined Retained Retained L memory transfer destination address register 1 LDA1 Undefined Undefined Retaine...

Page 286: ...ecautions on Handling of Product 9 RMD 0 R W On Chip Memory Access Mode Specifies the right of access to the L memory from the virtual address space 0 An access in privileged mode is allowed An address error exception occurs in user mode 1 An access user privileged mode is allowed 8 RP 0 R W On Chip Memory Protection Enable Selects whether or not to use the protective functions using ITLB and UTLB...

Page 287: ...l value R R R R W R W R W R W R W R W R W L0SADR L0SADR L0SSZ R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 0 0 0 0 Initial value R W R W R W R W R W R W R R R R R W R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 31 to 29 All 0 R Reserved For read write in these bits refer General Precautions on Handling of Product 28 to 10 L0SADR Undefined R W L Memory ...

Page 288: ...ss is used as the transfer source physical address 1 The L0SADR value is used as the transfer source physical address Settable values 111111 Transfer source physical address is specified in 1 Kbyte units 111110 Transfer source physical address is specified in 2 Kbyte units 111100 Transfer source physical address is specified in 4 Kbyte units 111000 Transfer source physical address is specified in ...

Page 289: ... R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 0 0 0 0 Initial value R W R W R W R W R W R W R R R R R W R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 31 to 29 All 0 R Reserved For read write in these bits refer to General Precautions on Handling of Product 28 to 10 L1SADR Undefined R W L Memory Page 1 Block Transfer Source Address When MMUCR AT 0 or RAMCR RP 0 the...

Page 290: ...d address is used as the transfer source physical address 1 The L1SADR value is used as the transfer source physical address Settable values 111111 Transfer source physical address is specified in 1 Kbyte units 111110 Transfer source physical address is specified in 2 Kbyte units 111100 Transfer source physical address is specified in 4 Kbyte units 111000 Transfer source physical address is specif...

Page 291: ... W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 0 0 0 0 Initial value R W R W R W R W R W R W R R R R R W R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 31 to 29 All 0 R Reserved For read write in these bits refer to General Precautions on Handling of Product 28 to 10 L0DADR Undefined R W L Memory Page 0 Block Transfer Destination Address When MMUCR AT 0 or RAMCR RP 0 ...

Page 292: ...used as the transfer destination physical address 1 The L0DADR value is used as the transfer destination physical address Settable values 111111 Transfer destination physical address is specified in 1 Kbyte units 111110 Transfer destination physical address is specified in 2 Kbyte units 111100 Transfer destination physical address is specified in 4 Kbyte units 111000 Transfer destination physical ...

Page 293: ... W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 0 0 0 0 Initial value R W R W R W R W R W R W R R R R R W R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 31 to 29 All 0 R Reserved For read write in these bits refer to General Precautions on Handling of Product 28 to 10 L1DADR Undefined R W L Memory Page 1 Block Transfer Destination Address When MMUCR AT 0 or RAMCR RP 0 ...

Page 294: ...ed as the transfer destination physical address 1 The L1DADR value is used as the transfer destination physical address Settable values 111111 Transfer destination physical address is specified in 1 Kbyte units 111110 Transfer destination physical address is specified in 2 Kbyte units 111100 Transfer destination physical address is specified in 4 Kbyte units 111000 Transfer destination physical ad...

Page 295: ...address in the L memory area in the virtual address space Data can be transferred from the L memory to the external memory through a write back instruction OCBWB Block transfer from the L memory to the external memory begins when the OCBWB instruction is issued to the address in the L memory area in the virtual address space In either case transfer rate is fixed to 32 bytes Since the start address...

Page 296: ...ion or protection error exception occurs if necessary If an exception occurs the block transfer is inhibited 2 When MMU is Disabled MMUCR AT 0 or RAMCR RP 0 The transfer source physical address in block transfer to page 0 in the L memory is set in the L0SADR bits of the LSA0 register And the L0SSZ bits in the LSA0 register choose either the virtual addresses specified through the PRFF instruction ...

Page 297: ...ccess mode bit RMD and the on chip memory protection enable bit RP in the on chip memory control register RAMCR Protective functions for access from the CPU and FPU When RAMCR RMD 0 and the L memory is accessed in user mode it is determined to be an address error exception When MMUCR AT 1 and RAMCR RP 1 MMU exception and address error exception are checked in the L memory area which is a part of P...

Page 298: ...ency In order to allocate instructions in the L memory write an instruction to the L memory execute the following sequence then branch to the rewritten instruction SYNCO ICBI Rn In this case the target for the ICBI instruction can be any address L memory address may be possible within the range where no address error exception occurs and cache hit miss is possible 8 5 3 Sleep Mode The SuperHyway b...

Page 299: ...tes the NMI pin state By reading this bit in the interrupt exception handling routine the pin state can be checked enabling it to be used as a noise canceller NMI request masking when the block bit BL in the status register SR is set to 1 Whether to mask NMI requests when the BL bit in SR is set to 1 can be selected Extended function for SH 4A Automatically updates the IMASK bit in SR according to...

Page 300: ...l module interrupt RTC TMU SCIF IIC STIF TPU SIM CMT HAC SIOF MMCIF SSI ADC PCC USBH USBF GETHER LCDC SECURITY However SECURITY is incorporated only in the R5S77630 not in the R5S77631 Legend WDT Watch Dog Timer H UDI User Debugging interface DMAC Direct Memory Access Controller PCIC PCI controller INTPRI Interrupt priority Level Setting Register ICR0 ICR1 Interrupt Control Register 0 1 INT2PRI0 t...

Page 301: ...y executing a return from exception instruction RTE This instruction restores the PC and SR contents and returns control to the normal processing routine at the point at which the exception occurred The SGR contents are not written back to R15 with an RTE instruction 1 The PC SR and R15 contents are saved to SPC SSR and SGR respectively 2 The block BL bit in SR is set to 1 3 The mode MD bit in SR ...

Page 302: ...e Table 9 1 Interrupt Types Source Number of Sources Max Priority INTEVT Remarks NMI 1 H 1C0 IRL 7 4 pin H 0 External interrupts IRL interrupt 1 2 H 200 IRL 3 0 pin H 0 High IRL 7 4 pin H 1 H 220 IRL 3 0 pin H 1 IRL 7 4 pin H 2 H 240 IRL 3 0 pin H 2 IRL 7 4 pin H 3 H 260 IRL 3 0 pin H 3 IRL 7 4 pin H 4 Inversion values of input pin values because of negative pins For example IRL 7 4 pin H 0 means ...

Page 303: ...alues of input pin values because of negative pins For example IRL 7 4 pin H 0 means external pin input level is IRL 7 pin Low IRL 6 pin Low IRL 5 pin Low IRL 4 pin Low then priority level is 15 H F See table 9 6 H 3C0 IRL 3 0 pin H E 8 Values set in INTPRI H 240 IRQ 0 IRQ interrupt H 280 IRQ 1 H 2C0 IRQ 2 H 300 IRQ 3 H 340 IRQ 4 H 380 IRQ 5 H 3C0 IRQ 6 H 200 IRQ 7 Low RTC 3 H 480 ATI Setting valu...

Page 304: ...to INT2PRI13 H 680 DMTE2 H 6A0 DMTE3 H 6C0 DMAE SCIF0 4 H 700 ERI0 H 720 RXI0 H 740 BRI0 H 760 TXI0 DMAC 7 2 7 H 780 DMTE4 H 7A0 DMTE5 IIC0 1 H 8A0 IICI0 IIC1 1 H 8C0 IICI1 CMT 1 H 900 CMTI GETHER 3 H 920 GEINT0 H 940 GEINT1 H 960 GEINT2 HAC 1 H 980 HACI PCIC0 1 H A00 SERR PCIC1 1 H A20 INTA PCIC2 1 H A40 INTB PCIC3 1 H A60 INTC PCIC4 1 H A80 INTD PCIC5 5 H AA0 ERR H AC0 PWD3 H AE0 PWD2 H B00 PWD1...

Page 305: ...E0 TXI1 SIOF0 1 H C00 SIOFI0 SIOF1 1 H C20 SIOFI1 SIOF2 1 H C40 SIOFI2 USBH 1 H C60 USBHI USBF 2 H C80 USBFI0 H CA0 USBFI1 TPU 1 H CC0 TPI PCC 1 H CE0 PCCI MMCIF 4 H D00 FSTAT H D20 TRAN H D40 ERR H D60 FRDY SIM 4 H D80 ERI H DA0 RXI H DC0 TXI H DE0 TEND TMU3 1 H E00 TUNI3 TMU4 1 H E20 TUNI4 TMU5 1 H E40 TUNI5 ADC 1 H E60 ADI SSI0 1 H E80 SSII0 SSI1 1 H EA0 SSII1 SSI2 1 H EC0 SSII2 SSI3 1 H EE0 SS...

Page 306: ...nput capture interrupt DMINT0 to DMINT11 DMAC channel 0 to 5 transfer end interrupt DMAE DMAC address error interrupt channel 0 to 5 ERI0 ERI1 SCIF channel 0 1 receive error interrupt RXI0 RXI1 SCIF channel 0 1 receive data full interrupt BRI0 BRI1 SCIF channel 0 1 break interrupt TXI0 TXI1 SCIF channel 0 1 transmission data empty interrupt 3 The SECURITY is not incorporated in the R5S77631 Theref...

Page 307: ...he CPU SH 4A and are initialized by a power on reset and a manual reset Table 9 3 shows the INTC register configuration Table 9 4 shows the register states in each operating mode Table 9 3 INTC Register Configuration Name Abbreviation R W P4 Address Area 7 Address Access Size Interrupt control register 0 ICR0 R W H FFD0 0000 H 1FD0 0000 32 Interrupt control register 1 ICR1 R W H FFD0 001C H 1FD0 0...

Page 308: ...ty register 9 INT2PRI9 R W H FFD4 00A4 H 1FD4 00A4 32 Interrupt priority register 10 INT2PRI10 R W H FFD4 00A8 H 1FD4 00A8 32 Interrupt priority register 11 INT2PRI11 R W H FFD4 00AC H 1FD4 00AC 32 Interrupt priority register 12 INT2PRI12 R W H FFD4 00B0 H 1FD4 00B0 32 Interrupt priority register 13 INT2PRI13 R W H FFD4 00B4 H 1FD4 00B4 32 Interrupt source register 0 mask state is not affected INT...

Page 309: ...0 H 1FD4 0050 32 Individual module interrupt source register 5 INT2B5 R H FFD4 0054 H 1FD4 0054 32 Individual module interrupt source register 6 INT2B6 R H FFD4 0058 H 1FD4 0058 32 Individual module interrupt source register 7 INT2B7 R H FFD4 005C H 1FD4 005C 32 Individual module interrupt source register 9 INT2B9 R H FFD4 0064 H 1FD4 0064 32 Individual module interrupt source register 10 INT2B10 ...

Page 310: ... Interrupt priority register 0 INT2PRI0 H 0000 0000 H 0000 0000 Retained Retained Interrupt priority register 1 INT2PRI1 H 0000 0000 H 0000 0000 Retained Retained Interrupt priority register 2 INT2PRI2 H 0000 0000 H 0000 0000 Retained Retained Interrupt priority register 3 INT2PRI3 H 0000 0000 H 0000 0000 Retained Retained Interrupt priority register 4 INT2PRI4 H 0000 0000 H 0000 0000 Retained Ret...

Page 311: ...egisters 1 INT2B1 H 0000 0000 H 0000 0000 Retained Retained Individual module interrupt source registers 2 INT2B2 H 0000 0000 H 0000 0000 Retained Retained Individual module interrupt source registers 3 INT2B3 H 0000 0000 H 0000 0000 Retained Retained Individual module interrupt source registers 4 INT2B4 H 0000 0000 H 0000 0000 Retained Retained Individual module interrupt source registers 5 INT2B...

Page 312: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 NMIL Undefined R NMI Input Level Sets the signal level input to the NMI pin Reading this bit allows the user to know the NMI pin level and writing is invalid 0 Low level is input to the NMI pin 1 High level is input to the NMI pin 30 MAI 0 R W MAI Int...

Page 313: ... NMI Edge Select Selects whether an interrupt request signal to the NMI pin is detected at the rising edge or the falling edge 0 An interrupt request is detected at the falling edge of NMI input initial value 1 An interrupt request is detected at the rising edge of NMI input 23 IRLM0 0 R W IRL Pin Mode 0 Selects whether IRQ3 IRL3 to IRQ0 IRL0 are used as the 4 bit encoded interrupt requests or as ...

Page 314: ...changed for four consecutive cycles 21 to 0 All 0 R Reserved These bits are always read as 0 The write value should always be 0 9 3 2 Interrupt Control Register 1 ICR1 ICR1 is a 32 bit readable writable register that specifies the individual input signal detection modes of external interrupt input pins IRQ7 IRL7 to IRQ4 IRL4 This setting is valid only when using IRL7 to IRL4 and IRL3 to IRL0 as IR...

Page 315: ...upt source is held until the CPU accepts an interrupt not always IRQ Therefore even if an interrupt source is disabled before this LSI returns from sleep mode it is guaranteed that processing is branched to the interrupt handler when this LSI returns from sleep mode The held interrupt can be cleared by setting the corresponding interrupt mask bit the IM bit in the interrupt mask register to 1 9 3 ...

Page 316: ... 3 to 0 IP7 H 0 R W Set priority of an independent interrupt request of IRQ7 Interrupt priorities should be determined by setting a value from H F to H 1 to each 4 bit field If the value is larger the priority is higher When the value of H 0 is set to a field a corresponding interrupt is masked initial value 9 3 4 Interrupt Source Register INTREQ INTREQ is a 32 bit readable and writable with condi...

Page 317: ...ote Write 1 to the corresponding bit read as 0 When reading 0 A corresponding IRQ interrupt pin is not asserted 1 A corresponding IRQ interrupt pin has asserted but the CPU does not accept it yet Writing is ignored 23 to 0 All 0 R Reserved These bits are always read as 0 The write value should always be 0 9 3 5 Interrupt Mask Register 0 INTMSK0 INTMSK0 is 32 bit readable and writable with conditio...

Page 318: ...st of IRQ0 30 IM01 1 R W Sets masking of an independent interrupt request of IRQ1 29 IM02 1 R W Sets masking of an independent interrupt request of IRQ2 28 IM03 1 R W Sets masking of an independent interrupt request of IRQ3 27 IM04 1 R W Sets masking of an independent interrupt request of IRQ4 26 IM05 1 R W Sets masking of an independent interrupt request of IRQ5 25 IM06 1 R W Sets masking of an i...

Page 319: ... 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 IM10 1 R W Sets masking of IRL3 to IRL0 interrupt requests when IRQ3 IRL3 to IRQ0 IRL0 are encoded interrupt input 30 IM11 1 R W Sets masking of IRQ7 IRL7 to IRQ4 IRL4 interrupt requests when IRL 7 4 are encoded...

Page 320: ...M014 R R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IM101 IM102 IM103 IM104 IM105 IM106 IM107 IM108 IM109 IM110 IM111 IM112 IM113 IM115 IM114 R R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 IM015 0 R W Sets mask...

Page 321: ...quest when IRL 3 0 HLLH H 9 21 IM005 0 R W Sets masking of an interrupt request when IRL 3 0 HLHL H A When reading 0 Interrupts are accepted 1 Interrupts are masked When writing 0 Invalid 1 Interrupts are masked Initial value 0 20 IM004 0 R W Sets masking of an interrupt request when IRL 3 0 HLHH H B 19 IM003 0 R W Sets masking of an interrupt request when IRL 3 0 HHLL H C 18 IM002 0 R W Sets mask...

Page 322: ...ked 12 IM112 0 R W Sets masking of an interrupt request when IRL 7 4 LLHH H 3 11 IM111 0 R W Sets masking of an interrupt request when IRL 7 4 LHLL H 4 10 IM110 0 R W Sets masking of an interrupt request when IRL 7 4 LHLH H 5 9 IM109 0 R W Sets masking of an interrupt request when IRL 7 4 LHHL H 6 8 IM108 0 R W Sets masking of an interrupt request when IRL 7 4 LHHH H 7 7 IM107 0 R W Sets masking o...

Page 323: ...hen writing 0 Invalid 1 Interrupts are masked 0 0 R Reserved This bit is always read as 0 The write value should always be 0 9 3 8 Interrupt Mask Clear Register 0 INTMSKCLR0 INTMSKCLR0 is 32 bit write only registers that clear the mask settings for IRQn n 0 to 7 interrupt requests An undefined value is read 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IC07 IC06 I...

Page 324: ...lears masking of an independent interrupt request of IRQ3 27 IC04 0 R W Clears masking of an independent interrupt request of IRQ4 26 IC05 0 R W Clears masking of an independent interrupt request of IRQ5 25 IC06 0 R W Clears masking of an independent interrupt request of IRQ6 24 IC07 0 R W Clears masking of an independent interrupt request of IRQ7 When reading An undefined value is read When writi...

Page 325: ...11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 IC10 0 R W Clears masking of IRQ3 IRL3 to IRQ0 IRL0 interrupt requests when IRL 3 0 are encoded interrupt input 30 IC11 0 R W Clears masking of IRQ7 IRL7 to IRQ4 IRL4 interrupt requests when IRL 7 4 are encoded interrupt input When...

Page 326: ... R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 IC015 0 R W Clears masking of an interrupt request when IRL 3 0 LLLL H 0 30 IC014 0 R W Clears masking of an interrupt request when IRL 3 0 LLLH H 1 29 IC013 0 R W Clears masking of an interrupt request when IRL 3 0 LLHL H 2 28 IC012 0 R W Clears masking of an ...

Page 327: ...d When writing 0 Invalid 1 Clears the corresponding interrupt mask Interrupts are enabled 18 IC002 0 R W Clears masking of an interrupt request when IRL 3 0 HHLH H D 17 IC001 0 R W Clears masking of an interrupt request when IRL 3 0 HHHL H E 16 0 R Reserved This bit is always read as 0 The write value should always be 0 15 IC115 0 R W Clears masking of an interrupt request when IRL 7 4 LLLL H 0 14...

Page 328: ...quest when IRL 7 4 HLLL H 8 When reading An undefined value is read When writing 0 Invalid 1 Clears the corresponding interrupt mask Interrupts are enabled 6 IC106 0 R W Clears masking of an interrupt request when IRL 7 4 HLLH H 9 5 IC105 0 R W Clears masking of an interrupt request when IRL 7 4 HLHL H A 4 IC104 0 R W Clears masking of an interrupt request when IRL 7 4 HLHH H B 3 IC103 0 R W Clear...

Page 329: ... cleared automatically Even if 0 is written to the NMIFL bit before the NMI request is accepted by the CPU the NMI request is not canceled 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NMIFL NMIL R W R R R R R R R R R R R R R R R 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Bit Initial value R W Bit Initial va...

Page 330: ...When addresses in area 7 are accessed using the MMU address translation function USERIMASK can be accessed in user mode Since only USERIMASK is allocated in the 64 Kbyte page other INTC registers are allocated to a different area it can be set to be accessed in user mode Interrupts whose priority levels are lower than the level set in the UIMASK bit are masked If the value of H F is set to the UIM...

Page 331: ... are always read as 0 The write value should always be 0 Procedure for Using User Interrupt Mask Level Register This function is used to save time by disabling interrupts whose priorities are low when a high priority interrupt is processed in the device driver Setting the interrupt mask level in USERIMASK disables interrupts having an equal or lower priority level than the specified mask level Thi...

Page 332: ...pts in the device driver that is operating in user mode 5 Process interrupts with high priority in the device driver 6 Clear the UIMASK bit to 0 to return from processing in the device driver 9 3 13 On chip module Interrupt Priority Registers INT2PRI0 to INT2PRI13 INT2PRI0 to INT2PRI13 are 32 bit readable writable registers that set priorities levels 31 to 0 of the on chip peripheral module interr...

Page 333: ...MU1 TUNI4 TMU1 TUNI5 RTC INT2PRI2 SCIF0 SCIF1 WDT Reserved INT2PRI3 H UDI DMAC ADC Reserved INT2PRI4 CMT HAC PCIC0 PCIC1 INT2PRI5 PCIC2 PCIC3 PCIC4 PCIC5 INT2PRI6 SIOF0 USBF MMCIF SSI0 INT2PRI7 SCIF2 GPIO Reserved Reserved INT2PRI8 SSI3 SSI2 SSI1 SECURITY INT2PRI9 LCDC Reserved IIC1 IIC0 INT2PRI10 TPU SIM SIOF2 SIOF1 INT2PRI11 PCC Reserved Reserved Reserved INT2PRI12 Reserved Reserved USBH GETHER ...

Page 334: ... value R W Bit Bit Name Initial Value R W Function Description 31 to 26 All 0 R These bits are always read as 0 The write value should always be 0 25 GPIO 0 R Indicates GPIO interrupt source 24 0 R This bit is always read as 0 The write value should always be 0 23 SSI0 0 R Indicates SSI0 interrupt source 22 MMCIF 0 R Indicates MMCIF interrupt source 21 0 R This bit is always read as 0 The write va...

Page 335: ...pts 1 Interrupts are generated Note Reading the INTEVT code notified to the CPU directly can identify interrupt sources In this case reading INT2A0 is not necessary 9 3 15 Interrupt Source Register 01 Mask State is not affected INT2A01 INT2A01 mask state is not affected is a 32 bit read only register that indicates interrupt source modules Even if interrupt masking is set in the interrupt mask reg...

Page 336: ...he write value should always be 0 17 USBH 0 R Indicates USBH interrupt source 16 GETHER 0 R Indicates GETHER interrupt source 15 PCC 0 R Indicates PCC interrupt source 14 0 R This bit is always read as 0 The write value should always be 0 13 0 R Undefined value is read from this bit The write value should always be 0 12 ADC 0 R Indicates ADC interrupt source 11 TPU 0 R Indicates TPU interrupt sour...

Page 337: ...rupt source 4 IIC0 0 R Indicates IIC0 interrupt source 3 SSI3 0 R Indicates SSI3 interrupt source 2 SSI2 0 R Indicates SSI2 interrupt source 1 SSI1 0 R Indicates SSI1 interrupt source 0 SECURITY 0 R Indicates SECURITY interrupt source Indicates interrupt sources for each peripheral module INT2A01 is not affected by the state of the interrupt mask register 0 No interrupts 1 Interrupts are generated...

Page 338: ...C2 PCIC1 PCIC0 HAC CMT DMAC H UDI WDT SCIF1 SCIF0 RTC TMU1 TMU0 Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Function Description 31 to 26 All 0 R These bits are always read as 0 The write value should always be 0 25 GPIO 0 R Indicates GPIO interrupt source 24 0 R This bit is always read as 0 The write value should always be 0 23 SSI0 0 R Indicates SSI0 interrupt sour...

Page 339: ... R Indicates DMAC interrupt source 7 H UDI 0 R Indicates H UDI interrupt source 6 0 R This bit is always read as 0 The write value should always be 0 5 WDT 0 R Indicates WDT interrupt source 4 SCIF1 0 R Indicates SCIF1 interrupt source 3 SCIF0 0 R Indicates SCIF0 interrupt source 2 RTC 0 R Indicates RTC interrupt source 1 TMU1 0 R Indicates TMU1 interrupt source 0 TMU0 0 R Indicates TMU0 interrupt...

Page 340: ...IF0 GETH ER PCC ADC TPU SIM SIOF2 SIOF1 LCDC IIC1 IIC0 SSI3 SSI2 SSI1 SECU RITY Bit Initial value R W Bit Initial value R W Note This bit is reserved in the R5S77631 Bit Bit Name Initial Value R W Function Description 31 to 26 All 0 R These bits are always read as 0 The write value should always be 0 25 SCIF2 0 R Indicates SCIF2 interrupt source 24 USBF 0 R Indicates USBF interrupt source 23 22 Al...

Page 341: ...cates SIOF1 interrupt source 7 LCDC 0 R Indicates LCDC interrupt source 6 0 R This bit is always read as 0 The write value should always be 0 5 IIC1 0 R Indicates IIC1 interrupt source 4 IIC0 0 R Indicates IIC0 interrupt source 3 SSI3 0 R Indicates SSI3 interrupt source 2 SSI2 0 R Indicates SSI2 interrupt source 1 SSI1 0 R Indicates SSI1 interrupt source 0 SECURITY 0 R Indicates SECURITY interrupt...

Page 342: ...CIC2 PCIC1 PCIC0 HAC CMT DMAC H UDI SCIF1 SCIF0 WDT RTC TMU1 TMU0 Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Function Description 31 to 26 All 1 R These bits are always read as 1 The write value should always be 1 25 GPIO 1 R W Masks GPIO interrupts 24 1 R This bit is always read as 1 The write value should always be 1 23 SSI0 1 R W Masks SSI0 interrupts 22 MMCIF 1 ...

Page 343: ...peripheral module When writing 0 Invalid 1 Interrupts are masked When reading 0 No mask setting 1 Mask setting 9 3 19 Interrupt Mask Register 1 INT2MSKR1 INT2MSKR1 is a 32 bit readable writable register that sets masking for each source indicated in the interrupt source register Interrupts whose corresponding bits in INT2MSKR1 are set to 1 are not notified to the CPU INT2MSK1 is initialized to H F...

Page 344: ... always be 1 17 USBH 1 R W Masks USBH interrupts 16 GETHER 1 R W Masks GETHER interrupts 15 PCC 1 R W Masks PCC interrupts 14 13 All 1 R These bits are always read as 1 The write value should always be 1 12 ADC 1 R W Masks ADC interrupts 11 TPU 1 R W Masks TPU interrupts 10 SIM 1 R W Masks SIM interrupts 9 SIOF2 1 R W Masks SIOF2 interrupts 8 SIOF1 1 R W Masks SIOF1 interrupts 7 LCDC 1 R W Masks L...

Page 345: ...ear Register INT2MSKCR INT2MSKCR is a 32 bit write only register that clears any masking set in the interrupt mask register Setting bits in this register to 1 clears the masking of the corresponding interrupt sources Reading bits in this register is always 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R R W R W R R W R R R R R R 0 1 2 3 4 5 6...

Page 346: ...ue should always be 0 20 SIOF0 0 R W Clears SIOF0 interrupt masking 19 PCIC5 0 R W Clears PCIC5 interrupt masking 18 PCIC4 0 R W Clears PCIC4 interrupt masking Clears interrupt masking for each peripheral module When writing 0 Invalid 1 Interrupt mask is cleared When reading Always 0 17 PCIC3 0 R W Clears PCIC3 interrupt masking 16 PCIC2 0 R W Clears PCIC2 interrupt masking 15 PCIC1 0 R W Clears P...

Page 347: ...nvalid 1 Interrupt mask is cleared When reading Always 0 9 3 21 Interrupt Mask Clear Register 1 INT2MSKCR1 INT2MSKCR1 is a 32 bit write only register that clears any masking set in the interrupt mask register Setting bits in this register to 1 clears the masking of the corresponding interrupt sources Reading bits in this register is always 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 ...

Page 348: ...t masking 16 GETHER 0 R W Clears GETHER interrupt masking 15 PCC 0 R W Clears PCC interrupt masking 14 13 All 0 R These bits are always read as 0 The write value should always be 0 12 ADC 0 R W Clears ADC interrupt masking 11 TPU 0 R W Clears TPU interrupt masking 10 SIM 0 R W Clears SIM interrupt masking 9 SIOF2 0 R W Clears SIOF2 interrupt masking 8 SIOF1 0 R W Clears SIOF1 interrupt masking 7 L...

Page 349: ...11 are 32 bit read only registers that indicate detailed sources for interrupt source modules indicated in the interrupt source register INT2B0 to INT2B7 and INT2B9 to INT2B11 are not affected by the mask state of the interrupt mask register When mask setting is made for individual detailed sources set the interrupt mask register or interrupt enable register in the corresponding modules The initia...

Page 350: ...sources for the RTC Module Bit Source Function Description 31 to 3 These bits are always read as 0 The write value should always be 0 2 CUI RTC carry interrupt 1 PRI RTC period interrupt RTC 0 ATI RTC alarm interrupt Indicates RTC interrupt sources This register indicates the RTC interrupt sources even if mask setting is made in the interrupt mask register for them INT2B2 Indicates detailed interr...

Page 351: ...r for them INT2B3 Indicates detailed interrupt sources for the DMAC Module Bit Source Function Description 31 to 13 These bits are always read as 0 The write value should always be 0 12 DMAE DMA channels 0 to 5 address error interrupt 11 to 6 These bits are always read as 0 The write value should always be 0 5 DMTE5 Channel 5 DMA transfer end interrupt 4 DMTE4 Channel 4 DMA transfer end interrupt ...

Page 352: ...dicates PCIC interrupt sources This register indicates the PCIC interrupt sources even if mask setting is made in the interrupt mask register for them INT2B5 Indicates detailed interrupt sources for the MMCIF Module Bit Source Function Description 31 to 4 These bits are always read as 0 The write value should always be 0 3 FRDY FIFO ready interrupt 2 ERR CRC error interrupt data timeout error inte...

Page 353: ...gister for them INT2B7 Indicates detailed interrupt sources for the GPIO Module Bit Source Function Description GPIO 31 to 28 These bits are always read as 0 The write value should always be 0 27 PINT15I GPIO interrupt from PINT15 pin 26 PINT14I GPIO interrupt from PINT14 pin 25 PINT13I GPIO interrupt from PINT13pin 24 PINT12I GPIO interrupt from PINT12 pin 23 to 20 These bits are always read as 0...

Page 354: ...register for them INT2B9 Indicates detailed interrupt sources for the GETHER Module Bit Source Function Description 31 to 3 These bits are always read as 0 The write value should always be 0 2 GEINT2 GEINT2 interrupt 1 GEINT1 GEINT1 interrupt GETHER 0 GEINT0 GEINT0 interrupt Indicates GETHER interrupt sources This register indicates the GETHER interrupt sources even if mask setting is made in the ...

Page 355: ...er INT2GPIC INT2GPIC enables interrupt requests input from the following pins PTB0 to PTB7 and PTM0 to PTM7 A GPIO interrupt is a low active and level sense signal Before enabling an interrupt request set the corresponding pin as an input with the corresponding port control register PBCR PMCR For the port control registers see section 40 General Purpose I O GPIO 16 17 18 19 20 21 22 23 24 25 26 27...

Page 356: ...13 pin 24 PINT12E 0 R W Enables a GPIO interrupt request from PINT12 pin 23 to 20 All 0 R Reserved These bits are always read as 0 The write value should always be 0 19 PINT11E 0 R W Enables a GPIO interrupt request from PINT11 pin 18 PINT10E 0 R W Enables a GPIO interrupt request from PINT10 pin 17 PINT9E 0 R W Enables a GPIO interrupt request from PINT9 pin 16 PINT8E 0 R W Enables a GPIO interru...

Page 357: ...IO interrupt request from PINT3 pin 2 PINT2E 0 R W Enables a GPIO interrupt request from PINT2 pin 1 PINT1E 0 R W Enables a GPIO interrupt request from PINT1 pin 0 PINT0E 0 R W Enables a GPIO interrupt request from PINT0 pin Enables a GPIO interrupt request for each pin 0 Disables an interrupt request 1 Enables an interrupt request When GPIO ports are used as interrupt ports if the GPIO detects an...

Page 358: ...n SR is not affected by the NMI interrupt exception handling 9 4 2 IRQ Interrupts IRQ interrupts are available when using the IRQ7 IRL7 to IRQ0 IRL0 pin for IRQn n 7 to 0 independent interrupt inputs by setting the IRLM0 and IRLM1 bits to 1 in ICR0 The IRQnS1 and IRQnS0 bits in ICR1 are used to select either rising edge falling edge low level or high level detection A priority level can be set for...

Page 359: ... is the level indicated by pins IRQ7 IRL7 to IRQ4 IRL4 or IRQ3 IRL3 to IRQ0 IRL0 An IRQ7 IRL7 to IRQ4 IRL4 or IRQ3 IRL3 to IRQ0 IRL0 pins input are all low level indicates the highest level interrupt request interrupt priority level 15 and all high level indicates no interrupt request interrupt priority level 0 Figure 9 2 shows an example of IRL interrupt connection and table 9 6 shows the corresp...

Page 360: ...t Request High High High High 0 No Interrupt Request After an interrupt request is accepted the interrupt request held in the detection circuit should be cleared For the specific clearing procedure see section 9 7 3 To Clear IRQ and IRL Interrupt Requests Note Although there is no interrupt source register for the IRL interrupt requests once an IRL interrupt request has been detected the INTC hold...

Page 361: ...register containing the relevant flag and wait the priority determination time shown in table 9 8 then clear the BL bit to 0 This will secure the necessary timing internally When updating a number of flags there is no problem if only the register containing the last flag updated is read from If flag updating is performed while the BL bit is cleared to 0 the program may jump to the interrupt handli...

Page 362: ...upt priority level that same for the CPU When multiple interrupt from on chip modules occur simultaneously the INTC proesses the priority level H 1B is higher than that of H 1A However if an external interrupt will be higher priority in some case NMI interrupt request IRQ or IRL interrupt request that the same priority level or more H D or more in this figure Priority level H 01 becomes H 00 by ro...

Page 363: ...rupt priority level setting registers then clear the BL bit to 0 This will secure the necessary timing internally Table 9 7 Interrupt Exception Handling and Priority Interrupt Source INTEVT Code Interrupt Priority MASK CLEAR Register Interrupt Source Register Detail Source Register Priority in the Source Default Priority NMI H 1C0 16 High IRL 7 4 LLLL H 0 INTMSK2 15 INTMSKCLR2 15 IRL 3 0 LLLL H 0 ...

Page 364: ... INTMSKCLR2 9 IRL 3 0 LHHL H 6 H 2C0 9 INTMSK2 25 INTMSKCLR2 25 IRL 7 4 LHHH H 7 INTMSK2 8 INTMSKCLR2 8 IRL 3 0 LHHH H 7 H 2E0 8 INTMSK2 24 INTMSKCLR2 24 IRL 7 4 HLLL H 8 INTMSK2 7 INTMSKCLR2 7 IRL 3 0 HLLL H 8 H 300 7 INTMSK2 23 INTMSKCLR2 23 IRL 7 4 HLLH H 9 INTMSK2 6 INTMSKCLR2 6 IRL 3 0 HLLH H 9 H 320 6 INTMSK2 22 INTMSKCLR2 22 IRL 7 4 HLHL H A H 340 5 INTMSK2 5 INTMSKCLR2 5 IRL 3 0 HLHL H A I...

Page 365: ...RL 7 4 HHHL H E INTMSK2 1 INTMSKCLR2 1 IRL L Low level input H High level input See table 9 6 IRL 3 0 HHHL H E H 3C0 1 INTMSK2 17 INTMSKCLR2 17 IRQ 0 H 240 INTPRI 31 28 INTMSK0 31 INTMSKCLR0 31 INTREQ 31 IRQ 1 H 280 INTPRI 27 24 INTMSK0 30 INTMSKCLR0 30 INTREQ 30 IRQ 2 H 2C0 INTPRI 23 20 INTMSK0 29 INTMSKCLR0 29 INTREQ 29 IRQ 3 H 300 INTPRI 19 16 INTMSK0 28 INTMSKCLR0 28 INTREQ 28 IRQ 4 H 340 INTP...

Page 366: ...11 0 WDT ITI 1 H 560 INT2PRI 2 12 8 INT2MSKR 5 INT2MSKCR 5 INT2A0 5 INT2A1 5 TMU0 TUNI0 1 H 580 INT2PRI 0 28 24 INT2B0 0 TMU1 TUNI1 1 H 5A0 INT2PRI 0 20 16 INT2B0 1 TUNI2 1 H 5C0 INT2PRI 0 12 8 INT2B0 2 TMU2 TICPI2 1 H 5E0 INT2PRI 0 4 0 INT2MSKR 0 INT2MSKCR 0 INT2A0 0 INT2A1 0 INT2B0 3 H UDI H UDI H 600 INT2PRI 3 28 24 INT2MSKR 7 INT2MSKCR 7 INT2A0 7 INT2A1 7 LCDC LCDCI H 620 INT2PRI 9 28 24 INT2M...

Page 367: ...IC1 IICI1 H 8C0 INT2PRI9 12 8 INT2MSKR1 5 INT2MSKCR1 5 INT2A01 5 INT2A11 5 CMT CMTI H 900 INT2PRI4 28 24 INT2MSKR 12 INT2MSKCR 12 INT2A0 12 INT2A1 12 GEINT0 H 920 INT2B9 0 GEINT1 H 940 INT2B9 1 GEther GEINT2 H 960 INT2PRI 12 4 0 INT2MSKR1 16 INT2MSKCR1 16 INT2A01 16 INT2A11 16 INT2B9 2 HAC HACI H 980 INT2PRI4 20 16 INT2MSKR 13 INT2MSKCR 13 INT2A0 13 INT2A1 13 PCIC0 PCISERR H A00 INT2PRI4 12 8 INT2...

Page 368: ...NT2A01 20 INT2A11 20 STIF1 STIFI1 H B60 INT2PRI 13 12 8 INT2MSKR1 21 INT2MSKCR1 21 INT2A01 21 INT2A11 21 SCIF1 ERI1 1 H B80 INT2B2 4 RXI1 1 H BA0 INT2B2 5 BRI1 1 H BC0 INT2B2 6 TXI1 1 H BE0 INT2PRI2 20 16 INT2MSKR 4 INT2MSKCR 4 INT2A0 4 INT2A1 4 INT2B2 7 High Low SIOF0 SIOFI0 H C00 INT2PRI6 28 24 INT2MSKR 14 INT2MSKCR 14 INT2A0 14 INT2A1 14 SIOF1 SIOFI1 H C20 INT2PRI1 0 4 0 INT2MSKR1 8 INT2MSKCR1 ...

Page 369: ... D40 INT2B5 2 MMCIF FRDY H D60 INT2PRI6 12 8 INT2MSKR 22 INT2MSKCR 22 INT2A0 22 INT2A1 22 INT2B5 3 High Low ERI H D80 INT2B11 0 RXI H DA0 INT2B11 1 TXI H DC0 INT2B11 2 SIM TEND H DE0 INT2PRI10 20 16 INT2MSKR1 10 INT2MSKCR1 10 INT2A01 10 INT2A11 10 INT2B11 3 TMU3 TUNI3 1 H E00 INT2PRI1 28 24 INT2B0 4 TMU4 TUNI4 1 H E20 INT2PRI1 20 16 INT2B0 5 TMU5 TUNI5 1 H E40 INT2PRI1 12 8 INT2MSKR 1 INT2MSKCR 1 ...

Page 370: ...NT2MSKCR1 25 INT2A01 25 INT2A11 25 INT2B6 3 High Low CH0 H F80 INT2B7 3 0 CH1 H FA0 INT2B7 11 8 CH2 H FC0 INT2B7 19 16 High GPIO CH3 H FE0 INT2PRI7 20 16 INT2MSKR 25 INT2MSKCR 25 INT2A0 25 INT2A1 25 INT2B7 27 24 Low Low Notes 1 ITI Interval timer interrupt TUNI0 to TUNI5 TMU channel 0 to 5 under flow interrupt TICPI2 TMU channel 2 input capture interrupt DMINT0 to DMINT5 DMAC channel 0 to 5 transf...

Page 371: ...egister INTEVT 6 SR and program counter PC are saved to SSR and SPC respectively R15 is saved to SGR at this time 7 The BL MD and RB bits in SR are set to 1 8 Execution jumps to the start address of the interrupt exception handling routine the sum of the value set in the vector base register VBR and H 0000 0600 In the exception handling routine execution may branch with the INTEVT value used as it...

Page 372: ...EVT Save SR to SSR save PC to SPC save R15 to SGR ICR0 MAI 1 Yes No Interrupt generated Yes No SR BL 0 or Sleep mode Yes No CPUOPM INTMU 1 No Yes NMI input is low Yes No ICR0 NMIB 1 Yes No NMI Yes No NMI Yes No Level 15 interrupt Yes No Level 14 interrupt Yes No Level 1 interrupt Yes Yes No SR IMASK level is 0 No Yes SR IMASK level is 14 or low No Yes SR IMASK level is 14 or low No Figure 9 4 Inte...

Page 373: ...he level of the accepted interrupt When the INTMU bit in CPUOPM is cleared to 0 set the IMASK bit in SR by software to the accepted interrupt level 5 Handle the interrupt as required 6 Set the BL bit in SR to 1 7 Restore SSR and SPC from memory 8 Execute the RTE instruction When these procedures are followed in order an interrupt of higher priority than the one being handled can be accepted if mul...

Page 374: ...7Pcyc Wait time until the CPU finishes the current sequence S 1 0 Icyc Interval from when interrupt exception handling begins saving SR and PC until a SHwy bus request is issued to fetch the start instruction of the exception handling routine 11Icyc 1Scyc Total S 10 Icyc 1Scyc 5Bcyc 2Pcyc S 10 Icyc 1Scyc 8Bcyc 2Pcyc S 10 Icyc 1Scyc 4Bcyc 2Pcyc S 10 Icyc 1Scyc 5Pcyc S 10 Icyc 1Scyc 7Pcyc Response t...

Page 375: ... Set the corresponding mask bit to 1 to clear the interrupt request held in the detection circuit 1 Write to the GPIO register or local bus space 2 Read the address to which writing has been made 1 Set the corresponding bit in INTMSK0 INTMSK1 2 Set the corresponding bit in INTMSKCLR0 INTMSKCLR1 3 Read INTMSK0 INTMSK1 Start of level encoded IRL or level sensed IRQ interrupt handing End of level enc...

Page 376: ...D 1 0 PL0MD 1 0 bits in PLCR 3 IRQ7 IRL7 to IRQ0 IRL0 pins setting to IRL or IRQ interrupt request input Set the IRLM 1 0 bit in ICR0 4 IRL and IRQ interrupt detection start Write 1 to the corresponding bit in INTMSKCLR0 and INTMSKCLR1 9 7 3 To Clear IRQ and IRL Interrupt Requests Clearing procedure of the interrupt held in the INTC is as follows To clear IRL interrupt requests To clear an IRL int...

Page 377: ...ge detection interrupt requests To clear an IRQ edge detection interrupt request from the IRQ7 IRL7 to IRQ0 IRL0 pins write 0 after reading 1 in the corresponding IRn n 0 to 7 bit in INTREQ The IRQ interrupt requests detected by the INTC is not cleared even if 1 is written to a corresponding bit in INTMSK0 ...

Page 378: ...Section 9 Interrupt Controller INTC Rev 1 00 Oct 01 2007 Page 312 of 1956 REJ09B0256 0100 ...

Page 379: ...THER and USBH connected to the SuperHyway bridge bus 10 1 Features SuperHyway bus interface Performs access protocol conversion between the SuperHyway bus and the SuperHyway bridge bus Arbitration The arbiter arbitrates between the accesses to the SuperHyway bus by the SECURITY GETHER and USBH modules connected to the SuperHyway bridge bus Priority can be set for the individual modules or ports Fi...

Page 380: ...0 0010 32 SuperHyway bus priority control register PRPRICR R W H FE60 0018 H 1F60 0018 32 Note The area P4 address is the address when the P4 area of a virtual address space is used The area 7 address is the address when the register is accessed through area 7 of a physical address space by using the TLB Table 10 2 Register State in Each Operating Mode Register Name Abbreviation Power On Reset Man...

Page 381: ...0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R W R W R W R R R R W USBH LV GEC1 LV GEC0 LV SEC LV Bit Bit Name Initial Value R W Description 31 to 7 All 0 R Reserved These bits are always read as 0 The write value should always be 0 6 SECLV 0 R W SECURITY Access Priority Level 0 Level 3 1 Level 2 5 GEC0LV 0 R W GETHER0 Access Priority Level 0 Level 3 ...

Page 382: ...on 31 to 1 All 0 R Reserved These bits are always read as 0 The write value should always be 0 0 SBAPR 1 R W SuperHyway Bus Access Priority Sets whether to give the CPU priority over the other function modules when accessing the SuperHyway bus 0 The CPU is given the same priority as the other function modules 1 The CPU is given priority over the other function modules Note With this bit set to 1 w...

Page 383: ...ncept of arbitration by the SBR SECURITY GETHER0 GETHER1 USBH SECURITY GETHER0 GETHER1 USBH Level 3 Level 3 4 round robin Level 2 5 round robin Level 1 Level 2 USBH Write USBH Read USBH Write USBH Read Figure 10 2 Bus Arbitration by the SBR The SBR performs arbitration for three groups level 1 level 2 and level 3 At level 3 round robin arbitration is performed for a total of four ports of three mo...

Page 384: ...riority level of access requests from SECURITY GETHER1 GETHER0 and USBH can be set to level 2 or level 3 through the SBRIVCLV register Note that in the USBH module round robin arbitration is first performed between read and write requests then inter module arbitration is performed using the result ...

Page 385: ...ed through register settings except area 0 which is controlled by the external pin setting Wait cycle insertion by the RDY pin Wait cycle insertion can be controlled by a program Types of memory are specifiable for connection to each area Output of the control signals of memory to each area Automatic wait cycle insertion to prevent data bus collisions on consecutive memory accesses to different ar...

Page 386: ...reas 0 to 2 and 4 to 6 Settable bus width 32 bits Byte control SRAM interface SRAM interface with byte control Connectable areas 1 and 4 Settable bus widths 32 and 16 bits PCMCIA interface Wait cycle insertion can be controlled by a program Bus sizing function for I O bus width Little endian Connectable areas 5 and 6 Settable bus widths 16 and 8 bits ...

Page 387: ...CS0 to CS2 CS4 to CS6 CE2A CE2B CE1A CE1B A0 to A25 BS RD RD FRAME RDWR WE3 IOWR WE2 IORD WE1 WE WE0 PCC_REG BACK Area control unit Legned BCR CSnBCR CSnPCR CSnWCR Memory control unit CSnWCR CSnBCR BCR CSnPCR SuperHyway bus Module bus D0 to D31 Bus Control Register n 0 to 2 4 to 6 CSn Bus Control Register n 5 to 6 CSn Wat Control Register n 0 to 2 4 to 6 Bus Control Register Figure 11 1 LBSC Block...

Page 388: ...utput Data bus input output direction designation signal Also used as PCMCIA interface write designation signal RD FRAME Read Cycle Frame Output Strobe signal indicating a read cycle FRAME signal when setting MPX interface WE0 PCC_REG Data Enable 0 Output When setting SRAM interface write strobe signal for D7 to D0 When setting PCMCIA interface REG signal WE1 WE Data Enable 1 Output When setting S...

Page 389: ...ting at a power on reset DACK0 2 DMAC0 Acknowledge Signal Output Data acknowledge of DMAC channel 0 DACK1 2 DMAC1 Acknowledge Signal Output Data acknowledge of DMAC channel 1 DACK2 2 DMAC2 Acknowledge Signal Output Data acknowledge of DMAC channel 2 DACK3 2 DMAC3 Acknowledge Signal Output Data acknowledge of DMAC channel 3 TEND0 2 DMAC0 Transfer End Signal Output Transfer end of DMAC channel 0 TEN...

Page 390: ...ual address can be allocated to any external address using the address translation function of the MMU For details see section 6 Memory Management Unit MMU This section describes the area division of the external address space With this LSI various types of memory or PC cards can be connected to each of the seven areas in the external address space as shown in table 11 2 and accordingly output the...

Page 391: ...ue area P4 area Notes 1 When the MMu is off MMUCR AT 0 the top 3 bits of the 32 bit address are ignored and memory is mapped onto a fixed 29 bit external address When the MMU is on MMUCR AT 1 the P0 U0 P3 and store queue areas can be mapped onto any extrnal space using theTLB For detalis see section 6 Memory Management Unit MMU 2 Figure 11 2 Correspondence between Virtual Address Space and Externa...

Page 392: ...8 16 32 bits and 32 bytes SRAM 8 16 32 2 Burst ROM 8 16 32 2 MPX 32 2 6 H 1800 0000 to H 1BFF FFFF 64 Mbytes PCMCIA 8 16 2 5 8 16 32 bits and 32 bytes 7 6 H 1C00 0000 to H 1FFF FFFF 64 Mbytes Notes 1 The memory bus width is specified by external pins 2 The memory bus width is specified by the register 3 Area 3 is used specifically for the DDR SDRAM For details see section 12 DDR SDRAM Interface DD...

Page 393: ...00000 Area 0 H 10000000 Area 0 H 14000000 Area 0 H 18000000 SRAM burst ROM MPX SRAM burst ROM MPX byte control SRAM SRAM burst ROM MPX DDR SDRAM DDR SDRAM SRAM burst ROM MPX byte control SRAM DDR SDRAM PCI SRAM burst ROM MPX PCMCIA DDR SDRAM SRAM vurst ROM MPX PCMCIA The PCMCIA interface is for memory and I O card use Figure 11 3 External Memory Space Allocation ...

Page 394: ...s used in areas 1 to 2 and 4 to 6 a bus width of 8 16 or 32 bits can be selected through the CSn bus control register CSnBCR When the burst ROM interface is used a bus width of 8 16 or 32 bits can be selected When the byte control SRAM interface is used a bus width of 16 or 32 bits can be selected When the MPX interface is used a bus width of 32 bits should be selected When using the PCMCIA interf...

Page 395: ...ace specifications for areas 5 and 6 in the external memory space The IC memory card interface and I O card interface prescribed in JEIDA specifications version 4 2 PCMCIA2 1 are supported Both the IC memory card interface and the I O card interface are supported in areas 5 and 6 in the external memory space The PCMCIA interface is only supported in little endian mode Table 11 5 PCMCIA Interface F...

Page 396: ...RD 10 A11 I Address A11 I Address A11 11 A9 I Address A9 I Address A9 12 A8 I Address A8 I Address A8 13 A13 I Address A13 I Address A13 14 A14 I Address A14 I Address A14 15 WE I Write enable WE I Write enable WE1 16 READY O Ready IREQ O Interrupt request Sensed on port 17 VCC Operation power supply VCC Operation power supply 18 VPP1 Programming power supply VPP1 Programming peripheral power supp...

Page 397: ...a D14 I O Data D14 41 D15 I O Data D15 I O Data D15 42 CE2 I Card enable CE2 I Card enable CE2A or CE2B 43 VS1 I Refresh request VS1 I Refresh request Output from port 44 RSRVD Reserved IORD I I O read IORD 45 RSRVD Reserved IOWR I I O write IOWR 46 A17 I Address A17 I Address A17 47 A18 I Address A18 I Address A18 48 A19 I Address A19 I Address A19 49 A20 I Address A20 I Address A20 50 A21 I Addr...

Page 398: ...ery voltage detection SPKR O Digital voice signal Sensed on port 63 BVD1 O Battery voltage detection STSCHG O Card status change Sensed on port 64 D8 I O Data D8 I O Data D8 65 D9 I O Data D9 I O Data D9 66 D10 I O Data D10 I O Data D10 67 CD2 O Card detection CD2 O Card detection Sensed on port 68 GND Ground GND Ground Notes 1 I O means input output on the side of the PCMCIA card The polarity of ...

Page 399: ... Control Register CS6BCR R W H 7777 7770 H FF80 2060 H 1F80 2060 32 CS0 Wait Control Register CS0WCR R W H 7777 770F H FF80 2008 H 1F80 2008 32 CS1 Wait Control Register CS1WCR R W H 7777 770F H FF80 2018 H 1F80 2018 32 CS2 Wait Control Register CS2WCR R W H 7777 770F H FF80 2028 H 1F80 2028 32 CS4 Wait Control Register CS4WCR R W H 7777 770F H FF80 2048 H 1F80 2048 32 CS5 Wait Control Register CS...

Page 400: ...0F H 7777 770F Retained Retained CS6 Wait Control Register CS6WCR H 7777 770F H 7777 770F Retained Retained CS5 PCMCIA Control Register CS5PCR H 7700 0000 H 7700 0000 Retained Retained CS6 PCMCIA Control Register CS6PCR H 7700 0000 H 7700 0000 Retained Retained 11 4 1 Memory Address Map Select Register MMSELR The memory address map select register MMSELR is a 32 bit register that selects memory ad...

Page 401: ...and other areas as the LBSC space 010 Sets areas 2 and 3 H 0800 0000 to H 0FFF FFFF as the DDRIF space and other areas as the LBSC space 011 Sets areas 2 and 3 H 0800 0000 to H 0FFF FFFF as the DDRIF space area 4 H 1000 0000 to H 13FF FFFF as PCI memory space and other areas as the LBSC space 100 Sets areas 2 to 5 H 0800 0000 to H 17FF FFFF as the DDRIF space 101 Setting prohibited 110 Setting pro...

Page 402: ...is never write again until execute power on reset or manual reset 11 4 2 Bus Control Register BCR The bus control register BCR is a 32 bit readable writable register that specifies the function and bus cycle status for each area It is initialized to H 0000 0000 in big endian mode or H 8000 0000 in little endian mode by a power on reset or a mammal reset 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31...

Page 403: ...his LSI 30 to 27 All 0 R Reserved These bits are always read as 0 The write value should always be 0 26 DPUP 0 R W Data Pin Pull Up Resistor Control Specifies the pull up resistor state of the data pins D31 to D0 This bit is initialized by a power on reset The pins are not pulled up when access is performed or when the bus is released even if the pull up resistor is on Also in standby mode pins D3...

Page 404: ...1A CS6 CE1B RD WEn RDWR CE2A and CE2B Note In standby mode the control output pins are pulled up regardless of the bit setting 23 to 20 DACKBST 3 0 All 0 R W DACK Burst Select assert period of DACKn signals of DMA burst transfer mode during DMA transfer start to end 0 DACKn signals does not keep assert from burst start to end 1 DACKn signals keep assert from burst start to end DACKBST 3 DACK3 DACK...

Page 405: ...erved This bit is always read as 0 The write value should always be 0 14 HIZCNT 0 R W High Impedance Hi Z Control Specifies the state of signals WEn and RD FRAME during the software standby mode and the bus released state 0 Signals of WEn and RD FRAME are high impedance during the bus released state 1 Signals of WEn and RD FRAME are output during the bus released state 13 to 7 0 R Reserved These b...

Page 406: ...memory immediately after reading This LSI automatically inserts the number of idle cycles set by CSnBCR to prevent data bus collision During idle cycles corresponding signals CS0 to CS2 CS4 CS5 CE1A CS6 CE1B RD WE CE2A CE2B and BS are not asserted and RDWR is in the high state and the data is not driven CSnBCR is initialized to H 7777 7770 by a power on reset or a manual reset 16 17 18 19 20 21 22...

Page 407: ...erted 010 2 idle cycles inserted 011 3 idle cycles inserted 100 4 idle cycles inserted 101 5 idle cycles inserted 110 6 idle cycles inserted 111 7 idle cycles inserted 27 0 R Reserved This bit is always read as 0 The write value should always be 0 26 to 24 IWRWD 111 R W Idle Cycles between Read Write to Different Spaces Specify the number of idle cycles to be inserted after an access to a memory c...

Page 408: ...erted 010 2 idle cycles inserted 011 3 idle cycles inserted 100 4 idle cycles inserted 101 5 idle cycles inserted 110 6 idle cycles inserted 111 7 idle cycles inserted 19 0 R Reserved This bit is always read as 0 The write value should always be 0 18 to 16 IWRRD 111 R W Idle Cycles between Read Read to Different Spaces Specify the number of idle cycles to be inserted after an access to a memory co...

Page 409: ... section 11 5 8 Wait Cycles between Accesses 000 No idle cycle inserted 001 1 idle cycle inserted 010 2 idle cycles inserted 011 3 idle cycles inserted 100 4 idle cycles inserted 101 5 idle cycles inserted 110 6 idle cycles inserted 111 7 idle cycles inserted 11 10 BST 01 R W Burst Length When a burst ROM interface is used these bits specify the number of accesses in a burst The MPX interface is n...

Page 410: ...iming When set this bit to 1 specify the number of RD negation CSn negation delay cycle to be 1 or more by setting the RDH bit in CSnWCR And RD negation CSn negation delay cycle is reduced 1 cycle to set this bit to 1 Available only when the SRAM interface or byte control SRAM interface 0 No hold cycle inserted 1 1 hold cycle inserted 6 to 4 BW 111 R W Burst Pitch When the burst ROM interface is u...

Page 411: ...selected Note The MPX bit in CS0BCR is read only 2 to 0 TYPE 000 R W Memory Type Setting Specify the type of memory connected to the space 000 SRAM Initial value 001 SRAM with byte selection 1 010 Burst ROM burst at read SRAM at write 011 Reserved Setting prohibited 100 PCMCIA 2 101 Reserved Setting prohibited 110 Reserved Setting prohibited 111 Reserved Setting prohibited Note 1 Setting possible ...

Page 412: ...23 24 25 26 27 28 29 31 30 1 1 1 0 1 1 1 0 1 1 1 0 1 1 0 1 RDH RDS ADH ADS R W R W R W R R W R W R W R R W R W R W R R W R W R R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 1 1 1 1 0 0 0 0 1 1 1 0 1 1 0 1 IW 3 0 BSH WTH WTS R W R W R W R W R W R W R W R R W R W R W R W R W R W R R W Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 0 R Reserved This bit is alway...

Page 413: ...will be no inserted cycle when setting to 0 for inserted wait cycle and setting to 0 for RD strobe hold wait in read access or WE strobe hold wait in write access 000 No cycle inserted 001 1 cycle inserted 010 2 cycles inserted 011 3 cycles inserted 100 4 cycles inserted 101 5 cycles inserted 110 6 cycles inserted 111 7 cycles inserted 23 0 R Reserved This bit is always read as 0 The write value s...

Page 414: ...e control an SRAM interface or burst ROM interface is selected 000 No cycle inserted 001 1 cycle inserted 010 2 cycles inserted 011 3 cycles inserted 100 4 cycles inserted 101 5 cycles inserted 110 6 cycles inserted 111 7 cycles inserted 15 0 R Reserved This bit is always read as 0 The write value should always be 0 14 to 12 WTS 111 R W WEn Setup Cycle CSn Assert WEn Assert Delay Cycle Specify the...

Page 415: ...the SRAM interface byte control SRAM interface or burst ROM interface is selected 000 No cycle inserted 001 1 cycle inserted 010 2 cycles inserted 011 3 cycles inserted 100 4 cycles inserted 101 5 cycles inserted 110 6 cycles inserted 111 7 cycles inserted 7 0 R Reserved This bit is always read as 0 The write value should always be 0 6 to 4 BSH 000 R W BS Hold Cycle Specify the number of cycles to...

Page 416: ...1010 11 cycles inserted 1011 13 cycles inserted 1100 15 cycles inserted 1101 17 cycles inserted 1110 21 cycles inserted 1111 25 cycles inserted Note IW 2 0 specify the number of wait cycles to be inserted into read and write cycles when MPX interface is selected IW 1 0 specify the number of wait cycles to be inserted into first data 00 1 cycle inserted into read cycle and no cycle inserted into wr...

Page 417: ...WA PCWB SAB SAA R W R W R W R W R W R W R W R W R W R W R W R R W R W R R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEHB TEHA TEDB TEDA R W R W R W R R W R W R W R R W R W R W R W R W R W R R W Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 0 R Reserved This bit is always read as 0 The write value should always be 0 30 to 28 ...

Page 418: ... A Wait cycle for low speed PCMCIA The number of wait cycles specified by these bits is added to the number designated by CSnWCR These bits are valid when the access area of PCMCIA interface is first half of area 5 or 6 00 No wait cycle inserted 01 15 wait cycles inserted 10 30 wait cycles inserted 01 50 wait cycles inserted 21 20 PCWB 00 R W PCMCIA Wait B Wait cycle for low speed PCMCIA The numbe...

Page 419: ...001 1 cycle inserted 0010 2 cycles inserted 0011 3 cycles inserted 0100 4 cycles inserted 0101 5 cycles inserted 0110 6 cycles inserted 0111 7 cycles inserted 1000 8 cycles inserted 1001 9 cycles inserted 1010 11 cycles inserted 1011 13 cycles inserted 1100 15 cycles inserted 1101 17 cycles inserted 1110 21 cycles inserted 1111 25 cycles inserted Note Specify the number of wait cycle designated by...

Page 420: ...inserted 101 9 wait cycles inserted 110 12 wait cycles inserted 111 15 wait cycles inserted 11 0 R Reserved This bit is always read as 0 The write value should always be 0 10 to 8 TEDB 000 R W OE WE Assert Delay B These bits set the delay time from address output to OE WE assertion for the access of second half area of PCMCIA interface 000 No wait cycle inserted 001 1 wait cycle inserted 010 2 wai...

Page 421: ...wait cycles inserted 100 6 wait cycles inserted 101 9 wait cycles inserted 110 12 wait cycles inserted 111 15 wait cycles inserted 3 0 R Reserved This bit is always read as 0 The write value should always be 0 2 to 0 TEHB 000 R W OE WE Negate Address Delay B These bits set the delay time from OE WE negation to address hold for the access of second half area of PCMCIA interface 000 No wait cycle in...

Page 422: ...ically generated to reach the access size In this case access is performed by incrementing the addresses corresponding to the bus width For example when a longword access is performed at the area with an 8 bit width in the SRAM interface each address is incremented one by one and then access is performed four times In the 32 byte transfer a total of 32 byte data is continuously transferred accordi...

Page 423: ...sert Word 4n 1 Data 15 to 8 Data 7 to 0 Assert Assert 4n 2 1 Data 15 to 8 Data 7 to 0 Assert Assert Longword 4n 1 Data 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0 Assert Assert Assert Assert Table 11 10 16 Bit External Device Big Endian Access and Data Alignment Operation Data Bus Strobe Signals Access Size Address No D31 to D24 D23 to D16 D15 to D8 D7 to D0 WE3 WE2 WE1 WE0 Byte 2n 1 Data 7 to...

Page 424: ...n Access and Data Alignment Operation Data Bus Strobe Signals Access Size Address No D31 to D24 D23 to D16 D15 to D8 D7 to D0 WE3 WE2 WE1 WE0 Byte n 1 Data 7 to 0 Assert Word 2n 1 Data 15 to 8 Assert 2n 1 2 Data 7 to 0 Assert Longword 4n 1 Data 31 to 24 Assert 4n 1 2 Data 23 to 16 Assert 4n 2 3 Data 15 to 8 Assert 4n 3 4 Data 7 to 0 Assert ...

Page 425: ...sert Word 4n 1 Data 15 to 8 Data 7 to 0 Assert Assert 4n 2 1 Data 15 to 8 Data 7 to 0 Assert Assert Longword 4n 1 Data 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0 Assert Assert Assert Assert Table 11 13 16 Bit External Device Little Endian Access and Data Alignment Operation Data Bus Strobe Signals Access Size Address No D31 to D24 D23 to D16 D15 to D8 D7 to D0 WE3 WE2 WE1 WE0 Byte 2n 1 Data 7...

Page 426: ...ian Access and Data Alignment Operation Data Bus Strobe Signals Access Size Address No D31 to D24 D23 to D16 D15 to D8 D7 to D0 WE3 WE2 WE1 WE0 Byte n 1 Data 7 to 0 Assert Word 2n 1 Data 7 to 0 Assert 2n 1 2 Data 15 to 8 Assert Longword 4n 1 Data 7 to 0 Assert 4n 1 2 Data 15 to 8 Assert 4n 2 3 Data 23 to 16 Assert 4n 3 4 Data 31 to 24 Assert ...

Page 427: ...mber is 0 the RDY signal is ignored When the burst ROM interface is used the number of transfer cycles for a burst cycle is selected from a range of 2 to 9 according to the number of wait cycles The setup time and hold time cycle number of the address and CS0 signals to the read and write strobe signals can be set within a range of 0 to 7 cycles by CS0WCR The BS hold cycles can be set within a ran...

Page 428: ... SRAM interface is used a bus width of 8 16 or 32 bits is selectable with bits SZ 1 0 in CS2BCR When the MPX interface is used a bus width of 32 bits should be selected through bits SZ 1 0 in CS2BCR When area 2 is accessed the CS2 signal is asserted except for DDR SDRAM area In the case where the SRAM interface is set the RD signal which can be used as OE and write control signals WE0 to WE3 are a...

Page 429: ...e through the external wait pin RDY When the insert number is 0 the RDY signal is ignored The setup time and hold time cycle number of the address and CS4 signals to the read and write strobe signals can be set within a range of 0 to 7 cycles by CS4WCR The BS hold cycles can be set within a range of 0 to 1 when the number of read and write strobe setup wait is 1 or more When the DDR SDRAM or PCI i...

Page 430: ...it cycles can be specified within a range from 0 to 50 cycles through bits PCWA 1 0 and PCWB 1 0 The number of wait cycles specified by CS5PCR is added to the value specified by IW 3 0 in CS5WCR or PCIW 3 0 in CS5PCR When the DDR SDRAM is used see section 12 DDR SDRAM Interface DDRIF 7 Area 6 For area 6 external address bits A28 to A26 are 110 The interfaces that can be set for this area are the S...

Page 431: ...RAM interface of this LSI are output primarily based on the SRAM connection Figure 11 4 shows the basic timing of the SRAM interface A no wait normal access is completed in two cycles The BS signal is asserted for one cycle to indicate the start of a bus cycle The CSn signal is asserted at the rising edge of the clock in the T1 state and negated at the next rising edge of the clock in the T2 state...

Page 432: ...tate Controller LBSC Rev 1 00 Oct 01 2007 Page 366 of 1956 REJ09B0256 0100 T1 CLKOUT A25 to A0 CSn RDWR RD D31 to D0 read WEn D31 to D0 Write BS T2 RDY DACKn DA DA Dual address DMA Figure 11 4 Basic Timing of SRAM Interface ...

Page 433: ...how examples of the connection to SRAM with data width of 32 16 and 8 bits A16 A0 CS OE I O7 I O0 WE A18 A2 CSn RD D31 D24 WE3 D23 D16 WE2 D15 D8 WE1 D7 D0 WE0 This LSI 128 K 8 bit SRAM A16 A0 CS OE I O7 I O0 WE A16 A0 CS OE I O7 I O0 WE A16 A0 CS OE I O7 I O0 WE Figure 11 5 Example of 32 Bit Data Width SRAM Connection ...

Page 434: ...16 A0 CS OE I O7 I O0 WE A17 This LSI A1 CSn RD D15 D8 WE1 D7 D0 WE0 A16 A0 CS OE I O7 I O0 WE 128 K 8 bit SRAM Figure 11 6 Example of 16 Bit Data Width SRAM Connection A16 A0 CSn RD D7 D0 WE0 A16 A0 CS OE I O7 I O0 WE This LSI 128K 8 bit SRAM Figure 11 7 Example of 8 Bit Data Width SRAM Connection ...

Page 435: ...e wait is inserted in accordance with the wait control bits For details see section 11 4 4 CSn Wait Control Register CSnWCR A specified number of Tw cycles is inserted as wait cycles in accordance with the CSnWCR setting The insertion timing of the wait cycle is shown in figure 11 8 T1 CLKOUT A25 to A0 CSn RDWR RD D31 to D0 read WE D31 to D0 Write BS Tw T2 RDY DACK DA DA Dual address DMA Figure 11...

Page 436: ... cycle is specified as a software wait The RDY signal is sampled at the transition from the Tw state to the T2 state Therefore the assertion of the RDY signal has no effect in the T1 cycle or in the first Tw cycle The RDY signal is sampled on the rising edge of the clock T1 CLKOUT A25 to A0 CSn RDWR RD read D31 to D0 read WEn Write D31 to D0 Write BS Tw Twe T2 RDY DACKn DA DA Dual address DMA Figu...

Page 437: ...ller LBSC Rev 1 00 Oct 01 2007 Page 371 of 1956 REJ09B0256 0100 3 Read Strobe Negate Timing When the SRAM interface is used the negation timing of the strobe signal during a read operation can be specified through the RDH bit in CSnWCR ...

Page 438: ...p wait CSnWCR RDS 0 to 7 TH1 TH2 RD Hold wait SnWCR RDH 0 to 7 TAS1 Address Setup wait CSnWCR RDS 0 to 7 Tw Access wait CSnWCR IW 0 to 25 TAH1 Address Hold wait CSnWCR AHS 0 to 7 TS1 WE Setup wait CSnWCR WTS 0 to 7 TH1 TH2 WE Hold wait CSnWCR WTH 0 to 7 TAS1 Address Setup wait CSnWCR ADS 0 to 7 Tw Access wait CSnWCR IW 0 to 25 TAH1 Address Hold wait CSnWCR ADH 0 to 7 CLKOUT CLKOUT Figure 11 10 SRA...

Page 439: ...n CSnBCR n 0 to 2 and 4 to 6 Similarly when 16 bit ROM is used 4 8 or 16 accesses can be set when 32 bit ROM is used 4 or 8 accesses can be set The RDY signal is always sampled when one or more wait cycles are set Even when no wait is specified in the burst ROM settings two access cycles are inserted in the second and subsequent accesses as shown in figure 11 12 A writing operation for the burst R...

Page 440: ...256 0100 T1 TB1 TB2 TB1 TB2 TB1 TB2 T2 CLKOUT A25 to A5 A4 to A0 CSn RDWR RD D31 to D0 read BS RDY Figure 11 11 Burst ROM Basic Access Timing T1 Twe TB2 TB1 Tw TB2 Tw Tw TB1 TB2 Tw T2 TB1 CLKOUT A25 to A5 A4 to A0 CSn RDWR RD D31 to D0 read BS RDY Figure 11 12 Burst ROM Wait Access Timing ...

Page 441: ... 14 shows an example of PCMCIA card connection to this LSI To enable hot insertion of PCMCIA cards i e insertion or removal while system power is being supplied a three state buffer must be connected between this LSI bus interface and the PCMCIA cards Since operation in big endian mode is not explicitly stipulated in the JEIDA PCMCIA standard this LSI supports the PCMCIA interface only in little e...

Page 442: ...s accessed bits IW 3 0 in CS5WCR are selected and when area 6 is accessed bits IW 3 0 in CS6WCR are selected In 32 byte transfer a total of 32 bytes are transferred continuously according to the set bus width The first access is performed on the data for which there was an access request and the remaining accesses are performed in wrap around method according to the set bus width The bus is not re...

Page 443: ...he size of DMA transfer is 16 byte After the DMA burst transfer has finished that DACKBST was enabled set the DACKBST bit to 1 again before starting the next DMA transfer CExx DACK CExx DACK a IO Card Interface DACKBST Invalid b ATA Complement Mode DACKBST Valid Note Number of DMA transter times 4 DMA transter size word 16 bit Figure 11 14 CExx and DACK Output of ATA Complete Mode in DMA Transfer ...

Page 444: ... 1 0 1 Invalid Upper write data Odd 16 Read 8 Even 1 0 0 Invalid Read data Odd 0 1 1 Read data Invalid 16 Even 0 0 0 Upper read data Lower read data Odd Write 8 Even 1 0 0 Invalid Write data Odd 0 1 1 Write data Invalid 16 Even 0 0 0 Upper write data Lower write data Odd Read 8 Even 0 1 0 0 Invalid Read data Odd 0 0 1 1 Read data Invalid Dynamic Bus Sizing 2 16 Even 0 0 0 0 Upper read data Lower r...

Page 445: ...Read data read Odd ATA comple ment mode 16 Even 1 0 0 Upper read data Lower read data Odd PIO 8 Even 0 1 0 Invalid Write data write Odd 16 Even 1 0 0 Upper write data Lower write data Odd DMA 8 Even 0 1 0 Invalid Read data read Odd 1 1 0 Read data Invalid 16 Even 1 1 1 Upper read data Lower read data Odd DMA 8 Even 1 1 0 Invalid Write data write Odd 1 1 0 Write data Invalid 16 Even 1 1 1 Upper wri...

Page 446: ... OE WE PGM WAIT A25 to A0 D15 to D0 RDWR CE2B CE2A RD WE1 CE1B CS6 CE1A CS5 IORD IOWR RDY IOIS16 G DIR D7 to D0 D15 to D8 D7 to D0 D15 to D8 G DIR G G G DIR G DIR PCC_REG REG REG PCカードメモリ IO PCカードメモリ IO Card detection circuit Card detection circuit This LSI A25 to A0 A25 to A0 D15 to D0 D15 to D0 CD1 CD2 CD1 CD2 PC card memory I O PC card memory I O Figure 11 15 Example of PCMCIA Interface ...

Page 447: ... Figure 11 16 shows the basic timing for the PCMCIA memory card interface and figure 11 17 shows the wait timing for the PCMCIA memory card interface CLKOUT Tpcm1 Tpcm2 A25 to A0 CExx RDWR D15 to D0 read D15 to D0 Write RD read WE1 Write BS DACK DA PCC_REG DA Dual address DMA Figure 11 16 Basic Timing for PCMCIA Memory Card Interface ...

Page 448: ...2007 Page 382 of 1956 REJ09B0256 0100 CLKOUT Tpcm0 A25 to A0 RDWR CExx RD WE1 BS RDY PCC_REG read D15 to D0 read D15 to D0 Write Write DACK DA Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w DA Dual address DMA Figure 11 17 Wait Timing for PCMCIA Memory Card Interface ...

Page 449: ...is high during the word size I O bus cycle the I O port is recognized as eight bits in bus width In this case a data access for only eight bits is performed in the I O bus cycle being executed and this is automatically followed by a data access for the remaining eight bits Dynamic bus sizing is also performed for byte size access to address 2n 1 Figure 11 20 shows the basic timing for dynamic bus ...

Page 450: ...age 384 of 1956 REJ09B0256 0100 CLKOUT A25 to A0 RDWR CExx IORD Write IOWR Write DACK DA D15 to D0 Write D15 to D0 Write BS RDY IOIS16 Tpci0 Tpci0w Tpci1 Tpci1w Tpci1w Tpci2 Tpci2w PCC_REG WE0 DA Dual address DMA Figure 11 19 Wait Timing for PCMCIA I O Card Interface ...

Page 451: ...9B0256 0100 Tpci Tpci0 Tpci1w Tpci2 Tpci2w Tpci0 Tpci Tpci2 Tpci1w Tpci2w CLKOUT A25 to A1 A0 RDWR IORD WE2 read IOWR WE3 Write D15 to D0 Write D15 to D0 read BS IOIS16 CExx PCC_REG WE0 RDY DACK DA DA Dual address DMA Figure 11 20 Dynamic Bus Sizing Timing for PCMCIA I O Card Interface ...

Page 452: ...n the data phase Therefore a negation cycle does not occur in the case of minimum pitch access The FRAME signal is asserted at the rising edge in Tm1 and negated at the start of the last data transfer cycle in the data phase Therefore an external device for the MPX interface must internally store the address information and access size output in the address phase and perform data input output for ...

Page 453: ...g is shown below When the MPX interface is used for areas 1 2 and 4 to 6 a bus size of 32 bits should be specified by CSnBCR In wait control either waits by CSnWCR or waits by the RDY pin can be inserted In a read one wait cycle is automatically inserted after address output even if CSnWCR is cleared to 0 Tm1 CLKOUT A RD FRAME CSn RDWR D31 to D0 BS Tmd1w Tmd1 RDY DACK DA D0 DA Dual address DMA Fig...

Page 454: ...er LBSC Rev 1 00 Oct 01 2007 Page 388 of 1956 REJ09B0256 0100 Tm1 CLKOUT A RD FRAME CSn RDWR D31 to D0 BS Tmd1w Tmd1w Tmd1 RDY DACK DA D0 DA Dual address DMA Figure 11 23 MPX Interface Timing 2 Single Read IW 0 One External Wait Inserted ...

Page 455: ...ontroller LBSC Rev 1 00 Oct 01 2007 Page 389 of 1956 REJ09B0256 0100 Tm1 CLKOUT A RD FRAME CSn RDWR D31 to D0 BS Tmd1 RDY DACK DA D0 DA Dual address DMA Figure 11 24 MPX Interface Timing 3 Single Write Cycle IW 0 No External Wait ...

Page 456: ...BSC Rev 1 00 Oct 01 2007 Page 390 of 1956 REJ09B0256 0100 Tm1 CLKOUT A RD FRAME CSn RDWR D31 to D0 BS Tmd1w Tmd1w Tmd1 RDY DACK DA D0 DA Dual address DMA Figure 11 25 MPX Interface Timing 4 Single Write Cycle IW 1 One External Wait Inserted ...

Page 457: ... Page 391 of 1956 REJ09B0256 0100 T m1 CLKOUT RD FRAME CSn RDWR D31 to D0 BS T md1w T md1 T md2 T md3 T md4 T md5 T md6 T md7 T md8 RDY DACK DA D2 D3 D4 D6 D7 D8 D5 A D1 DA Dual address DMA Figure 11 26 MPX Interface Timing 5 Burst Read Cycle IW 0 No External Wait ...

Page 458: ...2007 Page 392 of 1956 REJ09B0256 0100 T m1 CLKOUT A RD FRAME CSn RDWR D31 to D0 BS T md1w T md1 T md2w T md2 T md3 T md7 T md8w T md8 RDY DACK DA D7 D8 D2 D3 D1 DA Dual address DMA Figure 11 27 MPX Interface Timing 6 Burst Read Cycle IW 0 External Wait Control ...

Page 459: ...007 Page 393 of 1956 REJ09B0256 0100 T m1 CLKOUT A RD FRAME CSn RDWR D31 to D0 BS T md1 T md2 T md3 T md4 T md5 T md6 T md7 T md8 RDY DACK DA D1 D2 D3 D4 D5 D6 D7 D8 DA Dual address DMA Figure 11 28 MPX Interface Timing 7 Burst Write Cycle IW 0 No External Wait ...

Page 460: ...2007 Page 394 of 1956 REJ09B0256 0100 D3 D2 T m1 CLKOUT A RD FRAME CSn RDWR D31 to D0 BS T md1w T md1 T md2w T md2 T md3 T md7 T md8w T md8 RDY DACK DA D1 D7 D8 DA Dual address DMA Figure 11 29 MPX Interface Timing 8 Burst Write Cycle IW 1 External Wait Control ...

Page 461: ...EJ09B0256 0100 T m1 CLKOUT RD FRAME CSn RDWR D31 to D0 BS T md1w T md1 T md2 T md3 T md4 T md5 T md6 T md7 T md8 RDY DACK DA D2 D3 D4 D6 D7 D8 D5 A D1 DA Dual address DMA Figure 11 30 MPX Interface Timing 9 Burst Read Cycle IW 0 No External Wait 32 Bit Bus Width 32 Byte Data Transfer ...

Page 462: ...6 REJ09B0256 0100 T m1 CLKOUT A RD FRAME CSn RDWR D31 to D0 BS T md1w T md1 T md2w T md2 T md3 T md7 T md8w T md8 RDY DACK DA D7 D8 D2 D3 D1 DA Dual address DMA Figure 11 31 MPX Interface Timing 10 Burst Read Cycle IW 0 External Wait Control 32 Bit Bus Width 32 Byte Data Transfer ...

Page 463: ... REJ09B0256 0100 T m1 CLKOUT A RD FRAME CSn RDWR D31 to D0 BS T md1 T md2 T md3 T md4 T md5 T md6 T md7 T md8 RDY DACK DA D1 D2 D3 D4 D5 D6 D7 D8 DA Dual address DMA Figure 11 32 MPX Interface Timing 11 Burst Write Cycle IW 0 No External Wait 32 Bit Bus Width 32 Byte Data Transfer ...

Page 464: ...6 REJ09B0256 0100 D3 D2 T m1 CLKOUT A RD FRAME CSn RDWR D31 to D0 BS T md1w T md1 T md2w T md2 T md3 T md7 T md8w T md8 RDY DACK DA D1 D7 D8 DA Dual address DMA Figure 11 33 MPX Interface Timing 12 Burst Write Cycle IW 1 External Wait Control 32 Bit Bus Width 32 Byte Data Transfer ...

Page 465: ...only the WE signal for the byte being read is asserted Assertion is synchronized with the falling edge of the CLKOUT clock in the same way as for the WE signal while negation is synchronized with the rising edge of the CLKOUT clock in the same way as for the RD signal In 32 byte transfer a total of 32 bytes are transferred continuously according to the set bus width The first access is performed o...

Page 466: ... State Controller LBSC Rev 1 00 Oct 01 2007 Page 400 of 1956 REJ09B0256 0100 T1 T2 CLKOUT A25 to A0 CSn RDWR RD D31 to D0 read BS DACKn DA RDY WEn DA Dual address DMA Figure 11 35 Byte Control SRAM Basic Read Cycle No Wait ...

Page 467: ...troller LBSC Rev 1 00 Oct 01 2007 Page 401 of 1956 REJ09B0256 0100 T1 Tw T2 CLKOUT A25 to A0 CSn RDWR RD D31 to D0 read BS DACKn DA RDY WEn DA Dual address DMA Figure 11 36 Byte Control SRAM Basic Read Cycle One Internal Wait Cycle ...

Page 468: ...LBSC Rev 1 00 Oct 01 2007 Page 402 of 1956 REJ09B0256 0100 T1 Tw Twe T2 CLKOUT A25 to A0 CSn RDWR RD D31 to D0 read BS DACKn DA RDY WEn DA Dual address DMA Figure 11 37 Byte Control SRAM Basic Read Cycle One Internal Wait One External Wait ...

Page 469: ...e next access is started The process for wait cycle insertion consists of inserting idle cycles between the access cycles as shown in section 11 4 3 CSn Bus Control Register CSnBCR If bits IWW IWRWD IWRWS IWRRD and IWRRS in CSnBCR n 0 to 2 and 4 to 6 are used to set the number of idle cycles between accesses the number of inserted idle cycles is only the specified number of idle cycles minus the n...

Page 470: ... 1956 REJ09B0256 0100 T1 CLKOUT CSm CSn A25 to A0 BS RDWR RD D31 to D0 T2 Twait T1 T2 Twait T1 T2 Area m space read Area m inter access wait specificaton Area n inter access wait specification Area n space read Area n space Write Figure 11 38 Wait Cycles between Access Cycles ...

Page 471: ...de releasing the bus and turning on the output buffer on the side receiving the bus simultaneously with respect to the bus control signals it is possible to eliminate the signal high impedance period It is not necessary to provide the pull up resistors usually inserted in these control signal lines to prevent incorrect operation due to external noise in the high impedance state Bus transfer is exe...

Page 472: ...R CSn RD WEn RDWR A25 to A0 D31 to D0 Write HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ b Slave mode device access HiZ HiZ HiZ HiZ HiZ HiZ HiZ CLKOUT Master access Master access Slave access Master access Master access Slave access Asserted for least 2 cycles Must be asserted for at least 2 cycles Negated within 2 cycles Must be negated within 2 cycles Figure 11 39 Arbitration Sequence...

Page 473: ...e is as follows First the bus use permission signal is asserted in synchronization with the rising edge of the clock The address bus and data bus go to the high impedance state in synchronization from next rising edge of the clock after this BACK assertion At the same time the bus control signals BS CSn WEn RD RDWR CE2A and CE2B go to the high impedance state These bus control signals are negated ...

Page 474: ...ed When designing an application system that includes this LSI all control including initialization and low power consumption control are supposed to be carried out by this LSI In a power on reset this LSI will not accept bus requests from the slave until the BREQ enable bit BCR BREQEN is set to 1 To ensure that the slave processor does not access memory requiring initialization before use write 1...

Page 475: ...es The data bus width of the DDRIF is 32 bits Supports DDR SDRAM self refreshing Supports the DDR266 133MHz DDR200 100MHz Efficient data transfer is possible using the SuperHyway bus Internal bus Supports a 4 bank DDR SDRAM Supports a burst length of 2 Connectable memory size 256 Mbits 512 Mbits 1 Gbit and 2 Gbits Address bit width bit for supported memory is as follows DDR SDRAM data bus width is...

Page 476: ...erface The bus width is 64 bits and the maximum operating frequency is 133 MHz The LCDC interface LCDIF is an interface with the LCDC The bus width is 32 bits and the maximum operating frequency is 66 MHz The arbiter ARBT arbitrates SHIF that accesses the DDR SDRAM and LCDIF requests among the requests from the abovementioned interfaces The DDR SDRAM controller DDRC controls read write accesses to...

Page 477: ...ock enable Output When this pin goes high the clock signal is active When this pin goes low the clock signal is inactive M_CS Chip select Output Chip select output M_WE Write enable Output Write enable output M_A13 to M_A0 Address Output Row column address M_BA1 M_BA0 Bank active Output Bank address output M_D31 to M_D0 Data I O Data I O M_DQS3 to M_DQS0 I O data strobe I O I O data strobe M_DQM3 ...

Page 478: ...D16 M_D15 to M_D8 M_D7 to M_D0 Byte access at address 0 Data 7 to 0 Byte access at address 1 Data 7 to 0 Byte access at address 2 Data 7 to 0 Byte access at address 3 Data 7 to 0 Byte access at address 4 Data 7 to 0 Byte access at address 5 Data 7 to 0 Byte access at address 6 Data 7 to 0 Byte access at address 7 Data 7 to 0 Word access at address 0 Data 15 to 8 Data 7 to 0 Word access at address ...

Page 479: ...to 0 Byte access at address 6 Data 7 to 0 Byte access at address 7 Data 7 to 0 Word access at address 0 Data 15 to 8 Data 7 to 0 Word access at address 2 Data 15 to 8 Data 7 to 0 Word access at address 4 Data 15 to 8 Data 7 to 0 Word access at address 6 Data 15 to 8 Data 7 to 0 Longword access at address 0 Data 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0 Longword access at address 4 Data 31 to...

Page 480: ...vailable Bit 31 Example of memory address A 3 0 0000 Other than the above the DDRC wraps around the data on command boundaries read Address A 0 Address A 4 Address A 8 Address A 12 Bit 0 Little Wndian big endian 63 Address A 4 32 31 Address A 0 0 Address A 12 Address A 8 Write 64 bit width DDR SDRAM 32 bit Time Time 63 Address A 0 32 31 Address A 4 0 Address A 8 Address A 12 Time Figure 12 2 Data ...

Page 481: ...g endian mode when accessing bits 63 to 32 specify address 8n 0 When accessing bits 31 to 0 specify address 8n 4 Table 12 4 Register Configuration Register Name Abbreviation R W Area P4 Address 1 Area 7 Address 1 Access Size Memory interface mode register MIM R W H FE80 0008 H 1E80 0008 32 DDR SDRAM control register SCR R W H FE80 0010 H 1E80 0010 32 DDR SDRAM timing register STR R W H FE80 0018 H...

Page 482: ...00 0000 H 0000 0000 0000 0000 Retained Retained DDR SDRAM row attribute register SDR H 0000 0000 0000 0100 H 0000 0000 0000 0100 Retained Retained DDR SDRAM mode register SDMR Only writing Only writing Only writing Only writing DDR SDRAM back up register DBK H 0000 0000 0000 000x 2 H 0000 0000 0000 000x 2 Retained Retained Notes 1 The initial value of bit 8 ENDIAN bit depends on the setting of ext...

Page 483: ...R R R 32 48 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BOMODE PC KE SEL FS R MODE R R W R R R R R R R R R R R W R R W R W Note Depends on the setting of external pins MD5 Bit Initial value R W Bit Initial value R W Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 63 to 49 All 0 R Reserved These bits are always read as 0 The write value should always be 0 48 0 R Reserved ...

Page 484: ...the setting for enabling the CKE pin by the SMS bit in SCR is used for DDR SDRAM initialization 43 to 35 All 0 R Reserved These bits are always read as 0 The write value should always be 0 34 SELFS 0 R Self Refresh Decision Decides whether the DDR SDRAM is in the self refresh state When this bit is set to 1 the DDR SDRAM is in the self refresh state When this bit is cleared to 0 the DDR SDRAM is n...

Page 485: ...rs an auto refresh request is generated in the controller and auto refreshing is performed Note that the counter is cleared to 0 at the match and then begins incrementing again The single auto refresh request that has been generated is recorded max When the DCE and DRE bits are set to 1 and the RMODE bit is cleared to 0 an auto refresh request is not cleared until auto refreshing is performed To s...

Page 486: ...e 0 Little endian mode 7 to 4 All 0 R Reserved These bits are always read as 0 The write value should always be 0 3 DLLEN 0 R W DLL Enable Sets whether the DLL for generating the read timing for the DDR SDRAM is valid or invalid When this bit is set to 1 the DLL is enabled and read access to memory is possible 2 1 All 0 R Reserved These bits are always read as 0 The write value should always be 0 ...

Page 487: ...20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMS R W R W R W R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 32 47 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Bit Initial value R W Bit Initial value R W Bit Initia...

Page 488: ...ation Sequence After the DDR SDRAM has been initialized normal operation 000 is specified 000 Normal operation 001 The NOP command is issued valid only when the DCE bit in MIM is set to 1 010 The PREALL command is issued valid only when the DCE bit in MIM is set to 1 011 The M_CKE pin is enabled At that time the DESELECT command is issued valid only when the DCE bit in MIM is set to 1 100 The REFA...

Page 489: ...0 0 0 0 0 0 SRP SRCD SCL SRC SRAS SRRD SWR SRFC R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 32 47 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Bit Initial value R W Bit Initial value R W Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 63 to 20 All 0 R Reserv...

Page 490: ...se bits specify the number of cycles in the same bank for the following access times Trfc 1 From auto refresh to ACT command issuance 2 From auto refresh to auto refresh 000 11 cycles 001 12 cycles 010 13 cycles 011 14 cycles 100 15 cycles Other than above Setting prohibited 12 SWR 0 R W PRE PREALL Command Issuance Cycle Specifies the number of cycles from the last postamble to PRE PREALL command ...

Page 491: ...11 9 cycles Other than above Setting prohibited 7 to 5 SRC 000 R W Auto Refresh ACT Command Issuance Cycle These bits specify the number of cycles in the same bank for the following access times Trc 1 From ACT command issuance to auto refresh 2 From ACT command issuance to ACT command issuance 000 6 cycles 001 7 cycles 010 8 cycles 011 9 cycles 100 10 cycles 101 11 cycles 110 12 cycles 111 13 cycl...

Page 492: ...uance to ACT command issuance Trp 0 3 cycles 1 4 cycles 12 4 4 DDR SDRAM Row Attribute Register SDR 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 SPLIT R R R R R R R R R W R ...

Page 493: ... All 0 R Reserved These bits are always read as 0 The write value should always be 0 12 4 5 DDR SDRAM Mode Register SDMR SDMR is used to set the DDR SDRAM mode register and extended mode register Since SDMR is not physically contained in the DDRIF reading this register is invalid Only write addresses have a meaning for the DDR SDRAM and the write data is ignored When SDMR is written to signals are...

Page 494: ... L L L L L L L L L M_CS M_RAS M_CAS M_WE Figure 12 3 Relationship between Write Values in SDMR and Output Signals to Memory Pins For example when the DLL reset release CAS latency of 2 5 cycles sequential burst sequence and burst length of 2 are set to the mode register in the DDR SDRAM the following signals must be output to the DDR SDRAM pins CS low RAS low CAS low WE low BA0 low BA1 low MA13 MA...

Page 495: ... R R 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDBUP R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 32 47 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Bit Initial value R W Bit Initial value R W Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 63 to 1 All 0 R Reserved...

Page 496: ...alize the SDRAM according to the following sequence Otherwise the device may be damaged An example of the initialization sequence for the DDR SDRAM is shown below For details see each memory manufacturer s datasheet 1 Turn on the four power supplies to the DDR SDRAM in the following order VDD VDDQ VREF and VTT 2 After the power supply reference voltage and clock are stabilized maintain the current...

Page 497: ... use the SMS field in SCR to issue the REF command twice 11 Use SDMR to issue the MRS command release the DLL reset MA8 low and determine the operating mode In this case use the setting for the burst length etc that was specified in step 8 12 After the DLL is reset wait for 200 cycles of the memory clock normal memory access will then be possible Match the SDMR setting etc of the DDR SDRAM with th...

Page 498: ...H L L V L V V Write with auto precharge WRITEA H X L H L L V H V V Bank activate ACT H X L L H H V V V V Precharge select bank PRE H X L L H L X L V X Precharge all banks PREALL H X L L H L X H X X Auto refresh REFA H H L L L H X X X X Self refresh entry from IDLE REFS H L L L L H X X X X Self refresh exit REFSX L H H X X X X X X X Power down entry PWRDN H L H X X X X X X X Power down exit PWRDNX ...

Page 499: ...elf refresh mode is set by setting the DRE and RMODE bits in MIM to 1 If the sleep mode of CPU is canceled due to an interrupt the self refresh state is retained Although the self refresh state is entered through the register setting of the DDRIF the following sequence should be used Transition to self refresh state 1 Confirm that the transaction to the memory controller is completed 2 Through sof...

Page 500: ...This operation is required to make the delay adjustment unit in the memory controller operate 8 Set MIM so that the counter for the auto refresh function starts counting and thus drives auto refreshing at a regular interval After this normal memory access is possible 2 Power Down Mode when CKE Goes Low When the PCKE bit in MIM is set the CKE pin level is automatically changed and the DDR SDRAM the...

Page 501: ...er the self refresh state through software before the clock supply is stopped For details on entering canceling the self refresh mode see section 12 5 5 1 Self Refresh Mode 12 5 9 Using SCR to Issue REFA Commands Outside the Initialization Sequence This memory controller automatically opens the DDR SDRAM bank by memory access read write When issuing the REFA command with the SMS bits in SCR be sur...

Page 502: ...bits in SDR Table 12 7 shows the relationship between the DDR SDRAM bus width and the addresses that are output to the address pins according to the setting of the SPLIT bits If a setting not specified in table 12 7 is used correct operation is not guaranteed Table 12 7 DDR SDRAM Address Multiplexing 32 Bit Data Bus SPLIT 3 0 ROW COL M_ BA1 M_ BA0 M_ A13 M_ A12 M_ A11 M_ A10 M_ A9 M_ A8 M_ A7 M_ A...

Page 503: ...the LCDC have the same possibility of being arbitrated In non burst transfers arbitration is performed in 133 1 MHz units Requests are continuously output to the DDRC However in actuality burst and non burst transfers coexist Signals output from the interfaces are used to determine whether a burst transfer is expected or not When making arbitration from non burst transfers to burst transfers if th...

Page 504: ...ous timings should be set in the STR register within the range specified by the DDR SDRAM used Note that the DDRIF only supports 2 5 cycle CAS latency CL T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 tRCD SRCD 1 CL 2 5 ACT MCLK MCS MRAS MCAS MWE MCLK CKE Command MA13 11 MA9 0 MA10 BA1 0 MDQS MDQM MDA READ PRE Row Bank Bank D0 D1 Hi Z Hi Z Row Bank Col 0 Figure 12 5 Basic DDRIF Timing 1 Burst Read 1 2 4 or 8 B...

Page 505: ...9B0256 0100 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 ACT MCLK MCS MRAS MCAS MWE MCLK CKE Command MA13 11 MA9 0 MA10 BA1 0 MDQS MDQM MDA Row WRITE Col 0 PRE Row Bank Bank Bank D0 D1 Hi Z Hi Z tRCD SRCD 1 Figure 12 6 Basic DDRIF Timing 1 Burst Write 1 2 4 or 8 Bytes Without Auto Precharge ...

Page 506: ... T4 T5 T6 T7 T8 T9 T10 CL 2 5 ACT MCLK MCS MRAS MCAS MWE MCLK CKE Command MA13 11 MA9 0 MA10 BA1 0 MDQS MDQM MDA READA ACT Row Bank Bank Bank Row Col 0 Row Row D0 D1 Hi Z Hi Z tRC SRC 011 tRCD SRCD 1 tRP SRP 0 tRAS SRAS 000 Figure 12 7 Basic DDRIF Timing 1 Burst Read 1 2 4 or 8 Bytes With Auto Precharge ...

Page 507: ... T5 T6 T7 T8 T9 T10 ACT MCLK MCS MRAS MCAS MWE MCLK CKE Command MA13 11 MA9 0 MA10 BA1 0 MDQS MDQM MDA Row WRITEA Col 0 ACT Row Bank Row Row Bank Bank D0 D1 Hi Z Hi Z tRC SRC 101 tRCD SRCD 1 tWR SWR 0 tRP SRP 0 tRAS SRAS 010 Figure 12 8 Basic DDRIF Timing 1 Burst Write 1 2 4 or 8 Bytes With Auto Precharge ...

Page 508: ...6 T7 T8 T9 T10 tRCD SRCD 1 CL 2 5 ACT MCLK MCS MRAS MCAS MWE MCLK CKE Command MA13 11 MA9 0 MA10 BA1 0 MDQS MDQM MDA Row READ READ READ READ PRE Col 2 Col 0 Col 4 Col 6 Row Bank Bank Bank Bank Bank Bank D0 D1 D2 D3 D4 D5 D6 D7 Hi Z Hi Z Figure 12 9 Basic DDRIF Timing 4 Burst Read 32 Bytes Without Auto Precharge ...

Page 509: ... T6 T7 T8 T9 tRCD SRCD 1 ACT MCLK MCS MRAS MCAS MWE MCLK CKE Command MA13 11 MA9 0 MA10 BA1 0 MDQS MDQM MDA Row WRITE WRITE WRITE WRITE PRE Col 2 Col 0 Col 4 Col 6 Row Bank Bank Bank Bank Bank Bank Hi Z Hi Z D1 D2 D3 D4 D5 D6 D7 D0 Figure 12 10 Basic DDRIF Timing 4 Burst Write 32 Bytes Without Auto Precharge ...

Page 510: ...2007 Page 444 of 1956 REJ09B0256 0100 T0 T1 T2 T3 T4 tRP SRP 1 PREALL MCLK MCS MRAS MCAS MWE MCLK CKE Command MA13 11 MA9 0 MA10 BA1 0 MDQS MDQM MDA ACT Row Bank Hi Z Hi Z Row Figure 12 11 Basic DDRIF Timing Precharge all Banks PREALL to Bank Activate ACT ...

Page 511: ... Notes 1 Sets the operating mode and other necessary parameters 2 For mode register setting BA1 low BA0 low For extended mode register setting BA1 low BA0 high MCLK MCS MRAS MCAS MWE MCLK CKE Command MA13 11 MA9 0 MA10 BA1 0 MDQS MDQM MDA 1 Hi Z Hi Z 1 2 Figure 12 12 Basic DDRIF Timing Mode Register Set MRS ...

Page 512: ... 446 of 1956 REJ09B0256 0100 REFA REFA MCLK MCS MRAS MCAS MWE MCLK CKE T0 T1 Command MA13 11 MA9 0 BA1 0 Row ACT Bank Row MA10 tRFC 11 to 15 cycles tRFC 11 to 15 cycles Auto refresh Figure 12 13 Basic DDRIF Timing Auto Refresh REFA Enter Exit to Bank Activate ACT ...

Page 513: ...RAM used when driving CKE high 2 This timing should satisfy the conditions specified by the DDR SDRAM used tXSNR is for a non READ command and tXSRD is for a READ command tXSRD should usually be 200 clock cycles or longer MCLK T0 T1 T0 T1 CKE Command MA9 0 MA13 11 MA10 BA1 0 Any Command 1 Self refresh Figure 12 14 Basic DDRIF Timing Self Refresh Entry from IDLE REFS Self Refresh Exit REFSX to Any ...

Page 514: ...Section 12 DDR SDRAM Interface DDRIF Rev 1 00 Oct 01 2007 Page 448 of 1956 REJ09B0256 0100 ...

Page 515: ...perHyway bus The PCIC supports both the host bus bridge mode and normal mode non host mode In host busbridge mode PCI bus arbitration control is available and in normal mode arbitration is executed by the external PCI bus arbiter 13 1 Features The PCIC has the following features Supports subset of PCI Local Bus Specification Revision 2 2 PCI bus operating speeds of 33 MHz 66 MHz 32 bit data bus PC...

Page 516: ...t output INTA in normal mode Supports both big endian and little endian formats for the SuperHyway bus the PCI bus operates in the little endian format Number of devices which can be connected 33 MHz 4 or less 66 MHz 1 The PCIC does not support the following PCI functions Cache support no SBO or SDONE pin Address wrap around mechanism PCI JTAG other modules in this LSI can support the JTAG feature...

Page 517: ...ntrol PCI local bus PCIRESET PCI standard signal Figure 13 1 PCIC Block Diagram The PCIC comprises two blocks the PCI bus interface and SuperHyway bus interface block The PCI bus interface block comprises the PCI configuration register local register PCI master and PCI target controller The functions of the PCI bus interface are transaction control on the PCI local bus The SuperHyway bus interface...

Page 518: ... AD 31 0 and CBE 3 0 PCICLK CLK Input PCI Clock Provides timing for all transactions on the PCI bus PCIFRAME FRAME I O STRI PCI Frame Current initiator drives this signal which indicates the start and duration or end of a transaction TRDY TRDY I O STRI PCI Target Ready Selected target drives this signal which indicates the target is ready to execute a transaction During a write this signal indicat...

Page 519: ... is requesting an interrupt input in host bus bridge mode This signal is used to request an interrupt output O D in normal mode REQ3 to REQ1 4 REQ 3 1 Input PCI Bus Request Available only in host bus bridge mode GNT3 to GNT1 GNT 3 1 Output TRI PCI Bus Grant Available only in host bus bridge mode REQ0 REQOUT REQ0 I O TRI PCI Bus Request Functions as an input or an output in host bus bridge mode and...

Page 520: ...er PCIC Rev 1 00 Oct 01 2007 Page 454 of 1956 REJ09B0256 0100 Legend TRI Tri state STRI Sustained tri state O D Open Drain Note Clear the PCIC related interrupt masks only after the PCIC related pins are selected as the PCIC ...

Page 521: ...1E04 0008 8 PCI program interface register PCIPIF R W R H FE04 0009 H 1E04 0009 8 PCI sub class code register PCISUB R W R H FE04 000A H 1E04 000A 8 PCI base class code register PCIBCC R W R H FE04 000B H 1E04 000B 8 PCI cacheline size register PCICLS R R H FE04 000C H 1E04 000C 8 PCI latency timer register PCILTM R W R W H FE04 000D H 1E04 000D 8 PCI header type register PCIHDR R R H FE04 000E H ...

Page 522: ... H 1E04 0100 32 PCI local space register 0 PCILSR0 R W R H FE04 0104 H 1E04 0104 32 PCI local space register 1 PCILSR1 R W R H FE04 0108 H 1E04 0108 32 PCI local address register 0 PCILAR0 R W R H FE04 010C H 1E04 010C 32 PCI local address register 1 PCILAR1 R W R H FE04 0110 H 1E04 0110 32 PCI interrupt register PCIIR R WC R H FE04 0114 H 1E04 0114 32 PCI interrupt mask register PCIIMR R W R H FE...

Page 523: ...E04 01F4 H 1E04 01F4 32 PCI I O bank register PCIIOBR R W H FE04 01F8 H 1E04 01F8 32 PCI I O bank master register PCIIOBMR R W H FE04 01FC H 1E04 01FC 32 PCI cache snoop control register 0 PCICSCR0 R W H FE04 0210 H 1E04 0210 32 PCI cache snoop control register 1 PCICSCR1 R W H FE04 0214 H 1E04 0214 32 PCI cache snoop address register 0 PCICSAR0 R W H FE04 0218 H 1E04 0218 32 PCI cache snoop addre...

Page 524: ...r PCICLS H 20 H 20 Retained Retained PCI latency timer register PCILTM H 00 H 00 Retained Retained PCI header type register PCIHDR H 00 H 00 Retained Retained PCI BIST register PCIBIST H 00 H 00 Retained Retained PCI I O base address register PCIIBAR H 0000 0001 H 0000 0001 Retained Retained PCI Memory base address register 0 PCIMBAR0 H 0000 0000 H 0000 0000 Retained Retained PCI Memory base addre...

Page 525: ...errupt mask register PCIIMR H 0000 0000 H 0000 0000 Retained Retained PCI error address information register PCIAIR H xxxx xxxx H xxxx xxxx Retained Retained PCI error command information register PCICIR H xx00 000x H xx00 000x Retained Retained PCI arbiter interrupt register PCIAINT H 0000 0000 H 0000 0000 Retained Retained PCI arbiter interrupt mask register PCIAINTM H 0000 0000 H 0000 0000 Reta...

Page 526: ...etained PCI cache snoop address register 1 PCICSAR1 H 0000 0000 H 0000 0000 Retained Retained PCI PIO data register PCIPDR H xxxx xxxx H xxxx xxxx Retained Retained Legend x Undefined 13 3 1 PCIC Enable Control Register PCIECR 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Bit Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0...

Page 527: ...R R R R R R R R R PCI R W Bit Bit Name Initial Value R W Description 15 to 0 VID H 1912 SH R PCI R PCI Vender ID Indicates the PCI device manufacture identifier vender ID that is allocated by PCI SIG Renesas Technology s vendor ID is H 1912 2 PCI Device ID Register PCIDID This register uniquely identifies this LSI amongst PCI devices manufactured by the vendor 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14...

Page 528: ...to 10 All 0 SH R PCI R Reserved These bits are always read as 0 The write value should always be 0 9 FBBE 0 SH R PCI R PCI Fast Back to Back Enable Controls whether or not a master can do fast back to back transactions to different device 0 Fast back to back transactions are only allowed to the same target 1 Master is allowed to generate fast back to back transactions to different targets not supp...

Page 529: ... invalidate command is executable not supported 3 SC 0 SH R PCI R PCI Special Cycles Indicates whether or not to support the special cycle operations in a target access 0 Special cycles ignored 1 Special cycles monitored not supported 2 BM 0 SH R W PCI R W PCI Bus Master Control Controls a bus master 0 Bus master function disabled 1 Bus master function enabled 1 MS 0 SH R W PCI R W PCI Memory Spac...

Page 530: ...For instance to clear bit 14 and not affect any other bits write the value of B 0100 0000 0000 0000 to the register 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 CL 66C FBBC MDPE DEVSEL STA RTA RMA DPE SSE 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 R R R R R R W R W R R WC R R R WC R WC R WC R WC R WC Bit Initial value SH R W R R R R R R R R R WC R R R WC R WC R WC R WC R WC PCI R W Bit Bit Name Initial Value R W De...

Page 531: ...been terminated with a target abort 11 STA 0 SH R WC PCI R WC Target Abort Execution Status Indicates that the PCIC has terminated a transaction with a target abort when the PCIC functions as a target 0 PCIC has not terminated a transaction with a target abort 1 PCIC has terminated a transaction with target abort 10 9 DEVSEL 01 SH R PCI R DEVSEL Timing Status Indicate the response timing status of...

Page 532: ...ed 1 Fast back to back transactions to different agents supported 6 0 SH R W PCI R Reserved These bits are always read as 0 The write value should always be 0 5 66C 0 SH R W PCI R 66MHz Operation Capable Status Indicates whether or not the PCIC is capable of running at 66MHz 0 PCIC runs at 33 MHz 1 PCIC runs at 66 MHz 4 CL 1 SH R PCI R PCI Power Management Optional Function Indicates whether or no...

Page 533: ...CIC and it may be changed in the future 6 PCI Program Interface Register PCIPIF This register is the programming interface for the IDE controller class code For details of the class code refer to PCI Local Bus Specification Revision 2 2 Appendix D R R R R R R R R PCI R W 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 OMP PIP OMS PIS MIDED R W R W R W R W R R R R W Bit Initial value SH R W Bit Bit Name Initial Va...

Page 534: ...writing is ignored This bit is readable 2 OMS 0 SH R W PCI R PCI Operating Mode Secondary When the CFINIT bit in PCICR is 0 this bit is writable When the CFINIT bit in PCICR is 1 writing is ignored This bit is readable 1 PIP 0 SH R W PCI R PCI Programmable Indicator Primary When the CFINIT bit in CR is 0 this bit is writable When the CFINIT bit in PCICR is 1 writing is ignored This bit is readable...

Page 535: ...Bit Bit Name Initial Value R W Description 7 to 0 SUB H 00 SH R W PCI R Sub Class Code Indicate the sub class code The initial value is H 00 8 PCI Base Class Code Register PCIBCC This register identifies the base class code For details of the class code refer to PCI Local Bus Specification Revision 2 2 Appendix D 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 BCC R W R W R W R W R W R W R W R W Bit Initial value...

Page 536: ...mory target does not support a cache SDON and SBO are ignored 10 PCI Latency Timer Register PCILTM This register specifies in units of PCI bus clocks the value of latency timer for this PCI bus master 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 LTM R W R W R W R W R W R W R W R W Bit Initial value SH R W R W R W R W R W R W R W R W R W PCI R W Bit Bit Name Initial Value R W Description 7 to 0 LTM H 00 SH R W ...

Page 537: ...to 0 HDR H 00 SH R PCI R Configuration Layout Indicates the layout type of configuration registers H 00 Type 00h layout supported H 01 Type 01h layout supported not supported 12 PCI BIST Register PCIBIST R R R R R R R R PCI R W 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 BISTC R R R R R R R R Bit Initial value SH R W Bit Bit Name Initial Value R W Description 7 BISTC 0 SH R PCI R This bit is used to control t...

Page 538: ...OB upper 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value SH R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W PCI R W Bit Bit Name Initial Value R W Description 31 to 8 IOB upper H 000000 SH R W PCI R W I O Space Base Address upper 24 bits Specifies the upper 24 bits of I O base address that corresponds the PCIC lo...

Page 539: ...W R W R W R W R W R W R W R W R W Bit Initial value SH R W R R R R R W R W R W R W R W R W R W R W R W R W R W R W PCI R W Bit Bit Name Initial Value R W Description 31 to 20 MBA upper H 000 SH R W PCI R W Memory Space 0 Base Address upper 12 bits Specifies the upper 12 bits of memory base address that corresponds the local address space 0 SuperHyway bus address space of this LSI Update value PCIL...

Page 540: ...e 1 I O space 15 PCI Memory Base Address Register 1 PCIMBAR1 This register packages the memory space base address register of the PCI configuration register that is prescribed with PCI local bus specification Refer to Section 13 4 4 1 Accessing This LSI Address Space 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 ASI LAT LAP MBA lower 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Bit Init...

Page 541: ... 1111 1111 256 Mbytes 31 28 1 1111 1111 512 Mbytes 31 29 19 to 4 MBA lower H 0000 SH R PCI R Memory Space 1 Base Address lower 16 bits These bits are fixed H 0000 by hardware 3 LAP 0 SH R PCI R Prefetch Control Indicates whether or not local address space 1 is prefetchable 0 Not prefetchable 1 Prefetchable Not supported 2 1 LAT 00 SH R PCI R Memory Type Indicates the memory type of local address s...

Page 542: ...fied during initializing PCIC registers PCICR CFINIT 0 but cannot be modified after initialized PCIC register PCICR CFINIT 1 even if writing this field 17 PCI Subsystem ID Register PCISID Refer to section about miscellaneous registers of PCI local bus specification Revision 2 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 SSID 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R ...

Page 543: ...Description 7 to 0 CP H 40 SH R PCI R Capabilities pointer The offset address of the expansion function register 19 PCI Interrupt Line Register PCIINTLINE 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 INTLINE R W R W R W R W R W R W R W R W Bit Initial value SH R W R W R W R W R W R W R W R W R W PCI R W Bit Bit Name Initial Value R W Description 7 to 0 INTLINE H 00 SH R W PCI R W PCI Interrupt Line PCI interru...

Page 544: ...n the PCIC outputs interrupt request H 00 Does not connect INTD to INTA H 01 INTA is used to request an interrupt H 02 INTB is used to request an interrupt H 03 INTC is used to request an interrupt H 04 INTD is used to request an interrupt H 05 to H FF Reserved 21 PCI Minimum Grant Register PCIMINGNT This register is not programmable 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 MINGNT R R R R R R R R Bit Initi...

Page 545: ...ter device to the bus acquisition not supported 23 PCI Capability Identifier Register PCICID When H 01 is read by system software it indicates that the data structure currently being pointed to is the PCI power management data structure Each function of a PCI device may have only one item in its capability list with PCICID set to H 01 0 1 2 3 4 5 6 7 1 0 0 0 0 0 0 0 CID R R R R R R R R Bit Initial...

Page 546: ...n of the next item in the function s capability list 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 NIP R R R R R R R R Bit Initial value SH R W R R R R R R R R PCI R W Bit Bit Name Initial Value R W Description 7 to 0 NIP H 00 SH R PCI R Next Item Pointer Specifies the offset to the next expansion function H 00 Power management function is listed as the last item ...

Page 547: ...it Name Initial Value R W Description 15 to 11 PMCS 00000 SH R PCI R PME_SUPPORT This 5 bit field indicates the power states in which the function may assert PME A value of 0b for any bit indicates that the function is not capable of asserting the PME signal while in that power state Bit11 xxxx1 PME can be asserted from D0 Bit12 xxx1x PME can be asserted from D1 Bit13 xx1xx PME can be asserted fro...

Page 548: ...ation 0 Does not require the specific initialization 4 0 SH R PCI R Reserved These bits are always read as 0 The write value should always be 0 3 PMEC 1 SH R W PCI R PCI PME clock Specifies whether or not the device requires the clock to support PME generation 1 Requires the clock to support PME generation Note This LSI dose not have the PME pin 2 to 0 PMV 010 SH R W PCI R Version Specifies the ve...

Page 549: ...on 15 PMES 0 SH R PCI R PME Status Indicates the state of the PME signal Not supported Note This LSI dose not have the PME pin 14 13 DSC 00 SH R PCI R Data Scale Specify the scaling of data field Not supported 12 to 9 DSL 0000 SH R PCI R Data Select Specify the data output in the data filed 8 PMEEN 0 SH R PCI R PME Enable Controls the PME output Not supported Note This LSI dose not have the PME pi...

Page 550: ...the power state bits in bridge s PCIPMCSR cannot be used by the system software to control the power or clock of the bridge s secondary bus 6 B2B3N 0 SH R PCI R The state of this bit determines the action that is to occur as a direct result of programming the function to the D3 hot state 0 Indicates that when the bridge function is set to the D3 hot state its secondary bus will have its power remo...

Page 551: ...pation For details refer to PCI Bus Power Management Interface Specification Revision 1 1 Chapter 3 PCI Power Management Interface 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 PCDD R W R W R W R W R W R W R W R W Bit Initial value SH R W R R R R R R R R PCI R W Bit Bit Name Initial Value R W Description 7 to 0 PCDD H 00 SH R W PCI R This register is used to report the state dependent data requested by the PCIP...

Page 552: ... 0 0 0 0 0 0 0 Bit Initial value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 RST CTL CFI NIT IOCS R 0 BMAM TBS PFE FTO PFCS Bit Initial value Bit Bit Name Initial Value R W Description 31 to 24 H 00 SH R W PCI R Reserved Set these bits to H A5 only when writing to bits 11 to 8 6 and 3 to 0 These bits are always read as 0 23 to 12 All 0 SH R PCI R Reserved These bits are always ...

Page 553: ...I bus arbitration mode when the PCIC operates in host bus bridge mode This bit is ignored when the PCIC operates in normal mode 0 Fixed mode PCIC device0 device1 device2 device3 1 Pseudo round robin the most recently granted device is assigned the lowest priority 5 4 Undefined SH R PCI R Reserved These bits are always read as an undefined value The write value should always be 0 3 0 SH R PCI R Res...

Page 554: ... are completed Setting this bit enables accesses from the PCI bus During initialization in host bus bridge mode the bus is not given to the device on the PCI bus In normal mode the PCIC returns RETRY when it is accessed from the PCI bus 0 During initialization 1 Initialization completed 2 PCI Local Space Register 0 PCILSR0 Refer to Section 13 4 4 1 Accessing This LSI Address Space SH R W PCI R W R...

Page 555: ... in these bits must be the size minus 1 Mbytes Setting all the bits to 0 ensures 1 Mbyte space 0 0000 0000 1 Mbyte 0 0000 0001 2 Mbytes 0 0000 0011 4 Mbytes 0 0000 0111 8 Mbytes 0 0000 1111 16 Mbytes 0 0001 1111 32 Mbytes 0 0011 1111 64 Mbytes 0 0111 1111 128 Mbytes 0 1111 1111 256 Mbytes 1 1111 1111 512 Mbytes Other than above Setting prohibited 19 to 1 All 0 SH R PCI R Reserved These bits are al...

Page 556: ...Initial Value R W Description 31 to 29 All 0 SH R PCI R Reserved These bits are always read as 0 The write value should always be 0 28 to 20 LSR 0 0000 0000 SH R W PCI R Size of Local Address Space 1 9 bits Specify the size of local address space 1 SuperHyway bus address space of this LSI in units of Mbyte The value set in these bits must be the size minus 1 Mbytes Setting all the bits to 0 ensure...

Page 557: ... R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 20 LAR H 000 SH R W PCI R Local Address 12 bits Specify bits 31 to 20 of the start address in local address space 0 The effective bits of LAR depend on the capacity of local address space 0 as specified...

Page 558: ...7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 20 LAR H 000 SH R W PCI R Local Address 12 bits Specify bits 31 to 20 of the start address in local address space 1 The effective bits of LAR depend on the capacity of local address space 1 as specified in PCILSR1 The effective bits are as follows PCILSR1 LS1 28 20 0 0000 0000 Effective bits are 31 20 PCILSR...

Page 559: ...DI APE DI MDEI TMT OI TTA DI R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 15 All 0 SH R PCI R Reserved These bits are always read as 0 The write value should always be 0 14 TTADI 0 SH R WC PCI R Target Target Abort Interrupt Indicates that the ...

Page 560: ...of memory read operations 0 Target memory read retry timeout interrupt does not occur Clear condition Write 1 to this bit write clear 1 Target memory read retry timeout interrupt occurs Set condition When a target memory read retry timeout interrupt occurs 8 MDEI 0 SH R WC PCI R Master Function Disable Error Interrupt The PCIC attempted a master access when such accesses are disabled that is when ...

Page 561: ...6 SEDI 0 SH R WC PCI R SERR Detection Interrupt Indicates that the assertion of the SERR signal has been detected when the PCIC operates in host bus bridge mode 0 SERR detection interrupt does not occur Clear condition Write 1 to this bit write clear 1 SERR detection interrupt occurs Set condition When a SERR detection interrupt occurs 5 DPEITW 0 SH R WC PCI R Data Parity Error Interrupt for Targe...

Page 562: ...tection interrupt occurs 3 TADIM 0 SH R WC PCI R Target Abort Detection Interrupt for Master When the PCIC functions as a master it has detected a target abort that is the transaction is terminated 0 Target abort interrupt does not occur Clear condition Write 1 to this bit write clear 1 Target abort interrupt occurs Set condition When a target abort interrupt occurs 2 MADIM 0 SH R WC PCI R Master ...

Page 563: ...ur Clear condition Write 1 to this bit write clear 1 Master write PERR interrupt occurs Set condition When a master write PERR interrupt occurs 0 MRDPEI 0 SH R WC PCI R Master Read Data Parity Error Interrupt Indicates that a data parity error has been detected during a master read access only detected when PCICMD PER is set to 1 when the PCIC functions as a master 0 Master read data perity error ...

Page 564: ... 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 15 All 0 SH R PCI R Reserved These bits are always read as 0 The write value should always be 0 14 TTADIM 0 SH R W PCI R Target Target Abort Interrupt Mask 0 PCIIR TTADI disabled masked 1 PCIIR TTADI enabled not masked 13 to 10 All 0 SH R PCI R Reserved These bits are always read as 0 The write value should always b...

Page 565: ...ion Interrupt Mask for Target Read 0 PCIIR PEDITR disabled masked 1 PCIIR PEDITR enabled not masked 3 TADIMM 0 SH R W PCI R Target Abort Interrupt Mask for Master 0 PCIIR TADIM disabled masked 1 PCIIR TADIM enabled not masked 2 MADIMM 0 SH R W PCI R Master Abort Interrupt Mask for Master 0 PCIIR MADIM disabled masked 1 PCIIR MADIM enabled not masked 1 MWPDIM 0 SH R W PCI R Master Write Data Parity...

Page 566: ... 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit Initial value R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R AIL R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R AIL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 0 AIL Undefined SH R PCI R Address Information Log This register holds address information the sta...

Page 567: ... 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 MTEM Undefined SH R PCI R Master Error Indicates that an error has occurred during a master access 0 Master error does not occur 1 Master error occurs 30 to 27 All 0 SH R PCI R Reserved These bits are always read as 0 The write value should always be 0 26 RWTET Undefined SH R PCI R Target Error Indicates that an error has oc...

Page 568: ...R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R WC R WC R WC R WC R R R R R R R R WC R WC R WC R R R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WD PEI RD PEI MAI TAI MB TOI TB TOI MBI 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 14 All 0 SH R PCI R Reserved These bits are always read as 0 The write value should always be 0 13 M...

Page 569: ... to the 2nd 0 Target bus time out interrupt does not occur Clear condition Write 1 to this bit write clear 1 Target bus time out interrupt occurs Set condition When a target bus time out interrupt occurs 11 MBTOI 0 SH R WC PCI R Master Bus Time Out Interrupt An interrupt is detected when the IRDY signal is not asserted within 8 clock cycles 0 Master bus time out interrupt does not occur Clear cond...

Page 570: ...Master Abort Interrupt Indicates that a transaction is terminated with a master abort when a device other than the PCIC functions as a bus master 0 Master abort interrupt does not occur Clear condition Write 1 to this bit write clear 1 Master abort interrupt occurs Set condition When a master abort interrupt occurs 1 RDPEI 0 SH R WC PCI R Read Parity Error Interrupt The PERR assertion is detected ...

Page 571: ...s detected by the PERR assertion 11 PCI Arbiter Interrupt Mask Register PCIAINTM This register is the mask register for PCIAINT SH R W PCI R W SH R W PCI R W 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit Initial value R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R R R R R R R R W R W R W R R R R R R R R R R R R R R R R R R 0 ...

Page 572: ...BTOI disabled masked 1 PCIAINT MBTOI enabled not masked 10 to 4 All 0 SH R PCI R Reserved These bits are always read as 0 The write value should always be 0 3 TAIM 0 SH R WC PCI R Target Abort Interrupt Mask 0 PCIAINT TAI disabled masked 1 PCIAINT TAI enabled not masked 2 MAIM 0 SH R WC PCI R Master Abort Interrupt Mask 0 PCIAINT MAI disabled masked 1 PCIAINT MAI enabled not masked 1 RDPEIM 0 SH R...

Page 573: ... R R R R R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 REQ0 BME REQ1 BME REQ2 BME REQ3 BME REQ4 BME 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 5 All 0 SH R PCI R Reserved These bits are always read as 0 The write value should always be 0 4 REQ4BME Undefined SH R PCI R REQ4 Error An error occurs when the PCIC functions as a bus m...

Page 574: ... R W R W R W R W R W R W R W R W R W R W R W 0 0 CRA FN DN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 CCIE 1 SH R PCI Configuration Cycle Issue Enable Enables a configuration cycle to be issued 1 Indicates the configuration cycle generation enable 30 to 24 All 0 SH R PCI Reserved These bits are always read as 0 The write value should alway...

Page 575: ...iven to low level Device No IDSEL Device No IDSEL H 0 AD 16 high level H 8 AD 24 high level H 1 AD 17 high level H 9 AD 25 high level H 2 AD 18 high level H A AD 26 high level H 3 AD 19 high level H B AD 27 high level H 4 AD 20 high level H C AD 28 high level H 5 AD 21 high level H D AD 29 high level H 6 AD 22 high level H E AD 30 high level H 7 AD 23 high level H F AD 31 high level Other than abo...

Page 576: ...ays read as 0 The write value should always be 0 3 PMD3H 0 SH R WC PCI PCI Power Management D3 Hot Status Transition Interrupt 0 Interrupt request for a transition to D3 is not detected 1 Interrupt request for a transition to D3 is detected 2 PMD2 0 SH R WC PCI PCI Power Management D2 Status Transition Interrupt 0 Interrupt request for a transition to D2 is not detected 1 Interrupt request for a t...

Page 577: ... Initial Value R W Description 31 to 4 All 0 SH R PCI Reserved These bits are always read as 0 The write value should always be 0 3 PMD3HM 0 SH R W PCI PCI Power Management D3 Hot Status Transition Interrupt Mask 0 PCIPINT PM D3H disabled masked 1 PCIPINT PM D3H enabled not masked 2 PMD2M 0 SH R W PCI PCI Power Management D2 Status Transition Interrupt Mask 0 PCIPINT PMD2 disabled masked 1 PCIPINT...

Page 578: ...25 26 27 28 29 31 30 Bit Initial value R R R W R W R R R R R W R W R W R W R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PMSBA0 R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 18 PMSBA0 H 0000 SH R W PCI PCI Memory Space 0 Bank Address Specify the bank address in PCI m...

Page 579: ...R R R R R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSBAM0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 24 All 0 SH R PCI Reserved These bits are always read as 0 The write value should always be 0 23 to 18 MSBAM0 000000 SH R W PCI PCI Memory Space 0 Bank Address Mask 0000 00 256 Kbytes 0000 01 512 Kbytes 0000 11 1 Mby...

Page 580: ...25 26 27 28 29 31 30 Bit Initial value R R R W R W R R R R R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PMSBA1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 18 PMSBA1 All 0 SH R W PCI PCI Memory Space 1 Bank Address Specify the bank address in PCI me...

Page 581: ...R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSBAM1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 26 All 0 SH R PCI Reserved These bits are always read as 0 The write value should always be 0 25 to 18 MSBAM1 All 0 SH R W PCI PCI Memory Space 1 Bank Address Mask 8 bits 00 0000 00 256 Kbytes 00 0000 01 512 Kbytes 00 0000 11 1 Mbyte 00 0001 11 2 M...

Page 582: ...25 26 27 28 29 31 30 Bit Initial value R R R W R W R R R R R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PMSBA2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 18 PMSBA2 All 0 SH R W PCI PCI Memory Space 2 Bank Address Specify the bank address in PCI me...

Page 583: ...2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 29 All 0 SH R PCI Reserved These bits are always read as 0 The write value should always be 0 28 to 18 MSBAM2 All 0 SH R W PCI PCI Memory Space 2 Bank Address Mask 0 0000 0000 00 256 Kbytes 0 0000 0000 01 512 Kbytes 0 0000 0000 11 1 Mbyte 0 0000 0001 11 2 Mbytes 0 0000 0011 11 4 Mbytes 0 0000 0111 ...

Page 584: ... 27 28 29 31 30 Bit Initial value R R R W R W R R R R R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIOSBA 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 18 PIOSBA All 0 SH R W PCI PCI I O Space Bank Address 14 bits Specify the bank address in PCI I O ...

Page 585: ...0 0 R R R R R R R R R R R R R R R W R W R W R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOBAMR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 21 All 0 SH R PCI Reserved These bits are always read as 0 The write value should always be 0 20 to 18 IOBAMR All 0 SH R W PCI PCI I O Space Bank Address Mask 3 bits 000 256 Kbytes 001 512 K...

Page 586: ...MD RANGE R W R R R R R R R R R R R R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 5 All 0 SH R PCI Reserved These bits are always read as 0 The write value should always be 0 4 to 2 RANGE All 0 SH R W PCI Address Range to be Compared Specify the address range of PCICSAR0 to be ...

Page 587: ...r PCICSAR0 Specify if PCICSAR0 is compared with address requested by an external device Also specify how snoop function is executed when PCICSAR0 is compared 00 PCICSAR0 not compared 01 Reserved setting prohibited 10 PCICSAR0 compared If hit snoop function is not executed otherwise executed 11 PCICSAR0 compared If hit snoop function is executed otherwise not executed ...

Page 588: ...MD RANGE R W R R R R R R R R R R R R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 5 All 0 SH R PCI Reserved These bits are always read as 0 The write value should always be 0 4 to 2 RANGE All 0 SH R W PCI Address Range to be Compared Specify the address range of PCICSAR1 to be ...

Page 589: ...r PCICSAR1 Specify if PCICSAR1 is compared with address requested by an external device Also specify how snoop function is executed when PCICSAR1 is compared 00 PCICSAR1 not compared 01 Reserved setting prohibited 10 PCICSAR1 compared If hit snoop function is not executed otherwise executed 11 PCICSAR1 compared If hit snoop function is executed otherwise not executed ...

Page 590: ...16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W CADR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W CADR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 0 CADR All 0 SH R W PCI Add...

Page 591: ...16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W CADR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W CADR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 0 CADR All 0 SH R W PCI Add...

Page 592: ...Configuration Space Access SH R W PCI R W SH R W PCI R W 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit Initial value PDR PDR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R Bit Bit Name Initial Value R W Description 31 to 0 PDR Undefined SH R W PCI PCI PIO Data Register A read from or write to this register will cause a ...

Page 593: ...emory read Yes Yes 0111 Memory write Yes Yes 1000 Reserved 1001 Reserved 1010 Configuration read Yes 1 Yes 2 1011 Configuration write Yes 1 Yes 2 1100 Memory read multiple No Partially yes 3 1101 Dual address cycle No No 1110 Memory read line No Partially yes 3 1111 Memory write and invalidate No Partially yes 4 Legend 0 Low level 1 High level Notes 1 Only the host bus bridge mode is supported 2 S...

Page 594: ... will read 0 none of the registers can be modified and any access to the PCI bus will not be executed To initialize the PCIC first setting the enable bit in the PCIECR to 1 The PCIC s internal configuration registers and local registers must be initialized before setting the CFINIT bit in the PCICR to 1 while the CFINIT bit is cleared to 0 On completion of initialization set the CFINIT bit to 1 Wh...

Page 595: ...nded mode H C000 0000 to H DFFF FFFF 512 Mbytes PCI memory space 0 H FD00 0000 to H FDFF FFFF H FD00 0000 to H FDFF FFFF 16 Mbytes Control register H FE00 0000 to H FE03 FFFF H FE00 0000 to H FE03 FFFF 256 Kbytes PCIC internal register configuration and local registers H FE04 0000 to H FE07 FFFF H FE04 0000 to H FE07 FFFF 256 Kbytes Reserved H FE08 0000 to H FE1F FFFF H FE08 0000 to H FE1F FFFF 1 ...

Page 596: ...PCIMBR and PCI memory bank mask register PCIMBMR These registers should have an address space ranging from 16 Mbytes to 512 Mbytes PCI addresses can be allocated to by software The PCIC supports burst transfers to memory transfer Consecutive accesses with the SuperHyway load 32 byte or SuperHyway store 32 byte command result in a burst transfer of 32 byte or more 64 byte 96 byte etc The PCI memory...

Page 597: ...uperHyway bus address are replaced with bits 31 to 24 in PCI memory bank register 0 PCIMBR0 31 31 24 23 18 17 0 0 24 23 18 17 PCIMBMR0 mask SH address MSBAM0 31 24 23 18 17 0 31 24 23 18 17 0 PCIMBR0 PCI address PMSBA0 Figure 13 3 SuperHyway Bus to PCI Local Bus Address Translation PCI Memory Space 0 For PCI memory space 1 accesses bits 25 to 18 of a SuperHyway address are controlled by PCI memory...

Page 598: ...MR2 PCIMBMR2 28 18 B 1 1111 1111 11 PCI address 28 18 SH address 28 18 PCIMBMR2 28 18 B 0 1111 1111 11 PCI address 28 18 PCIMBR2 28 SH address 27 18 PCIMBMR2 28 18 B 0 0000 0000 01 PCI address 28 18 PCIMBR2 28 19 SH address 18 PCIMBMR2 28 18 B 0 0000 0000 00 PCI address 28 18 PCIMBR2 28 18 The upper three bits 31 29 of a SuperHyway bus address are replaced with bits 31 to 29 in PCI memory bank reg...

Page 599: ... PCIIOBMR Note In the following item and figure SH means the SuperHyway bus of this LSI and PCI means the PCI local bus PCIIOMR0 20 18 B 111 PCI address 20 18 SH address 20 18 PCIIOMR0 20 18 B 011 PCI address 20 18 PCIIOBR 20 SH address 19 18 PCIIOMR0 20 18 B 001 PCI address 20 18 PCIIOBR 20 19 SH address 18 PCIIOMR0 20 18 B 000 PCI address 20 18 PCIIOBR 20 18 The upper 11 bits 31 21 of a SuperHyw...

Page 600: ...pported 5 Endian The PCIC of this LSI supports both the big endian and little endian formats Since PCI local bus is inherently little endian the PCIC supports both byte swapping and non byte swapping The endian format is specified by the setting of the TBS bit in the PCI control register PCICR at a reset Note In the following figures SH means the SuperHyway bus of this LSI and PCI means the PCI lo...

Page 601: ...D Buffer data A B C D A B C D A B C D PCI Address 2 1 PCI Address 2 0 MSByte 31 0 LSByte MSByte LSByte SH data PCI data Note PCI Address 2 AD 2 address 2 Big Endian A B C D A B C D Buffer data A B C D A B C D A B C D PCI Address 2 0 PCI Address 2 1 Figure 13 7 Endian Conversion from SuperHyway Bus to PCI Local bus Non Byte Swapping TBS 0 ...

Page 602: ...ddress 2 1 PCI Address 2 0 MSByte 31 0 LSByte MSByte LSByte D C B A D C B A A B C D A B C D A B C D PCI Address 2 1 PCI Address 2 0 SH data PCI data 1 Little Endian Buffer data SH data PCI data 2 Big Endian Buffer data Note PCI Address 2 AD 2 address Figure 13 8 Endian Conversion from SuperHyway Bus to PCI Local bus Byte Swapping TBS 1 ...

Page 603: ... modes 1 Accessing This LSI Address Space Accesses to the address space of this LSI by an external PCI bus master are described here H 0000 0000 Memory base 0 Local address space 0 base 0 Local address space 1 base 1 I O space 4 Mbytes Memory base 1 I O base 1 PCI I O space PCI local bus address space 4 Gbytes SuperHyway bus address space 4 Gbytes H FFFF FFFF H 0000 0000 H FFFF FFFF H FE00 0000 H ...

Page 604: ...pace used by the PCI device The PCILAR0 1 specifies the starting address of the local address space 0 1 The PCILSR0 1 expresses the size of the memory used by the PCI device Address translation from PCI local bus to SuperHyway bus For the PCIMBAR0 1 and PCILAR0 1 the more significant address bits that are higher than the memory size set in the PCILSR0 1 becomes valid The more significant address b...

Page 605: ... to the SuperHyway bus without translation Data prefetching for memory read commands is supported When a PCI burst read is performed 8 bytes or 32 bytes of data block is prefetched this depends on the settings of the PFE and PFCS bits in PCICR 2 Accessing PCIC I O Space Allocate a 256 byte area to the I O address space Address translation from PCI local bus to SuperHyway bus The lower 8 bits 7 0 a...

Page 606: ...rminated to end the transaction Local Registers Access the local registers using an offset from a PCI local register space base address with the I O read or I O write command Only a single longword access is performed If a burst transfer is attempted it is terminated to end the transaction Control Register PCIECR Do not read or write access to the PCIECR from the PCI local bus 4 Access to this LSI...

Page 607: ...ce lock does not occur Another on chip module can access the PCIC during a lock transfer 6 Endian This LSI supports both the big and little endian formats Since the PCI local bus is inherently little endian the PCIC supports both byte swapping and non byte swapping The endian format is specified by the setting of the TBS bit in the PCI control register PCICR Note In the following figures MSByte me...

Page 608: ...ittle Endian A B C D A B C D Buffer data A B C D A B C D A B C D PCI Address 2 1 PCI Address 2 0 31 0 PCI data SH data A B C D A B C D Buffer data A B C D A B C D A B C D PCI Address 2 0 PCI Address 2 1 2 Big Endian Note PCI Address 2 AD 2 address Figure 13 12 Endian Conversion from PCI Local Bus to SuperHyway bus Non Byte Swapping TBS 0 ...

Page 609: ...C D D B C D A B C D PCI Address 2 1 PCI Address 2 0 31 0 D C B A D C B A D C B A D C B A A B C D PCI Address 2 0 PCI Address 2 1 PCI data SH data 1 Little Endian Buffer data PCI data SH data Buffer data 2 Big Endian Note PCI Address 2 AD 2 address Figure 13 13 Endian Conversion from PCI Local Bus to SuperHyway bus Non Byte Swapping TBS 1 ...

Page 610: ...xecute memory read or write after flush purge request issued to the CPU cache in the access of cache hit It reduces PCI bus transfer speed and CPU performance When using this function do not use the prefetch function Do not set PFE bit in the PCICR to 1 Do not use this function when the CPU is sleep state If cache hit occurs in sleep state it becomes an error access on the SuperHyway bus and memor...

Page 611: ...EJ09B0256 0100 PCI address SuperHyway address Cache snoop address register Cache snoop control register Set issue the flush purge issue the read write Issue the read write compare Hit No hit Figure 13 14 Cache Flush Purge Execution Flow for PCI local Bus to SuperHyway Bus ...

Page 612: ... outputs to external masters 0 to 3 Including the PCIC arbitration of up to five masters is possible 2 Configuration Space Access The PCIC supports configuration mechanism 1 The PCI PIO address register PCIPAR and PCI PIO data register PCIPDR correspond to the configuration address register and configuration data register respectively When PCIPDR is read from or written to after PCIPAR has been se...

Page 613: ...to the PCIPDR 4 Arbitration In host bus bridge mode the PCI bus arbiter in the PCIC is activated The PCIC supports four external masters i e four REQ and GNT pairs If use of the bus is simultaneously requested by more than one device the bus is granted to the device with the highest priority The PCI bus arbiter supports two modes to determine the priority of devices fixed priority and pseudo round...

Page 614: ...the PCIC operates normal mode INTA output is available to the host device on the PCI bus The INTA pin is specified assert or negate by the IOCS bit in the PCICR Table 13 6 Interrupt Priority Signal Interrupt Source Priority PCISERR SERR assertion detected in host bus bridge mode High PCIINTA PCI interrupt A INTA detected in host bus bridge mode PCIINTB PCI interrupt B INTB detected in host bus bri...

Page 615: ...ter that performing bus parking is different from the next transaction master the bus will be high impedance state for minimum one clock cycle before the address phase In normal mode the GNT0 GNTIN pin is used for the grant input signal to the PCIC and the REQ0 REQOUT pin is used for the request output signal from the PCIC 13 4 7 Power Management The PCIC supports PCI power management revision 1 1...

Page 616: ... detects a transition from the power state D0 D1 D2 to D3 Interrupt masks can be set for each interrupt No power state D0 interrupt is generated at a power on reset The following cautions should be noted when the PCIC is operating in normal mode and a power down interrupt is received from the host In PCI power management the PCI local bus clock stops within a minimum of 16 clocks after the host de...

Page 617: ... burst read cycle in normal mode Note that the response speed of DEVSEL and TRDY differs according to the connected target device In host bus bridge mode master accesses always use single read write cycles The issuing of configuration transfers is only possible in host bus bridge mode PCICLK AD 31 0 PAR CBE 3 0 C BE 3 0 PCIFRAME IRDY DEVSEL TRDY LOCK IDSEL REQ GNT Legend Addr AP Com Dn DPn BEn PCI...

Page 618: ...0 PCICLK AD 31 0 PAR PCIFRAME IRDY DEVSEL TRDY LOCK IDSEL REQ GNT D0 DP0 Addr AP BE0 Com CBE 3 0 C BE 3 0 Legend Addr AP Com Dn DPn BEn PCI space address Address parity Command nth data nth data parity nth data byte enable Figure 13 18 Master Read Cycle in Host Bus Bridge Mode Single ...

Page 619: ...K AD 31 0 PAR PCIFRAME IRDY DEVSEL TRDY LOCK IDSEL REQ GNT AP Com Addr D0 D1 Dn BE0 BE1 BEn DP0 DPn DPn 1 CBE 3 0 C BE 3 0 Legend Addr AP Com Dn DPn BEn PCI space address Address parity Command nth data nth data parity nth data byte enable Figure 13 19 Master Write Cycle in Normal Mode Burst ...

Page 620: ...K AD 31 0 PAR PCIFRAME IRDY DEVSEL TRDY LOCK IDSEL REQ GNT AP Com Addr D0 D1 Dn BE0 BE1 BEn DP0 DPn DPn 1 CBE 3 0 C BE 3 0 Legend Addr AP Com Dn DPn BEn PCI space address Address parity Command nth data nth data parity nth data byte enable Figure 13 20 Master Read Cycle in Normal Mode Burst ...

Page 621: ...is completely written to the local memory if reading the target write data immediately after write access Only single transfers are supported in the case of target accesses of the configuration space and I O space If there is a burst access request the external master is disconnected on completion of the first transfer Note that the DEVSEL response speed is fixed at 2 clocks Medium in the case of ...

Page 622: ...PCIFRAME IRDY DEVSEL TRDY STOP LOCK IDSEL REQOUT GNTIN Addr AP D0 DP0 Com Locked At configuration access Disconnect BE0 CBE 3 0 C BE 3 0 Legend Addr AP Com Dn DPn BEn PCI space address Address parity Command nth data nth data parity nth data byte enable Figure 13 21 Target Read Cycle in Normal Mode Single ...

Page 623: ...CIFRAME IRDY DEVSEL TRDY STOP LOCK IDSEL REQOUT GNTIN Addr AP D0 DP0 Com BE0 CBE 3 0 C BE 3 0 Legend Addr AP Com Dn DPn BEn PCI space address Address parity Command nth data nth data parity nth data byte enable Locked At configuration access Disconnect Figure 13 22 Target Write Cycle in Normal Mode Single ...

Page 624: ...AME IRDY DEVSEL TRDY STOP LOCK IDSEL REQ GNT Addr AP D0 DP0 Com BE0 D1 Dn BEn DPn DPn 1 BE1 CBE 3 0 C BE 3 0 Legend Addr AP Com Dn DPn BEn PCI space address Address parity Command nth data nth data parity nth data byte enable Locked Disconnect Figure 13 23 Target Memory Read Cycle in Host Bus Bridge Mode Burst ...

Page 625: ...ME IRDY DEVSEL TRDY STOP LOCK IDSEL REQ GNT Addr AP D0 DP0 Com BE0 D1 Dn BEn DPn DPn 1 BE1 CBE 3 0 C BE 3 0 Legend Addr AP Com Dn DPn BEn PCI space address Address parity Command nth data nth data parity nth data byte enable Locked Disconnect Figure 13 24 Target Memory Write Cycle in Host Bus Bridge Mode Burst ...

Page 626: ...ed logic level in one clock When the PCIC operates as the host bus bridge mode it is recommended to use this function for the issuance of configuration transfers Figure 13 25 is an example of burst memory write cycle with stepping Figure 13 26 is an example of target burst read cycle with stepping PCICLK AD 31 0 PAR PCIFRAME IRDY DEVSEL TRDY Addr D0 Dn Com BE0 BEn AP DP0 DPn DPn 1 D1 BE1 CBE 3 0 C...

Page 627: ...31 0 PAR PCIFRAME IRDY DEVSEL TRDY Addr D1 D0 Com BE0 BEn AP Dn DPn DP0 DPn 1 BE1 CBE 3 0 C BE 3 0 Legend Addr AP Com Dn DPn BEn PCI space address Address parity Command nth data nth data parity nth data byte enable Figure 13 26 Target Memory Read Cycle in Host Bus Bridge Mode Burst with stepping ...

Page 628: ...ked thus disabling correct transfers via the PCI bus which leads to unstable operation of the PCI bus system 1 Host mode MD6 high 2 PCI bus master arbitration mode is set to fixed mode BMAM bit in PCICR 0 3 In addition to this LSI with the PCIC in host mode two or more external PCI devices that can be a bus master are connected to the PCI bus 4 Among the above external devices there is at least on...

Page 629: ...set BMAM bit in PCICR 1 as the PCI bus arbitration scheme 2 Assign the lowest priority level to the relevant device When there is only one device that does not execute REQ negation and FRAME assertion simultaneously the device should be connected to the REQn and GNTn with the lowest priority However if none of the external devices connected to the PCI has such negation assertion timing or if none ...

Page 630: ...Section 13 PCI Controller PCIC Rev 1 00 Oct 01 2007 Page 564 of 1956 REJ09B0256 0100 ...

Page 631: ...216 transfers Address mode Dual address mode Transfer requests External request channel 0 to 3 on chip peripheral module request channel 0 to 5 or auto request can be selected The following modules can issue an on chip peripheral module request CMT SCIF0 SCIF1 SCIF2 HAC USBF SSI0 to SSI3 MMCIF SIM SIOF0 to SIOF2 STIF0 and STIF1 Selectable bus modes Cycle steal mode normal mode and intermittent mod...

Page 632: ... 3 4 5 for channels 0 to 5 n 0 1 2 3 for channels 0 to 5 Note The half end interrupt request is available in channels 0 to 3 CHCRm DARBn DARm DMAE DMAOR DMA channel control register DMA destination address register B DMA destination address register DMA Address error interrupt request DMA operation register DMARS0 to DMARS2 DMINTm SARBn SARm TCRBn TCRm DMA extended resource selectors 0 to 2 DMA tr...

Page 633: ...ansfer request acknowledge Output Strobe output from channel 0 to external device which has output regarding DMA transfer request 0 TEND0 2 DMA transfer end notification Output DMA transfer end output from channel 0 to external device DREQ1 1 DMA transfer request Input DMA transfer request input from external device to channel 1 DACK1 2 DMA transfer request acknowledge Output Strobe output from ch...

Page 634: ...ding DMA transfer request 2 TEND2 2 DMA transfer end notification Output DMA transfer end output from channel 2 to external device DREQ3 1 DMA transfer request Input DMA transfer request input from external device to channel 3 DACK3 2 DMA transfer request acknowledge Output Strobe output from channel 3 to external device which has output regarding DMA transfer request 3 TEND3 2 DMA transfer end no...

Page 635: ... 2 SAR2 R W H FF60 8040 H 1F60 8040 32 DMA destination address register 2 DAR2 R W H FF60 8044 H 1F60 8044 32 DMA transfer count register 2 TCR2 R W H FF60 8048 H 1F60 8048 32 DMA channel control register 2 CHCR2 R W 1 H FF60 804C H 1F60 804C 32 3 DMA source address register 3 SAR3 R W H FF60 8050 H 1F60 8050 32 DMA destination address register 3 DAR3 R W H FF60 8054 H 1F60 8054 32 DMA transfer co...

Page 636: ...B2 R W H FF60 8140 H 1F60 8140 32 DMA destination address register B2 DARB2 R W H FF60 8144 H 1F60 8144 32 DMA transfer count register B2 TCRB2 R W H FF60 8148 H 1F60 8148 32 3 DMA source address register B3 SARB3 R W H FF60 8150 H 1F60 8150 32 DMA destination address register B3 DARB3 R W H FF60 8154 H 1F60 8154 32 DMA transfer count register B3 TCRB3 R W H FF60 8158 H 1F60 8158 32 0 1 DMA extend...

Page 637: ...d Undefined Retained Retained TCR2 Undefined Undefined Retained Retained CHCR2 H 4000 0000 H 4000 0000 Retained Retained 3 SAR3 Undefined Undefined Retained Retained DAR3 Undefined Undefined Retained Retained TCR3 Undefined Undefined Retained Retained CHCR3 H 4000 0000 H 4000 0000 Retained Retained 0 to 5 DMAOR H 0000 H 0000 Retained Retained 4 SAR4 Undefined Undefined Retained Retained DAR4 Undef...

Page 638: ...ARS1 H 0000 H 0000 Retained Retained 4 5 DMARS2 H 0000 H 0000 Retained Retained 14 3 1 DMA Source Address Registers SAR0 to SAR5 SAR is 32 bit readable writable registers that specify the source address of a DMA transfer During a DMA transfer these registers indicate the next source address To transfer data in word or in longword units specify the address with word or longword address boundary Whe...

Page 639: ...0 9 8 7 6 5 4 3 2 1 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W Bit Initial value R W SARB SARB 14 3 3 DMA Destination Address Registers DAR0 to DAR5 DAR is 32 bit readable writable registers that specify the destination address of a DMA transfer During a DMA transfer these registers indicat...

Page 640: ...6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W Bit Initial value R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W DARB DARB 14 3 5 DMA Transfer Count Registers TCR0 to TCR5 TCR is 32 bit readable writable registers that specify the DMA transfer count The number of transfers is 1 when the setting is H ...

Page 641: ...load mode the lower 16 bits operate as transfer count counters values of SAR and DAR are updated after the value of the lower 16 bits became 0 and then the value of the upper 16 bits of TCRB are loaded to the lower 16 bits In upper 16 bits set the number of transfers which starts reloading In reload mode the same number of transfers should be set in both upper and lower 16 bits Also set the HIE bi...

Page 642: ...l value R W LCKN RPT 2 0 DO TS 2 HE HIE AM AL DM 1 0 SM 1 0 RS 3 0 DL DS TB TS 1 0 IE TE DE DVMD Bit Bit Name Initial Value R W Descriptions 31 0 R Reserved This bit is always read as 0 The write value should always be 0 30 LCKN 1 R W Bus Lock Signal Disable Specifies whether enable or disable the bus lock signal output when a load instruction is output in dual transfer mode This bit is effective ...

Page 643: ... TCR used as reload area 111 Reload mode SAR TCR used as reload area 24 0 R Reserved This bit is always read as 0 The write value should always be 0 23 DO 0 R W DMA Overrun Selects whether DREQ is detected by overrun 0 or by overrun 1 This bit is valid only in CHCR0 to CHCR3 0 Detects DREQ by overrun 0 1 Detects DREQ by overrun 1 22 0 R Reserved This bit is always read as 0 The write value should ...

Page 644: ...transfer destination is a register of an on chip peripheral module with a transfer size set a proper transfer size for the register should be set For the transfer source or destination address specified by SAR or DAR an address boundary should be set according to the transfer data size TS 2 0 000 Byte units transfer 001 Word 2 byte units transfer 010 Longword 4 byte units transfer 011 16 byte unit...

Page 645: ...transfers is decreased to half of the TCR value set preceding the transfer The HE bit is kept set when the transfer ends by an NMI interrupt or address error or clearing the DE bit bit 0 or the DME bit in DMAOR after the HE bit is set to 1 To clear the HE bit write 0 after reading 1 in the HE bit This bit is valid only in CHCR0 to CHCR3 0 During the DMA transfer or DMA transfer has been interrupte...

Page 646: ...ctive This bit is valid only in CHCR0 to CHCR3 0 Low active output of DACK and TEND 1 High active output of DACK and TEND 15 14 DM 1 0 00 R W Destination Address Mode Specify whether the DMA destination address is incremented decremented or left fixed 00 Fixed destination address 01 Destination address is incremented 1 in byte units transfer 2 in word units transfer 4 in longword units transfer 16...

Page 647: ...ddress is decremented 1 in byte units transfer 2 in word units transfer 4 in longword units transfer Setting prohibited in 16 32 byte units transfer 11 Setting prohibited 11 to 8 RS 3 0 0000 R W Resource Select Specify which transfer requests will be sent to the DMAC The changing of transfer request source should be done in the state that the DMA enable bit DE is cleared to 0 0000 External request...

Page 648: ... detected at low level 01 DREQ detected at falling edge 10 DREQ detected at high level 11 DREQ detected at rising edge 5 TB 0 R W Transfer Bus Mode Specifies the bus mode when DMA transfers data 0 Cycle steal mode 1 Burst mode Burst mode cannot be used when the on chip peripheral module is the transfer request source 4 3 TS 1 0 00 R W DMA Transfer Size Specify See the description of TS 2 bit 20 2 ...

Page 649: ...ndition Writing 0 after TE 1 read 1 DMA transfer ends by the specified count TCR 0 0 DE 0 R W DMA Enable Enables or disables the DMA transfer In auto request mode DMA transfer starts by setting the DE bit and DME bit in DMAOR to 1 In this time all of the bits TE NMIF and AE in DMAOR must be 0 In an external request or peripheral module request DMA transfer starts if DMA transfer request is generat...

Page 650: ... Initial value R W Bit Bit Name Initial Value R W Descriptions 15 14 All 0 R Reserved These bits are always read as 0 The write value should always be 0 13 12 CMS 1 0 00 R W Cycle Steal Mode Select Select either normal mode or intermittent mode in cycle steal mode It is necessary that all channel bus modes are set to cycle steal mode to make valid intermittent mode 00 Normal mode 01 Setting prohib...

Page 651: ...ed These bits are always read as 0 The write value should always be 0 2 AE 0 R W Address Error Flag Indicates that an address error occurred during DMA transfer This bit is set under following conditions The value set in SAR or DAR does not match to the transfer size boundary The transfer source or transfer destination is invalid space The transfer source or transfer destination is in module stop ...

Page 652: ... is stopped when an NMI interrupt is input After returning from the NMI interrupt routine set all channels again and then start the DMA transfer 0 DME 0 R W DMA Master Enable Enables or disables DMA transfers on all channels If the DME bit and the DE bit in CHCR are set to 1 transfer is enabled In this time all of the bits TE in CHCR NMIF and AE in DMAOR must be 0 If this bit is cleared during tra...

Page 653: ...ranteed The transfer request from DMARS is valid only when the resource select bits RS 3 0 has been set to B 1000 for CHCR0 to CHCR5 registers Otherwise even if DMARS has been set transfer request source is not accepted DMARS0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W C1MID 5 0 C1RID 1...

Page 654: ...Transfer request module ID for DMA channel 2 MID See table 14 4 1 0 C2RID 1 0 00 R W R W Transfer request register ID for DMA channel 2 RID See table 14 4 DMARS2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W C5MID 5 0 C5RID 1 0 C4MID 5 0 C4RID 1 0 Bit Bit Name Initial Value R W Description...

Page 655: ...10 00 B 01 Transmit SCIF0 H 22 B 0010 00 B 10 Receive H 29 B 0010 10 B 01 Transmit SCIF1 H 2A B 0010 10 B 10 Receive H 41 B 0100 00 B 01 Transmit SCIF2 H 42 B 0100 00 B 10 Receive H 45 B 0100 01 B 01 Transmit HAC H 46 B 0100 01 B 10 Receive H 51 B 0101 00 B 01 Transmit USBF H 52 B 0101 00 B 10 Receive SSI0 H 73 B 0111 00 B 11 Transmit and Receive SSI1 H 77 B 0111 01 B 11 Transmit and Receive SSI2 ...

Page 656: ...lue for One Channel MID and RID MID RID Function H B1 B 1011 00 B 01 Transmit SIOF0 H B2 B 1011 00 B 10 Receive H B5 B 1011 01 B 01 Transmit SIOF1 H B6 B 1011 01 B 10 Receive H C1 B 1100 00 B 01 Transmit SIOF2 H C2 B 1100 00 B 10 Receive STIF0 H D3 B 1101 00 B 11 Transmit and Receive STIF1 H D7 B 1101 01 B 11 Transmit and Receive ...

Page 657: ...equest signal from an external source as in a memory to memory transfer or a transfer between memory and an on chip peripheral module unable to request a transfer auto request mode allows the DMAC to automatically generate a transfer request signal internally When the DE bits in CHCR0 to CHCR5 and the DME bit in DMAOR are set to 1 the transfer begins so long as the AE and NMIF bits in DMAOR are al...

Page 658: ...e same number of transfer has been performed as requests Overrun 1 Transfer is aborted after transfers have been performed for the number of requests plus 1 times The DO bit in CHCR selects this overrun 0 or overrun 1 Table 14 7 Selecting External Request Detection with DO Bit CHCR DO External Request 0 Overrun 0 initial value 1 Overrun 1 3 On Chip Peripheral Module Request Mode In this mode a tra...

Page 659: ...1 11 CMT channel 3 Compare match transfer request Any Any Cycle steal 000100 11 CMT channel 4 Compare match transfer request Any Any Cycle steal 01 SCI F0 transmitter TXI transmit FIFO data empty interrupt Any SCFTDR0 Cycle steal 001000 10 SCIF0 receiver RXI receive FIFO data full interrupt SCFRDR0 Any Cycle steal 01 SCI F1 transmitter TXI transmit FIFO data empty interrupt Any SCFTDR1 Cycle steal...

Page 660: ...t FIFO data write request Any DR Cycle steal 100100 11 MMCIF data part receive FIFO data read request DR Any Cycle steal 01 SIM transmitter TXT transmit data empty Any SCTDR Cycle steal 101000 10 SIM receiver RXI receive data full SCRDR Any Cycle steal 01 SIOF0 transmitter TXI transmit FIFO data empty Any SITDR0 Cycle steal 101100 10 SIOF0 receiver RXI receive data full SIRDR0 Any Cycle steal 1011...

Page 661: ...s of fixed modes as follows CH0 CH1 CH2 CH3 CH4 CH5 CH0 CH2 CH3 CH1 CH4 CH5 These are selected by the bits PR 1 0 in DMAOR 2 Round Robin Mode In round robin mode each time data of one transfer unit word byte longword 16 byte or 32 byte unit is transferred on one channel the priority is rotated The channel on which the transfer was just finished rotates to the bottom of the priority The round robin...

Page 662: ...ottom priority The priority of channels 0 and 1 which were higher than channel 2 are also shifted If immediately after there is a request to transfer channel 5 only channel 5 becomes bottom priority and the priority of channels 3 and 4 which were higher than channel 5 are also shifted Channel 1 becomes bottom priority The priority of channel 0 which was higher than channel 1 is also shifted Channe...

Page 663: ... 0 becomes lowest priority 5 At this point channel 1 has a higher priority than channel 3 so the channel 1 transfer begins channel 3 waits for transfer 6 When the channel 1 transfer ends channel 1 becomes lowest priority 7 The channel 3 transfer begins 8 When the channel 3 transfer ends channels 3 and 2 shift downward in priority so that channel 3 becomes the lowest priority Transfer request Waiti...

Page 664: ...le At this time transfer data is temporarily stored in the DMAC In the transfer between external memories as shown in figure 14 4 data is read to the DMAC from one external memory in a data read cycle and then that data is written to the other external memory in a write cycle Data buffer Address bus Data bus Address bus Data bus Memory Transfer source module Transfer destination module Memory Tran...

Page 665: ...K is output in read cycle or write cycle Figure 14 5 shows an example of DMA transfer timing in dual address mode CLKOUT A25 to A0 Note In transfer between external memories with DACK output in the read cycle DACK output timing is the same as that of CSn D31 to D0 WE RD DACK Active low CSn Transfer source address Transfer destination address Data read cycle Data write cycle 1st cycle 2nd cycle Fig...

Page 666: ...unit When that transfer ends the bus mastership is passed to the other bus master This is repeated until the transfer end conditions are satisfied In cycle steal normal mode transfer areas are not affected regardless of settings of the transfer request source transfer source and transfer destination Figure 14 6 shows an example of DMA transfer timing in cycle steal normal mode Transfer conditions ...

Page 667: ...tership from other bus master The DMAC then transfers data of one transfer unit and returns the bus mastership to other bus master These operations are repeated until the transfer end condition is satisfied It is thus possible to make lower the ratio of bus occupation by DMA transfer than cycle steal normal mode When the DMAC issues again the transfer request DMA transfer can be postponed in case ...

Page 668: ...ter the DMAC transfer request that has already been accepted ends even if the transfer end conditions have not been satisfied Burst mode cannot be used when the on chip peripheral module is the transfer request source Figure 14 9 shows DMA transfer timing in burst mode CPU CPU CPU DMAC DMAC DMAC DMAC DMAC DMAC CPU DREQ Read Read Read Write Write Write SuperHyway bus cycle Figure 14 9 DMA Transfer ...

Page 669: ...space DDRIF space PCIC space On chip peripheral module 1 L RAM LBSC space Yes Yes Yes Yes Yes DDRIF space Yes Yes Yes Yes Yes PCIC space Yes Yes Yes Yes Yes On chip peripheral module 1 Yes Yes Yes Yes Yes L RAM Yes Yes Yes Yes Yes Legend Yes Transfer is available Note 1 When the transfer source or destination is on chip peripheral module register the transfer size should be the same value of its a...

Page 670: ... transfer size should be the same value of its access size 2 Transfer is available when the AM bit in CHCR is cleared to 0 3 Transfer is available when the AM bit in CHCR is set to 1 4 Transfer is available when the AM bit in CHCR is set to 1 and the destination address of the PCIC is H FD00 0000 to H FDFF FFFF PCI memory space 0 5 Transfer is available when the AM bit in CHCR is cleared to 0 and ...

Page 671: ...n chip peripheral module the transfer is available in channel 0 to 5 4 Bus Mode and Channel Priority When the priority is set in fixed mode CH0 CH1 and channel 1 is transferring in burst mode if there is a transfer request to channel 0 with a higher priority the transfer of channel 0 will begin immediately At this time if channel 0 is also operating in burst mode the channel 1 transfer will contin...

Page 672: ...register DMAOR and DMA extended resource selectors DMARS are set the DMAC transfers data according to the following procedure 1 Checks to see if transfer is enabled DE 1 DME 1 TE 0 AE 0 NMIF 0 2 When a transfer request occurs while transfer is enabled the DMAC transfers one transfer unit of data depending on the TS0 and TS1 settings In auto request mode the transfer begins automatically when the D...

Page 673: ...rupt request IE 1 NMIF 1 or AE 1 or DE 0 or DME 0 HIE 0 or HE 1 TCR TCRB 2 Yes Yes Yes TCR 0 Repeat mode NMIF 1 or AE 1 or DE 0 or DME 0 HE 1 DEI interrupt request HIE 1 Notes 1 In repeat mode a transfer request is acceptted with TE 1 when HIE 1 and HE 0 half end interrupt is enable and clear the HE to 0 after HE is set to 1 2 In auto request mode transfer starts when bits NMIF AE and TE are all 0...

Page 674: ...imes Satisfy the following settings of CHCR Bits RPT 2 0 B 010 Repeat mode use DAR as a repeat area Bit HIE B 1 TCR 2 interrupt generated Bits DM 1 0 B 01 DAR incremented Bits SM 1 0 B 00 SAR fixed Bit IE B 1 Interrupt enabled Bit DE B 1 DMA transfer enabled Set such as bits TB and TS 2 0 according to use conditions Set bits CMS 1 0 and PR 1 0 in DMAOR according to use conditions and set the DME b...

Page 675: ...ly 14 4 6 Reload Mode Transfer In a reload mode transfer according to the settings of bits RPT 2 0 in CHCR the value set in SARB DARB is set to SAR DAR and the value of bits TCRB 23 16 is set in bits TCRB 7 0 at each transfer set in the bits TCRB 7 0 and the transfer is repeated until TCR becomes 0 without specifying the transfer settings again A reload mode transfer is effective when repeating da...

Page 676: ...arted 1st acceptance 2nd acceptance Non sensitive period DMAC Figure 14 13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection CPU CPU DMAC CLKOUT CPU CPU DMAC CLKOUT DREQ Overrun 0 Low level DACK Low active DRAK Low active DRAK Low active Bus cycle Acceptance started 1st acceptance 2nd acceptance DREQ Overrun 1 Low level DACK Low active Bus cycle Acceptance started 1st acceptance 2...

Page 677: ...REQ Input Detection in Burst Mode Edge Detection CPU DMAC CLKOUT CPU CLKOUT DREQ Overrun 0 Low level DRAK Low active Bus cycle Acceptance started 1st acceptance DREQ Overrun 1 Low level DRAK Low active DACK Low active DACK Low active Bus cycle 1st acceptance 3rd acceptance Acceptance started Acceptance started Non sensitive period 2nd acceptance 2nd acceptance DMAC DMAC Figure 14 16 Example of DRE...

Page 678: ...UT DREQ DACK Active high TEND Active high Bus cycle Last DMA transfer Figure 14 17 DMA Transfer End Signal Cycle Steal Mode Level Detection Note that the DACK output and TEND output are divided to align the data when an 8 bit or 16 bit external device is accessed in longword units or when an 8 bit external device is accessed in word units This example is shown in figure 14 18 ...

Page 679: ... Address Data TENDn Active low Note TEND is asserted during the last transfer unit of the DMA transfer When the transfer unit is divided into several bus cycles and CS is negated between bus cycles TEND is also divided DACKn Active low Figure 14 18 Example of BSC Ordinary Memory Access No Wait Idle Cycle 1 Longword Access to 16 Bit Device ...

Page 680: ... Address Error When a DMA address error is occurred after execute the following procedure and then start a transfer 1 Dummy read for the below listed registers BCR LBSC PCIECR PCIC MIM DDRIF INTCB3 INTC 2 Issue the SYNCO instruction 3 Set registers of all channels again If the AE bit in DMAOR is set to 1 channels 0 to 5 should be set again 14 5 3 Notes on Burst Mode Transfer During a burst mode tr...

Page 681: ...formed with larger transfer size than the bus width For example performing the 16 32 byte transfer to the 8 16 32 bit bus width LBSC space longword 32 bit transfer to the 8 16 bit bus width LBSC space or word 16 bit transfer to the 8 bit bus width LBSC space Note that except for a 32 bit access to the MPX interface This access generates only one bus cycle burst 2 When the CSn output is negated bet...

Page 682: ...ansfer source and the transfer destination are the LBSC spaces does not apply this Tables 14 12 to 14 15 show the number of the bus cycles generated in each DMA transfer and the register settings for the LBSC space With these settings CSn is not negated even if multiple bus cycles are generated Note that in the following settings when either the transfer source or the transfer destination is the L...

Page 683: ...s not negated Bus Width bit DMA Transfer Access Size Bus Cycle Number CSnBCR IWRRD IWRRS or IWW CSnWCR ADS and ADH Byte 1 Any Any Word 2 Any B 000 Longword 4 Any B 000 16 Byte 16 B 000 B 000 8 32 Byte 32 Any B 000 Byte 1 Any Any Word 1 Any Any Longword 2 Any B 000 16 Byte 8 B 000 B 000 16 32 Byte 16 Any B 000 Byte 1 Any Any Word 1 Any Any Longword 1 Any Any 16 Byte 4 B 000 B 000 32 32 Byte 8 Any B...

Page 684: ...ny 16 Byte 8 B 000 16 32 Byte 16 Any Table 14 14 Register Setting for MPX Interface Read Access Register Setting of CSn is not negated Bus Width bit DMA Transfer Access Size Bus Cycle Number CSnWCR ADS and ADH Byte 1 Any Word 1 Any Longword 1 Any 16 Byte 4 Impossible Negated 32 32 Byte 1 Any Table 14 15 Register Settings for MPX Interface Write Access Register Setting of CSn is not negated Bus Wid...

Page 685: ...ransfer to DMAC Prohibited Do not perform DMA transfer with the DMAC register specified as the transfer source or transfer destination 14 5 8 NMI Interrupt When an NMI interrupt occurs the DMA transfer is stopped After returning from the NMI interrupt routine set all channels again and then restart the DMA transfer ...

Page 686: ...Section 14 Direct Memory Access Controller DMAC Rev 1 00 Oct 01 2007 Page 620 of 1956 REJ09B0256 0100 ...

Page 687: ...access from an external CPU An external CPU is able to access the DDR SDRAM space and internal registers of this LSI The MPX protocol is used for access from an external CPU The SH7750 Group and the SH7751 Group can be connected as the external CPU via the buses of the SH7750 Group and the SH7751 Group Figure 15 1 shows a block diagram of the EXCPU Registers External CPU interface controller Super...

Page 688: ...RAME Access cycle Input Indicates an access cycle period EX_RDWR Read write Input Indicates whether it is data write or read EX_SIZE2 to EX_SIZE0 Access size Input Indicates the access size Note These pins are used in the SH7750 Group In the SH7751 Group pins D31 to D29 act as access size signals EX_AD0 EX_AD31 Address data Input output During an address phase signals on EX_AD25 to EX_AD0 are inpu...

Page 689: ...H FE40 000C H 1E40 000C 32 External CPU memory space select register EXCMSETR R W H FE40 0010 H 1E40 0010 32 External CPU output interrupt control register EXCINOR R W H FE40 0014 H 1E40 0014 32 Table 15 3 Register States in Each Operating Mode Register Name Abbrevia tion Power On Reset Manual Reset Sleep Standby External CPU control register EXCCTRL H 0000 0000 H 0000 0000 Retained Retained Exter...

Page 690: ... R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R W EXC CD EXC SEL Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 EXCMD Undefined R External CPU Connection Indicator Indicates the state of the MD10 pin 0 External CPU is not connected 1 External CPU ...

Page 691: ... 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R W R W R W R W EXCMSET 3 0 Bit Bit Name Initial Value R W Description 31 to 4 All 0 R Reserved These bits are always read as 0 The write value should always be 0 3 to 0 EXCMSET 0000 R W Internal Memory Space Base Address These bits set the base address of the memory space used for access to the internal memory by the external CPU The address of the m...

Page 692: ...1 0 Bit Initial value R W Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R W EXC INO Bit Bit Name Initial Value R W Description 31 to 1 All 0 R Reserved These bits are always read as 0 The write value should always be 0 0 EXCINI 0 R W Notification of Interrupt to External CPU 1 Asserts the EX_INT p...

Page 693: ...s access to the DDR SDRAM space in this LSI by converting the signal from the external CPU from the MPX protocol to the SuperHyway bus protocol In this process data alignment conversion is performed with the same endian as this LSI according to the access size from the external CPU 1 Space Accessible to the External CPU The DDR SDRAM space and internal registers of this LSI are accessible to the e...

Page 694: ...X_AD7 to EX_AD0 Byte access to address 0 Data 7 to data 0 Byte access to address 1 Data 7 to data 0 Byte access to address 2 Data 7 to data 0 Byte access to address 3 Data 7 to data 0 Byte access to address 4 Data 7 to data 0 Byte access to address 5 Data 7 to data 0 Byte access to address 6 Data 7 to data 0 Byte access to address 7 Data 7 to data 0 Word access to address 0 Data 15 to data 8 Data ...

Page 695: ... to address 4 Data 7 to data 0 Byte access to address 5 Data 7 to data 0 Byte access to address 6 Data 7 to data 0 Byte access to address 7 Data 7 to data 0 Word access to address 0 Data 15 to data 8 Data 7 to data 0 Word access to address 2 Data 15 to data 8 Data 7 to data 0 Word access to address 4 Data 15 to data 8 Data 7 to data 0 Word access to address 6 Data 15 to data 8 Data 7 to data 0 Lon...

Page 696: ... through handshaking of the access request BREQ and access acknowledge BACK signals Figures 15 2 and 15 3 show the access timing of the EXCPU and external CPU A0 D0 A0 D0 CLKOUT BREQ BACK EX_CS0 EX_BS EX_FRAME EX_RDY Read access Write access EX_RDWR EX_AD 31 0 CLKOUT BREQ BACK EX_CS0 EX_BS EX_FRAME EX_RDY EX_RDWR EX_AD 31 0 High Low Figure 15 2 External CPU Access Single Access ...

Page 697: ..._BS EX_FRAME EX_RDY Read access Write access EX_RDWR EX_AD 31 0 CLKOUT BREQ BACK EX_CS0 EX_BS EX_FRAME EX_RDY EX_RDWR EX_AD 31 0 High A0 D1 D6 D7 Low D0 Figure 15 3 External CPU Access Burst Access 4 Configuration of Connection to the External CPU Figure 15 4 shows the configuration of the connection between the external CPU and this LSI ...

Page 698: ...E DATA31 to DATA0 DATA31 to DATA29 RDWR BS CS CS BSREQ BSACK RDY SH7750 7751 This LSI BS EX_BS CS2 EX_CS1 CS1 EX_CS0 RD FRAME EX_FRAME RDWR EX_RDWR D31 EX_AD31 to D0 EX_AD0 BREQ BACK A25 EX_SIZE2 to A23 EX_SIZE0 RDY EX_RDY MD10 EXCPU LBSC EX_INT Figure 15 4 Configuration of Connection with External CPU ...

Page 699: ...k SHck used by the SuperHyway and peripheral clocks Pck0 Pck1 supplied to the peripheral modules Clocks supplied to outside modules Generates the bus clock Bck used by the external bus interface and the memory clocks DDRck used by the DDR interface Clock modes Either a crystal resonator or an externally input clock can be selected as the CPG clock input The combination of the division ratios for t...

Page 700: ...LKOUT Bus clock Bck CPU clock Ick SHwy clock SHck Pwripheral clock Pck0 Pck1 MD2 MD1 MD0 MD8 EXTAL PLLCR MSTPCR Bus interface Peripheral bus Legend Note Refer to section 18 Power Down Mode for detaiis on STBCR and MSTPCR FRQCR STBCR MSTPCR PLLCR Frequency control register Standby control register Module stop register PLL control register PLL cicuit 3 ４ DDRck0 DDRck90 DDRck180 DDRck270 DDR clock Di...

Page 701: ...tor used when a crystal resonator is connected to the XTAL or EXTAL pin The crystal oscillator can be enabled by the MD8 pin setting 4 Divider 1 Divider 1 generates the CPU clock Ick SHwy clock SHck peripheral module clocks Pck0 Pck1 and bus clock Bck The division ratio is selected by the combination of mode control pins MD0 MD1 and MD2 5 Frequency Control Register FRQCR The frequency control regi...

Page 702: ...MD2 Mode control pins 0 1 2 Clock operating mode Input Sets the clock operating mode after a power on reset MD8 Mode control pin 8 Clock input mode Input Selects the use of the crystal resonator MD8 low External clock is input from the EXTAL pin MD8 high Crystal resonator is connected to the EXTAL and XTAL pins XTAL Output A crystal resonator is connected EXTAL Input A crystal resonator is connect...

Page 703: ...ng Modes Notes 1 Mode pin MD0 MD1 and MD2 combinations other than above are prohibited 2 The ratio of the frequency of each clock to that of the crystal oscillator or the clock input from the EXTAL pin External pin combination 1 Clock generated by CPG Clock operating mode MD2 MD1 MD0 PLL 1 PLL 2 PLL 3 EXTAL frequency MHz Ick SHck Bck Pck0 Pck1 DDRck Initial value of FRQCR Frequency ratio 2 8 4 2 2...

Page 704: ...tion Register Name Abbrevia tion R W Area P4 Address Area 7 Address Access Size Frequency control register FRQCR R H FFC8 0000 H 1FC8 0000 32 PLL control register PLLCR R W H FFC8 0024 H 1FC8 0024 32 Table 16 4 Register States in Each Operating Mode Register Name Abbrevia tion Power On Reset Manual Reset Standby Sleep Frequency control register FRQCR H 1013 0035 Retained Retained Retained PLL cont...

Page 705: ...0 19 18 17 16 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 Bit Initial value R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R R R R R R R R R R R R CFC 2 0 BFC 2 0 P0FC 2 0 P1FC 2 0 R W R W R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 R W R W R W R W R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 31 to 28 0001 R Reserved These bits are read as B 0001 27 t...

Page 706: ...ator CPG Rev 1 00 Oct 01 2007 Page 640 of 1956 REJ09B0256 0100 Bit Bit Name Initial Value R W Description 3 0 R Reserved This bit is always read as 0 2 to 0 P1FC 2 0 101 R Peripheral Clock 1 Pck1 Frequency Division Ratio 101 1 16 ...

Page 707: ... R R R R R R R R R 0 Bit Bit Name Initial Value R W Description 31 to 15 All 0 R Reserved The write value should be the same as the initial values 14 13 All 1 R Reserved The write value should be the same as the initial values 12 to 2 All 0 R Reserved The write value should be the same as the initial values 1 CKOFF 0 R W CLKOUT Output Stop 0 Clock is output from the CLKOUT pin 1 Clock is not outpu...

Page 708: ... to cross the EXTAL or XTAL line to prevent induction from interfering with correct oscillation Avoid crossing signal lines Note The values for CL1 CL2 and the damping resistance should be determined after consultation with the crystal resonator manufacturer Recommended values CL1 CL2 0 33 pF R 0 Ω Crystal resonator XTAL R SH7763 EXTAL CL2 CL1 Figure 16 2 Notes on Using Crystal Resonator 2 Notes o...

Page 709: ... and bypass capacitors CPB near the pins for noise filtering VDD DLL and VSS DLL should be set to the same level as the VDD and VSS levels respectively VDD PLL1 VSS PLL1 SH7763 VDD PLL2 VSS PLL2 VDD PLL3 VSS PLL3 CPB11 0 1µF CPB12 RCB1 RCB1 RCB2 RCB3 4 7Ω CPB11 CPB21 CPB31 0 1µF CPB12 CPB22 CPB32 1µF Recommended values 1 25V 1µF 4 7Ω 4 7 Ω 4 7 Ω CPB21 0 1µF CPB22 RCB2 1µF CPB31 0 1µF CPB32 RCB3 1µ...

Page 710: ...Section 16 Clock Pulse Generator CPG Rev 1 00 Oct 01 2007 Page 644 of 1956 REJ09B0256 0100 ...

Page 711: ... Features WDT monitors a system crash using a timer counting at specified intervals WDT supports the watchdog timer mode and the interval timer mode WDT generates an internal reset when a WDT overflow occurs in watchdog timer mode A power on reset or a manual reset can be selectable WDT generates the interval timer interrupt when counter overflow occurs in interval timer mode The maximum time unti...

Page 712: ... WDTCNT WDTCSR WDTST Count up signal Comparator Reset control circuit CPG Internal reset request Interrupt control circuit INTC Peripheral clock Legend WDTBCNT Watchdog timer base counter WDTBST Watchdog timer base stop time register WDTCNT Watchdog timer counter WDTCSR Watchdog timer control status register WDTST Watchdog timer stop time register WDTBCNT WDTBST Comparator Figure 17 1 System Block...

Page 713: ...on I O Description PRESET Power on reset input Input Power on reset occurs at low level MRESET Manual reset input Input Manual reset occurs at low level STATUS1 Processing state 1 Indicate the processor s operating status STATUS0 Processing state 0 Output STATUS1 High High Low Low STATUS0 High Low High Low Operating Status Reset Sleep mode Standby mode Normal operation Note These pins are multiple...

Page 714: ... FFCC 0008 H 1FCC 0008 32 Watchdog timer counter WDTCNT R H FFCC 0010 H 1FCC 0010 32 Watchdog timer base counter WDTBCNT R H FFCC 0018 H 1FCC 0018 32 Table 17 3 Register State in Each Operating Mode Register Name Abbreviation Power on Reset by PRESET Pin Power on Reset by WDT H UDI Manual Reset Sleep Standby Watchdog timer stop time register WDTST H 0000 0000 Retained Retained Retained Retained Wa...

Page 715: ...g value of bits 31 to 24 is always H 00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R W R W R W R W R W R W R W R W Bit Initial value Given code R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTST R W R W R W R W R W R W R W R W R W R W R W R W R R R R Bit Initial value R W Bit Bit Name Initial Value R W Description 31...

Page 716: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOVF WOVF RSTS WT IT TME R R R R W R W R W R W R W R R R R R R R R Bit Initial value R W Given code Bit Bit Name Initial Value R W Description 31 to 24 Given code H 00 R W Reserved Given code for writing These bits are always read as H 00 To write to this register the write value must be H A5 23 to 8 All 0 R Reserved These bits are always read as 0 The write value sh...

Page 717: ... reset 4 WOVF 0 R W Watchdog Timer Overflow Flag Indicates that WDTCNT has overflowed in watchdog timer mode This flag is not set in interval timer mode 0 An overflow has not occurred 1 An overflow on WDTCNT has occurred 3 IOVF 0 R W Interval Timer Overflow Flag Indicates that WDTCNT has overflowed in interval timer mode This flag is not set in watchdog timer mode 0 An overflow has not occurred 1 ...

Page 718: ... 22 23 24 25 26 27 28 29 31 30 R R R R R R R R R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value PCI R W Bit Initial value PCI R W Given code Bit Bit Name Initial Value R W Description 31 to 24 Given code R W H 00 Reserved Given code for writing These bits are alway...

Page 719: ... R R R R R R R R R Bit Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTCNT R R R R R R R R R R R R R R R R Bit Initial value R W 17 3 5 Watchdog Timer Base Counter WDTBCNT WDTBCNT is a 32 bit read only register that comprises 18 bit counter and counts up on the peripheral clock Pck0 When WDTBCNT overflows WDTCNT is counted up and WDTBCNT is cleared to 0 W...

Page 720: ...the EXPEVT register The VBR and SR registers are initialized and the program branches to PC H A000 0000 By initialization the VBR register is set to H 0000 0000 In the SR register the MD RB and BL bits are set to 1 the FD bit is cleared to 0 and the IMASK3 to IMASK0 bits interrupt mask level are set to B 1111 The CPU and the peripheral modules are also initialized For details see the register desc...

Page 721: ... to PC H A000 0000 By initialization the VBR register is set to H 0000 0000 In the SR register the MD RB and BL bits are set to 1 the FD bit is cleared to 0 and the IMASK3 to IMASK0 bits interrupt mask level are set to B 1111 The CPU and the peripheral modules are also initialized For details see the register descriptions in each section Manual_reset EXPEVT H 0000 0020 VBR H 0000 0000 SR MD 1 SR R...

Page 722: ...is operating in interval timer mode an interval timer interrupt is generated each time the counter overflows This enables interrupts to be generated at fixed intervals 1 Set the WDTCNT overflow time in WDTST 2 Clear the WT IT bit in WDTCSR to 0 3 When the TME bit in WDTCSR is set to 1 the WDT count starts 4 When the WDTCNT overflows the WDT sets the IOVF flag in WDTCSR to 1 and sends an interval t...

Page 723: ...flow signal of WDTBCNT Interval timer mode Clear counter when overflowed Clear counter when overflowed WDT mode Clear counter after reset operation Counting up with Pck Start counting up Set flag Time Time WDTCNT value H 0003 FFFF H 0000 0000 TME WOVF IOVF WDTBCNT value Reset internal Interval timer mode WDT mode Figure 17 2 WDT Counting Up Operation ...

Page 724: ...er starts count up operation when overflow occurs in WDTBCNT The time until WDTCNT overflows becomes the maximum value when H 000 is set to WDTST Where the peripheral clock frequency is 66 6 MHz the maximum overflow time is approximately 16 105 s 2 12 bit 3 932 ms And the time until WDTCNT overflows becomes the minimum value when H 5A000001 is set to WDTST The minimum overflow time is approximatel...

Page 725: ...n settling time and the PLL2 synchronization settling time After the PRESET pin input level is changed from low level to high level the reset state is continued during the reset holding time in the LSI The reset holding time is 20 clock cycles of the EXTAL pin input clock and thereafter equal to or more than 45 clock cycles of the peripheral clock Pck0 The STATUS 1 0 pins output timing that indica...

Page 726: ... 01 2007 Page 660 of 1956 REJ09B0256 0100 VDD TRST input PRESET input CLKOUT output STATUS 1 0 output HH reset LL normal EXTAL input stabilization time PLL oscillation settling time Reset holding time EXTAL input Figure 17 3 STATUS Output during Power on ...

Page 727: ...l PLL oscillation settling time Reset holding time EXTAL input PRESET input Figure 17 4 STATUS Output by Reset input during Normal Operation 3 PRESET input during Sleep Mode It is necessary to ensure the PLL oscillation time when power on reset generates by the PRESET pin low revel input during sleep mode CLKOUT output STATUS 1 0 output HH reset LL normal HL sleep PLL oscillation settling time Res...

Page 728: ...is 1 clock cycle of the EXTAL input clock and thereafter equal to or more than 5 clock cycles of the peripheral clock Pck0 The STATUS 1 0 pins output timing that indicates the reset state or a normal operation is asynchronous with both the EXTAL pin input clock and the CLKOUT pin input clock because the STATUS 1 0 pins output timing is synchronous with the peripheral clock Pck0 1 Power On Reset by...

Page 729: ...56 0100 2 Power On Reset by Watchdog timer Overflowed in Sleep Mode CLKOUT output STATUS 1 0 output WDT overflow signal HH reset LL normal EXTAL input WDT reset stabilization time WDT reset holding time Figure 17 7 STATUS Output by Watchdog timer overflow Power On Reset during Sleep Mode ...

Page 730: ...t and thereafter equal to or more than 5 clock cycles of the peripheral clock Pck0 The STATUS 1 0 pins output timing that indicates the reset state or a normal operation is asynchronous with both the EXTAL pin input clock and the CLKOUT pin input clock because the STATUS 1 0 pins output timing is synchronous with the peripheral clock Pck0 1 Manual Reset by Watchdog timer Overflowed in Normal Opera...

Page 731: ...0100 2 Manual Reset by Watchdog timer Overflowed in Sleep Mode CLKOUT output WDT overflow signal STATUS 1 0 output HH reset HL sleep LL normal EXTAL input WDT reset stabilization time WDT reset holding time Figure 17 9 STATUS Output by Watchdog timer overflow Manual Reset during Sleep Mode ...

Page 732: ...Section 17 Watchdog Timer and Reset WDT Rev 1 00 Oct 01 2007 Page 666 of 1956 REJ09B0256 0100 ...

Page 733: ...pports RTC power supply backup mode where the power supply for only the RTC is held and other power supplies are turned off Supports DDR SDRAM power supply backup mode where the power supply for only the 2 5 V power supplied modules are held and other power supplies are turned off 18 1 1 Types of Power Down Modes The types and functions of power down modes are as shown below Sleep mode Software st...

Page 734: ...t Halt Halt Run Halt Hi Z 4 Undefined refresh not performed Power on reset 0 1 DDR SDRAM power supply backup 1 3 See section 18 7 DDR SDRAM Power Supply Backup Halt Halt Halt Halt Halt Undefined 5 SR 6 Power on reset 0 0 Power on reset PRESET pin driven low Initial state Initial state Initial state Counter retained Initial state Initial state Initial state 1 1 Manual reset MRESET pin driven low or...

Page 735: ...CLKOUT pin continues if the CKONE bit in PLLCR of the CPG is set to 1 18 2 Input Output Pins Table 18 2 lists the pin configuration related to power down modes Table 18 2 Pin Configuration Pin Name Function I O Description STATUS1 Processing state 1 Output STATUS0 Processing state 0 Output These pins indicate the operating state of this LSI STATUS 1 0 Operating state H H Power on reset or manual r...

Page 736: ...s Access Size Standby control register STBCR R W H FFC8 0020 H 1FC8 0020 32 Module stop register 0 MSTPCR0 R W H FFC8 0030 H 1FC8 0030 32 Module stop register 1 MSTPCR1 R W H FFC8 0038 H 1FC8 0038 32 Table 18 4 Register States in Each Operating Mode Register Name Abbreviation Power On Reset Manual Reset Sleep Standby Standby control register STBCR H 0000 0000 Retained Retained Retained Module stop...

Page 737: ... R R R R R R R R R R R 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R R R R R R R R R R R Bit Initial value R W Bit Initial value R W 0 R STBY Bit Bit Name Initial Value R W Description 31 to 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7 STBY 0 R W Standby Selects whether to enter sleep mode or software standby mo...

Page 738: ... 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R LCDC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R W R Bit Bit Name Initial Value R W Description 31 to 16 All 0 R Reserved These bits are always read as 0 The write value should always be 0 15 LCDC 0 R W LCDC Module Stop Bit When set to 1 the clock supply to the LCDC ...

Page 739: ...C PCC R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R SCIF0 ADC DAC CMT TMU1 TMU0 TPU MMC SIM SCIF1 SCIF2 SIOF0 SIOF1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R W R W R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 31 0 R Reserved This bit is always read as 0 The write value should always be 0 30 PCC 0 R W PCC Module S...

Page 740: ...upply to STIF0 is halted 26 SSI3 0 R W SSI3 Module Stop Bit When set to 1 the clock supply to the SSI3 module is halted 0 SSI3operates 1 Clock supply to SSI3 is halted 25 SSI2 0 R W SSI2 Module Stop Bit When set to 1 the clock supply to the SSI2 module is halted 0 SSI2 operates 1 Clock supply to SSI2 is halted 24 SSI1 0 R W SSI1 Module Stop Bit When set to 1 the clock supply to the SSI1 module is ...

Page 741: ...s halted 20 SIOF2 0 R W SIOF2 Module Stop Bit When set to 1 the clock supply to the SIOF2 module is halted 0 SIOF2 operates 1 Clock supply to SIOF2 is halted 19 SIOF1 0 R W SIOF1 Module Stop Bit When set to 1 the clock supply to the SIOF1 module is halted 0 SIOF1 operates 1 Clock supply to SIOF1 is halted 18 SIOF0 0 R W SIOF0 Module Stop Bit When set to 1 the clock supply to the SIOF0 module is ha...

Page 742: ...1 Clock supply to SCIF0 is halted 14 SIM 0 R W SIM Module Stop Bit When set to 1 the clock supply to the SIM module is halted 0 SIM operates 1 Clock supply to SIM is halted 13 ADC 0 R W ADC Module Stop Bit When set to 1 the clock supply to the ADC module is halted 0 ADC operates 1 Clock supply to ADC is halted 12 DAC 0 R W DAC Module Stop Bit When set to 1 the clock supply to the DAC module is hal...

Page 743: ... 8 TPU 0 R W TPU Module Stop Bit When set to 1 the clock supply to the TPU module is halted 0 TPU operates 1 Clock supply to TPU is halted 7 to 4 All 0 R Reserved These bits are always read as 0 The write value should always be 0 3 MMC 0 R W MMC Module Stop Bit When set to 1 the clock supply to the MMC module is halted 0 MMC operates 1 Clock supply to MMC is halted 2 to 0 All 0 R Reserved These bi...

Page 744: ...R is 1 If necessary save SPC and SSR to the stack before executing the SLEEP instruction 1 Canceling with Interrupt When an NMI IRQ IRL 7 0 or on chip peripheral module interrupt occurs sleep mode is canceled and interrupt exception handling is executed A code indicating the interrupt source is set in INTEVT 2 Canceling with Reset Sleep mode is canceled by a power on reset caused by the RESET pin ...

Page 745: ...TBY bit in STBCR to 1 2 Execute the SLEEP instruction 3 Software standby mode is entered and the clocks within the LSI are halted The output on the STATUS0 pin goes high All modules should be stopped before the above procedure is executed 18 5 2 Canceling Software Standby Mode Software standby mode is canceled by an interrupt NMI or IRQ IRL or a reset 1 Canceling with Interrupt When an NMI or IRQ ...

Page 746: ... normal mode Modules in module standby mode keep the state immediately before the transition to the module standby mode The registers retain their contents before the module is halted and the external pins also hold their states before halted At waking up from the module standby state operation starts from the condition immediately before the module was halted 18 6 2 Canceling Module Standby Mode ...

Page 747: ...a cancellation of the self refresh mode are done by issuing a command 1 RMODE Bit Bit 33 in the MIM register The initial value is 0 Setting this bit to 1 after setting the DRE bit in MIM to 1 causes the DDRIF to start the sequence for a transition to the self refresh mode For details see section 12 5 5 1 Self Refresh Mode 2 Bits SMS2 to SMS0 Bits 2 to 0 in the SCR register These bits are used to a...

Page 748: ... the all bank precharge command PREALL with bits SMS2 to SMS0 in SCR by software Activated banks will be closed After that issue the auto refresh command REFA with bits SMS2 to SMS0 in SCR to perform CBR refresh on all rows 3 Specify the DRE and RMODE bits in the MIM register of the DDRIF to put the SDRAM into the self refresh mode At this time keep the DCE bit set to 1 The DDRIF automatically iss...

Page 749: ...nceled 1 Confirm that all transactions of DDRIF caused by on chip peripheral modules are completed 2 3 4 5 6 Set SCR to issue PREALL and REFA commands Set MIM to issue self refresh command Set MIM SELFS 1 Drive M_BKPRST from high to low Turn off system power supply Time Processing Command SELFS Low High REFA NOP PREALL REFA REFS Low High M_CKE SDRAM State Performs auto refresh at regular intervals...

Page 750: ...ower on reset Even when any interrupt condition is satisfied in the RTC power supply backup mode the interrupt generating condition will be canceled by the power on reset RTC power supply backup mode can be canceled in the following steps 1 Turn on the VDD power supply 1 2 V while holding the PRESET signal low 2 Since the VDD RTC 3 3 V which is exclusively used for the RTC is supplied drive the XR...

Page 751: ...t canceled Figure 18 3 Sequence for Turning VDD Power Supply 1 2 V On Off 18 9 STATUS Pin Signal Change Timing 18 9 1 Timing at Reset Refer to section 17 5 Status Pin Change Timing during Reset 18 9 2 Timing at Sleep Mode Cancellation 1 When an Interrupt Occurs in Sleep Mode Figure 18 4 shows the timing of signal changes on the STATUS pins HL sleep Interrupt request LL Normal operation LL Normal o...

Page 752: ...Section 18 Power Down Mode Rev 1 00 Oct 01 2007 Page 686 of 1956 REJ09B0256 0100 ...

Page 753: ... or falling edge as external clock input edge when external clock is selected or input capture function is used for each channel 32 bit timer constant register for auto reload use readable writable at any time and 32 bit down counter provided for each channel Selection of seven counter input clocks External clock TMU_TCLK for channel 0 to 2 only RTC clock RTCCLK and five peripheral clocks Pck0 4 P...

Page 754: ...start register Timer constant register Timer counter Timer control register Input capture register 2 only in channel 2 TMU operation controller TOCR TSTR To each channel TUNI2 TUNI2 TCLK Pck 4 Pck 16 Pck 64 TUNI0 1 3 4 and 5 RESET STBY etc RTCCLK To channels 0 to 2 Counter TCR2 Interrupt controller Prescaler TCLK controller TCOR2 TCNT2 TCPR2 Counter Bus interface TCR Interrupt controller TCOR TCNT...

Page 755: ...1956 REJ09B0256 0100 19 2 Input Output Pins Table 19 1 shows the TMU pin configuration Table 19 1 Pin Configuration Pin Name Function I O Description TMU_TCLK Clock input Input Channel 0 1 and 2 external clock input pin channel 2 input capture control input pin ...

Page 756: ... 1FD8 0018 32 1 Timer control register 1 TCR1 R W H FFD8 001C H 1FD8 001C 16 Timer constant register 2 TCOR2 R W H FFD8 0020 H 1FD8 0020 32 Timer counter 2 TCNT2 R W H FFD8 0024 H 1FD8 0024 32 Timer control register 2 TCR2 R W H FFD8 0028 H 1FD8 0028 16 2 Input capture register 2 TCPR2 R H FFD8 002C H 1FD8 002C 32 3 4 5 Common Timer start register 1 TSTR1 R W H FFD8 8004 H 1FD8 8004 8 Timer consta...

Page 757: ...tained Retained Timer counter 2 TCNT2 H FFFF FFFF H FFFF FFFF Retained Retained Timer control register 2 TCR2 H 0000 H 0000 Retained Retained 2 Input capture register 2 TCPR2 H XXXX XXXX H XXXX XXXX Retained Retained 3 4 5 Common Timer start register 1 TSTR1 H 00 H 00 Retained Retained Timer constant register3 TCOR3 H FFFF FFFF H FFFF FFFF Retained Retained Timer counter 3 TCNT3 H FFFF FFFF H FFFF...

Page 758: ... input pin 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 TCOE R W R R R R R R R BIt Initial value R W Bit Bit Name Initial Value R W Description 7 to 1 All 0 R Reserved These bits are always read as 0 The write value should always be 0 0 TCOE 0 R W Timer Clock Pin Control TCOE Specifies whether timer clock pin TMU_TCLK is used as the external clock or input capture control input pin 0 TMU_TCLK is used as extern...

Page 759: ...Value R W Description 7 to 3 All 0 R Reserved These bits are always read as 0 The write value should always be 0 2 STR2 0 R W Counter Start 2 Specifies whether TCNT2 is operated or stopped 0 TCNT2 count operation is stopped 1 TCNT2 performs count operation 1 STR1 0 R W Counter Start 1 Specifies whether TCNT1 is operated or stopped 0 TCNT1 count operation is stopped 1 TCNT1 performs count operation...

Page 760: ... as 0 The write value should always be 0 2 STR5 0 R W Counter Start 5 Specifies whether TCNT5 is operated or stopped 0 TCNT5 count operation is stopped 1 TCNT5 performs count operation 1 STR4 0 R W Counter Start 4 Specifies whether TCNT4 is operated or stopped 0 TCNT4 count operation is stopped 1 TCNT4 performs count operation 0 STR3 0 R W Counter Start 3 Specifies whether TCNT3 is operated or sto...

Page 761: ...e R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 BIt Initial value R W 19 3 4 Timer Counter TCNTn n 0 to 5 The TCNT registers are 32 bit readable writable registers Each TCNT counts down on the input clock selected by the TPSC2 to TPSC0 bits in TCR When a TCNT counter underflows while counting down the UNF flag is set in TCR of the corresponding channel At the same time the TCOR value is set in TCNT an...

Page 762: ...al value R W TCR2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TPSC0 TPSC1 TPSC2 CKEG0 CKEG1 UNIE ICPE0 ICPE1 UNF ICPF R W R W R W R W R W R W R W R W R W R W R R R R R R BIt Initial value R W Bit Bit Name Initial Value R W Description 15 to 10 All 0 R Reserved These bits are always read as 0 The write value should always be 0 9 ICPF 1 0 R W Input Capture Interrupt Flag St...

Page 763: ...ng prohibited 10 Input capture function is used but interrupt due to input capture TICPI2 is not enabled Data transfer request is sent to the DMAC in the event of input capture 11 Input capture function is used and interrupt due to input capture TICPI2 is enabled 5 UNIE 0 R W Underflow Interrupt Control Controls enabling or disabling of interrupt generation when the UNF status flag is set to 1 ind...

Page 764: ...or 1 initial value is 0 and can only be read 2 Writing 1 does not change the value the previous value is retained 3 Do not set in channels 3 4 and 5 19 3 6 Input Capture Register 2 TCPR2 TCPR2 is a 32 bit read only register for use with the input capture function provided only in channel 2 The input capture function is controlled by means of the ICPE and CKEG bits in TCR2 When input capture occurs...

Page 765: ...nting Channel 2 also has an input capture function 19 4 1 Counter Operation When one of bits STR0 to STR2 in TSTR is set to 1 the TCNT for the corresponding channel starts counting When TCNT underflows the UNF flag in TCR is set If the UNIE bit in TCR is set to 1 at this time an interrupt request is sent to the CPU At the same time the value is copied from TCOR into TCNT and the count down continu...

Page 766: ...set without clearing the flag another interrupt will be generated Select the count clock with the TPSC2 to TPSC0 bits in TCR When the external clock TCLK is selected specify the external clock edge with the CKEG1 and CKEG0 bits in TCR Specify whether an interrupt is to be generated on TCNT underflow with the UNIE bit in TCR When the input capture function is used set the ICPE bits in TCR including...

Page 767: ...TCNT on underflow Time Figure 19 3 TCNT Auto Reload Operation 3 TCNT Count Timing Operating on internal clock Any of five count clocks Pck0 4 Pck0 16 Pck0 64 Pck0 256 or Pck0 1024 scaled from the peripheral clock can be selected as the count clock by means of the TPSC2 to TPSC0 bits in TCR Figure 19 4 shows the timing in this case Internal clock Pck TCNT N 1 N N 1 Figure 19 4 Count Timing when Ope...

Page 768: ...selected with the CKEG1 and CKEG0 bits in TCR Figure 19 5 shows the timing for both edge detection External clock input pin Pck TCNT N 1 N N 1 Figure 19 5 Count Timing when Operating on External Clock Operating on on chip RTC output clock The on chip RTC output clock can be selected as the timer clock by means of the TPSC2 to TPSC0 bits in TCR Figure 19 6 shows the timing for both edge detection R...

Page 769: ...this function is used 3 Use bits CKEG1 and CKEG0 in TCR to specify whether the rising or falling edge of the TCLK pin is to be used to set the TCNT value in TCPR2 When input capture occurs the TCNT2 value is set in TCPR2 only when the ICPF bit in TCR2 is 0 A new DMAC transfer request is not generated until processing of the previous request is finished Figure 19 7 shows the operation timing when t...

Page 770: ... and the interrupt enable bit UNIE for that channel are set to 1 When the input capture function is used and an input capture request is generated an interrupt is requested if the ICPF bit in TCR2 is 1 and the input capture control bits ICPE1 and ICPE0 in TCR2 are both set to 11 The TMU interrupt sources are summarized in Table 19 4 Table 19 4 TMU Interrupt Sources Channel Interrupt Source Descrip...

Page 771: ...n the flags UNF and ICPF are cleared while the count is in progress make sure not to change the values of bits other than those being cleared 19 6 2 Reading from TCNT Reading from TCNT is performed synchronously with the timer count operation Note that when the timer count operation is performed simultaneously with reading from a register the synchronous processing causes the TCNT value before the...

Page 772: ...Section 19 Timer Unit TMU Rev 1 00 Oct 01 2007 Page 706 of 1956 REJ09B0256 0100 ...

Page 773: ... input clocks for channels 2 and 3 The following operations can be set for each channel Waveform output at compare match Selection of 0 1 or toggle output Counter clear operation Counter clearing possible by compare match PWM mode Any PWM output duty can be set Maximum of 4 phase PWM output possible Buffer operation settable for each channel Automatic rewriting of output compare register possible ...

Page 774: ...General registers buffer registers TGR0C TGR0D TGR1C TGR1D TGR2C TGR2D TGR3C TGR3D Output pins TPU_TO0 TPU_TO1 TPU_TO2 TPU_TO3 Counter clear function TGR compare match TGR compare match TGR compare match TGR compare match Compare 0 output match 1 output output Toggle output PWM mode Phase counting mode Buffer operation Interrupt sources 5 sources Compare match Overflow 5 sources Compare match Over...

Page 775: ...annel 1 Same as channel 0 Channel 3 Same as channel 2 Note 1 clear TGRA Pck0 TPU_TI2A TPU_TI2B TPU_TI3A TPU_TI3B TPU_TO0 TPU_TO2 TPU_TO1 TPU_TO3 Pck0 1 Pck0 4 Pck0 16 Pck0 64 TGRB TGRC TGRD Selecter Clock selection Edge selection Comparator Buffer Phase comparison Counter up Output control Note 1 Note 1 Output disabled Initial value 0 1 Compare match 0 1 toggle clear down TGRA TGRB TGRC TGRD Selec...

Page 776: ...put TGR1A output compare output PWM output pin 2 Output compare match 2A TPU_TO2 Output TGR2A output compare output PWM output pin Clock input 2A TPU_TI2A Input External clock channel 2A input pin channel 2 counting mode A phase input Clock input 2B TPU_TI2B Input Channel 2 counting mode B phase input 3 Output compare match 3A TPU_TO3 Output TGR3A output compare output PWM output pin Clock input 3...

Page 777: ... 1FE2 8028 16 Timer general register B_0 TGRB_0 R H FFE2 802C H 1FE2 802C 16 Timer general register C_0 TGRC_0 R H FFE2 8030 H 1FE2 8030 16 Timer general register D_0 TGRD_0 R H FFE2 8034 H 1FE2 8034 16 Timer control register_1 TCR_1 R W H FFE2 8050 H 1FE2 8050 16 Timer mode register_1 TMDR_1 R W H FFE2 8054 H 1FE2 8054 16 Timer I O control register_1 TIOR_1 R W H FFE2 8058 H 1FE2 8058 16 Timer in...

Page 778: ...ontrol register_3 TCR_3 R W H FFE2 80D0 H 1FE2 80D0 16 Timer mode register_3 TMDR_3 R W H FFE2 80D4 H 1FE2 80D4 16 Timer I O control register_3 TIOR_3 R W H FFE2 80D8 H 1FE2 80D8 16 Timer interrupt enable register_3 TIER_3 R W H FFE2 80DC H 1FE2 80DC 16 Timer status register_3 TSR_3 R W H FFE2 80E0 H 1FE2 80E0 16 Timer counter_3 TCNT_3 R H FFE2 80E4 H 1FE2 80E4 16 Timer general register A_3 TGRA_3...

Page 779: ...r_1 TCR_1 H 0000 H 0000 Retained Retained Timer mode register_1 TMDR_1 H 0000 H 0000 Retained Retained Timer I O control register_1 TIOR_1 H 0000 H 0000 Retained Retained Timer interrupt enable register_1 TIER_1 H 0000 H 0000 Retained Retained Timer status register_1 TSR_1 H 0000 H 0000 Retained Retained Timer counter_1 TCNT_1 H 0000 H 0000 Retained Retained Timer general register A_1 TGRA_1 H FFF...

Page 780: ...egister_3 TMDR_3 H 0000 H 0000 Retained Retained Timer I O control register_3 TIOR_3 H 0000 H 0000 Retained Retained Timer interrupt enable register_3 TIER_3 H 0000 H 0000 Retained Retained Timer status register_3 TSR_3 H 0000 H 0000 Retained Retained Timer counter_3 TCNT_3 H 0000 H 0000 Retained Retained Timer general register A_3 TGRA_3 H FFFF H FFFF Retained Retained Timer general register B_3 ...

Page 781: ...d Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R W R W R W R W R W R W R W R W CCLR 2 0 CKEG 1 0 TPSC 2 0 Bit Bit Name Initial Value R W Description 15 to 8 All 0 R Reserved These bits are always read as 0 and cannot be modified 7 to 5 CCLR 2 0 000 R W Counter Clear These bits select the TCNT counter clearing source 000 TCNT clearing d...

Page 782: ...unt at rising edge 01 Count at falling edge 1X Count at both edges Legend X Don t care Note If Pck0 1 is selected for the input clock operation is disabled 2 to 0 TPSC 2 0 000 R W Time Prescaler These bits select the TCNT counter clock The clock source can be selected independently for each channel Table 20 5 shows the clock sources that can be set for each channel For more in formation on count c...

Page 783: ...le 20 6 TPSC 2 0 2 Channel TPSC 2 TPSC 1 TPSC 0 Description 1 0 0 0 Internal clock counts on Pck0 1 Initial value 1 Internal clock counts on Pck0 4 1 0 Internal clock counts on Pck0 16 1 Internal clock counts on Pck0 64 1 Reserved setting prohibited Table 20 6 TPSC 2 0 3 Channel TPSC2 TPSC1 TPSC0 Description 2 0 0 0 Internal clock counts on Pck0 1 Initial value 1 Internal clock counts on Pck0 4 1 ...

Page 784: ...TPSC 2 0 4 Channel TPSC2 TPSC1 TPSC0 Description 3 0 0 0 Internal clock counts on Pck0 1 Initial value 1 Internal clock counts on Pck0 4 1 0 Internal clock counts on Pck0 16 1 Internal clock counts on Pck0 64 1 0 0 External clock counts on TPU_TI3A pin input 1 Reserved setting prohibited 1 Note Don t care ...

Page 785: ... W Description 15 to 7 All 0 R Reserved These bits are always read as 0 and cannot be modified 6 BFWT 0 R W Buffer Write Timing Specifies TGRA and TGRB update timing when TGRC and TGRD are used as a compare match buffer When TGRC and TGRD are not used as a compare match buffer register this bit does not function 0 TGRA and TGRB are rewritten at compare match of each register 1 TGRA and TGRB are re...

Page 786: ...ting prohibited 010 PWM mode 011 Reserved setting prohibited 100 Phase counting mode 1 101 Phase counting mode 2 110 Phase counting mode 3 111 Phase counting mode 4 Note Operation when setting BFWT BFB BFA 1 1 0 is the same as when setting BFWT BFB BFA 1 0 1 However when the BFB bit is set to 1 TGRB and TGRD used together for buffer operation the setting of BFWT BFB BFA 1 1 1 should be made In thi...

Page 787: ...ould be made only when TCNT operation is halted Care is required since TIOR is affected by the TMDR setting If the counting operation is halted the initial value set by this register is output from the TPU_TO pin 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R W R W R W Bit Initial value R W IOA 2 0 Bit Bit Name Initial Value R W Description 15 to ...

Page 788: ...l value 0 1 0 output at TGRA compare match 0 1 output at TGRA compare match 0 1 1 Initial output is 0 output for TPU_TO pin Toggle output TGRA at compare match 0 Always 1 output 0 1 0 output at TGRA compare match 0 1 output at TGRA compare match 0 to 3 1 1 1 Initial output is 1 output for TPU_TO pin Toggle output at TGRA compare match Note This setting is invalid in PWM mode ...

Page 789: ...ved These bits are always read as 0 and cannot be modified 5 TC1EU 0 R W Underflow Interrupt Enable Enables or disables interrupt requests by the TCFU bit when the TCFU bit in TSR is set to 1 in phase counting mode of channels 2 and 3 TCNT underflow In channels 0 and 1 bit 5 is reserved It is always read as 0 and cannot be modified 0 Interrupt requests by TCFU disabled 1 Interrupt requests by TCFU...

Page 790: ...y TGFC disabled 1 Interrupt requests by TGFC enabled 1 TG1EB 0 R W TGR Interrupt Enable B Enables or disables interrupt requests by the TGFB bit when the TGFB bit in TSR is set to 1 TCNT and TGRB compare match 0 Interrupt requests by TGFB disabled 1 Interrupt requests by TGFB enabled 0 TG1EA 0 R W TGR Interrupt Enable A Enables or disables interrupt requests by the TGFA bit when the TGFA bit in TS...

Page 791: ...ription 15 to 8 All 0 R Reserved These bits are always read as 0 and cannot be modified 7 TCFD 0 R Count Direction Flag Status flag that shows the direction in which TCNT counts in phase counting mode of channels 2 and 3 In channels 0 and 1 bit 7 is reserved It is always read as 0 and cannot be modified 0 TCNT counts down 1 TCNT counts up 6 0 R Reserved This bit is always read as 0 and cannot be m...

Page 792: ...D 0 R W Compare Flag D Status flag that indicates the occurrence of TGRD compare match Clearing conditions When 0 is written to TGFD after reading TGFD 1 Setting conditions When TCNT TGRD 2 TGFC 0 R W Compare Flag C Status flag that indicates the occurrence of TGRC compare match Clearing conditions When 0 is written to TGFC after reading TGFC 1 Setting conditions When TCNT TGRC 1 TGFB 0 R W Compar...

Page 793: ...sters are 16 bit counters The TPU has four TCNT counters one for each channel The TCNT counters are initialized to H 0000 by a reset The TCNT counters are not initialized in standby mode sleep mode or module standby 20 3 7 Timer General Registers TGR The TGR registers are 16 bit registers The TPU has 16 TGR registers four each for channels 0 and 3 TGRC and TGRD can also be designated for operation...

Page 794: ...mode sleep mode or module standby 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R W R W R W R W Bit Initial value R W CST3 CST2 CST1 CST0 Bit Bit Name Initial Value R W Description 15 to 4 All 0 R Reserved These bits are always read as 0 and cannot be modified 3 2 1 0 CST3 CST2 CST1 CST0 0 0 0 0 R W R W R W R W Counter Start These bits select operati...

Page 795: ...ng from a buffer register rewriting on compare match occurrence or on counter clearing can be selected 3 PWM Mode In this mode a PWM waveform is output The output level can be set by means of TIOR A PWM waveform with a duty of between 0 and 100 can be output according to the setting of each TGR register 4 Phase Counting Mode In this mode TCNT is incremented or decremented by detecting the phases o...

Page 796: ...iod Start count Periodic counter 1 2 4 3 6 Free running counter Start count Free running counter 6 Set external pin function 5 1 2 3 4 5 6 Select output compare register Set external pin function 5 Select the counter clock with bits TPSC2 to TPSC0 in TCR At the same time select the input clock edge with bits CKEG1 and CKEG0 in TCR For periodic counter operation select the TGRA to be used as the TC...

Page 797: ...free running counter operation TCNT value H FFFF H 0000 CST bit TCFV Time Figure 20 3 Free Running Counter Operation When compare match is selected as the TCNT clearing source the TCNT counter for the relevant channel performs periodic count operation The TGR register for setting the period is designated as an output compare register and counter clearing by compare match is selected by means of bi...

Page 798: ...re match Figure 20 5 shows an example of the setting procedure for waveform output by compare match Select waveform output mode Output selection Set output timing Start count Waveform output 1 2 Set external pin function 3 4 1 Select initial value 0 output or 1 output and compare match output value 0 output 1 output or toggle output by means of TIOR The set initial value is output at the TPU_TO pi...

Page 799: ...l coincide the pin level does not change TCNT value H FFFF H 0000 TPU_TO pin 1 output TPU_TO pin 0 output Time TGRA No change No change No change No change Figure 20 6 Example of 0 Output 1 Output Operation Figure 20 7 shows an example of toggle output In this example TCNT has been designated as a periodic counter with counter clearing performed by compare match B and settings have been made so th...

Page 800: ...Timer General Register Buffer Register TGRA TGRC TGRB TGRD When a compare match occurs the value in the buffer register for the corresponding channel is transferred to the timer general register For update timing from a buffer register rewriting on compare match occurrence or on counter cleaning can be selected This operation is illustrated in figure 20 8 Buffer register Timer general register TCN...

Page 801: ...eration Buffer operation Set rewriting timing Start count Buffer operation 1 2 Set external pin function 3 4 1 Designate TGR for buffer operation with bits BFA and BFB in TMDR 2 Set rewriting timing from the buffer register with bit BFWT in TMDR 3 Set the external pin function in pin function controller PFC 4 Set the CST bit in TSTR to 1 to start the count operation Figure 20 9 Example of Buffer O...

Page 802: ... output at counter clearing Rewriting timing from the buffer register is set at counter clearing As buffer operation has been set when compare match A occurs the output changes When counter clearing occurs by TGRB the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA This operation is repeated each time compare match A occurs For deta...

Page 803: ... TPU_TO pin using TGRB as the period register and TGRA as duty registers The output specified in TIOR is performed by means of compare matches Upon counter clearing by a period register compare match the output value of each pin is the initial value set in TIOR Set TIOR so that the initial output and an output value by compare match are different If the same levels or toggle outputs are selected o...

Page 804: ...count 7 1 Select the counter clock with bits TPSC2 to TPSC0 in TCR At the same time select the input clock edge with bits CKEG1 and CKEG0 in TCR 2 Use bits CCLR2 to CCLR0 in TCR to select the TGRB to be used as the TCNT clearing source 3 Use TIOR to select the initial value and output value 4 Set the period in TGRB and set the duty in TGRA 5 Select the PWM mode with bits MD3 to MD0 in TMDR 6 Set t...

Page 805: ... and output value and 1 is set as the TGRA output value In this case the value set in TGRB is used as the period and the value set in TGRA as the duty TCNT value TGRB H 0000 TPU_TO pin Time TGRA Counter cleared by TGRB compare match Figure 20 12 Example of PWM Mode Operation 1 Figure 20 13 shows examples of PWM waveform output with 0 duty and 100 duty in PWM mode TCNT TGRA 1 TGRA 2 TGRA 3 Rewrite ...

Page 806: ...nd TGR are valid and compare match and interrupt functions can be used The previous set value initial output value set before the timer was started in phase counting mode is output from the TPU_TO pin in TIOR When overflow occurs while TCNT is counting up the TCFV flag in TSR is set when underflow occurs while TCNT is counting down the TCFU flag is set The TCFD bit in TSR is the count direction fl...

Page 807: ...e counting mode setting procedure Select phase counting mode Phase counting mode Start count Phase counting mode 1 Set external pin function 2 3 1 Select phase counting mode with bits MD3 to MD0 in TMDR 2 Set the external pin function in pin function controller PFC 3 Set the CST bit in TSTR to 1 to start the count operation Figure 20 14 Example of Phase Counting Mode Setting Procedure ...

Page 808: ...le of phase counting mode 1 operation and table 20 10 summarizes the TCNT up down count conditions TCNT value Time Down count Up count TPU_TI2A channel 2 TPU_TI3A channel 3 TPU_TI2B channels 2 TPU_TI3B channels 3 Figure 20 15 Example of Phase Counting Mode 1 Operation Table 20 10 Up Down Count Conditions in Phase Counting Mode 1 TPU_TI2A Channel 2 TPU_TI3A Channel 3 TPU_TI2B Channel 2 TPU_TI3B Cha...

Page 809: ...e Down count Up count TPU_TI2A Channel 2 TPU_TI3A Channel 3 TPU_TI2B Channel 2 TPU_TI3B Channel 3 Figure 20 16 Example of Phase Counting Mode 2 Operation Table 20 11 Up Down Count Conditions in Phase Counting Mode 2 TPU_TI2A Channel 2 TPU_TI3A Channel 3 TPU_TI2B Channel 2 TPU_TI3B Channel 3 Operation High level Don t care Low level Low level High level Up count High level Don t care Low level High...

Page 810: ...e Up count TPU_TI2A channel 2 TPU_TI3A channel 3 TPU_TI2B channel 2 TPU_TI3B channel 3 Down count Figure 20 17 Example of Phase Counting Mode 3 Operation Table 20 12 Up Down Count Conditions in Phase Counting Mode 3 TPU_TI2A Channel 2 TPU_TI3A Channel 3 TPU_TI2B Channel 2 TPU_TI3B Channel 3 Operation High level Don t care Low level Low level High level Up count High level Down count Low level Don ...

Page 811: ...channel 2 TPU_TI3A channel 3 TPU_TI2B channel 2 TPU_TI3B channel 3 Up count Down count TCNT value Figure 20 18 Example of Phase Counting Mode 4 Operation Table 20 13 Up Down Count Conditions in Phase Counting Mode 4 TPU_TI2A Channel 2 TPU_TI3A Channel 3 TPU_TI2B Channel 2 TPU_TI3B Channel 3 Operation High level Up count Low level Low level Don t care High level High level Down count Low level High...

Page 812: ...e TPU will not operate properly with a narrower pulse width In phase counting mode the phase difference and overlap between the two input clocks must be at least 2 states and the pulse width must be at least 3 states Figure 20 19 shows the input clock conditions in phase counting mode Overlap Phase differ ence Phase differ ence Overlap TPU_TCLKA TPU_TCLKC TPU_TCLKB TPU_TCLKD Pulse width Pulse widt...

Page 813: ...oad up counter All channels are provided with 32 bit constant registers and 32 bit up counters that can be written or read at any time Allows selection among three counter input clocks for channel 0 to channel 4 Peripheral clock Pck0 1 8 1 32 and 1 128 One shot operation and free running operation are selectable Allows selection of compare match or overflow for the interrupt source Generate a DMA ...

Page 814: ...MA transfer Internal interrupt DMA transfer CMSTR Pck0 CH0 CMT CMCNT_0 CMCOR_0 CMCSR_0 Interrupt control CH1 CMCNT_1 CMCOR_1 CMCSR_1 CH2 CMCNT_2 CMCOR_2 CMCSR_2 CH3 CMCNT_3 CMCOR_3 CMCSR_3 CH4 CMCNT_4 CMCOR_4 CMCSR_4 Peripheral bus Legend CMSTR CMCSR Compare match timer start register Compare match timer control status register CMCNT CMCOR Compare match timer counter Compare match timer constant r...

Page 815: ...0 0024 32 Compare match timer constant register_1 CMCOR_1 R W H FF20 0028 H 1F20 0028 32 Compare match timer control status register_2 CMCSR_2 R W H FFE2 0030 H 1FE2 0030 16 Compare match timer counter_2 CMCNT_2 R W H FF20 0034 H 1F20 0034 32 Compare match timer constant register_2 CMCOR_2 R W H FF20 0038 H 1F20 0038 32 Compare match timer control status register_3 CMCSR_3 R W H FFE2 0040 H 1FE2 0...

Page 816: ...0000 Retained Retained Compare match timer constant register_1 CMCOR_1 H FFFF FFFF H FFFF FFFF Retained Retained Compare match timer control status register_2 CMCSR_2 H 0000 H 0000 Retained Retained Compare match timer counter_2 CMCNT_2 H 0000 0000 H 0000 0000 Retained Retained Compare match timer constant register_2 CMCOR_2 H FFFF FFFF H FFFF FFFF Retained Retained Compare match timer control sta...

Page 817: ...2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R W R W R W R W R W Bit Initial value R W STR 4 0 Bit Bit Name Initial Value R W Description 15 to 5 All 0 R Reserved These bits are always read as 0 The write value should always be 0 4 to 0 STR 4 0 All 0 R W Count Start Selects whether to operate or halt the compare match timer counter for each channel CMCNT_4 to CMCNT_0 0 CMCNTn count ...

Page 818: ...0 CMR 1 0 Bit Bit Name Initial Value R W Description 15 CMF 0 R W 1 Compare Match Flag This flag indicates whether or not values of the compare match timer counter CMCNT and compare match timer constant register CMCOR have matched Software cannot write 1 to the bit When one shot is selected for the counter operation counting resumes by clearing this bit 0 CMCNT and CMCOR values have not matched Cl...

Page 819: ...es as a 32 bit counter 1 Operates as a 16 bit counter 8 CMM 0 R W Compare Match Mode Selects one shot operation or free running operation of the counter 0 One shot operation 1 Free running operation 7 6 All 0 R Reserved These bits are always read as 0 The write value should always be 0 5 4 CMR 1 0 00 R W Compare Match Request Selects enable or disable for a DMA transfer request or internal interru...

Page 820: ...fore set CMCSR first before starting a channel operation corresponding to the compare match timer start register CMSTR When the 16 bit counter operation is selected by the CMS bit bits 15 to 0 of this register become valid When the register should be written to write the data that is added H 0000 to the upper half in a 32 bit operation The contents of this register are initialized to H 00000000 21...

Page 821: ... in CMCSR is set to 1 Counting by CMCNT stops after it has been cleared To detect an overflow interrupt set the value in CMCOR to H FFFFFFFF When the value in CMCNT matches the value in CMCOR CMCNT is cleared to H 00000000 and bits CMF and OVF in CMCSR are set to 1 Value in CMCNT CMCOR CMF 1 OVF 1 When an overflow is detected H 00000000 Time Figure 21 2 Counter Operation One Shot Operation Free Ru...

Page 822: ... This is selected by the CMS bit in CMCSR When the 16 bit size is selected use a 32 bit value which has H 0000 as its upper half to set CMCOR To detect an overflow interrupt the value must be set to H 0000FFFF 21 3 3 Timing for Counting by CMCNT In this module the clock for the counter can be selected from among the following For channels 0 to 4 Peripheral clock Pck0 1 8 1 32 or 1 128 The clock fo...

Page 823: ... the value set in the DMAC and the output of the request then automatically stops To clear the interrupt request the CMF bit should be set to 0 Set the CMF bit to 0 in the handling routine for the CMT interrupt 21 3 5 Compare Match Flag Set Timing All Channels The CMF bit in CMCSR is set to 1 by the compare match signal generated when CMCOR and CMCNT match The compare match signal is generated upo...

Page 824: ...Section 21 Compare Match Timer CMT Rev 1 00 Oct 01 2007 Page 758 of 1956 REJ09B0256 0100 ...

Page 825: ...nary display The 64 Hz counter register indicates a state of 64 Hz to 1 Hz within the RTC frequency divider Start stop function 30 second adjustment function Alarm interrupts Comparison with second minute hour day of week day month or year can be selected as the alarm interrupt condition Periodic interrupts An interrupt period of 1 256 second 1 64 second 1 16 second 1 4 second 1 2 second 1 second ...

Page 826: ...84 kHz 32 768 kHz 128 kHz ATI PRI CUI RCR1 RCR2 RCR3 RYRCNT RYRAR RMONCNT RWKCNT RDAYCNT RHRCNT RMINCNT RSECCNT RSECAR RMINAR RHRAR RDAYAR RWKAR RMONAR Prescaler RTC crystal oscillator RTC operation control unit Counter unit Interr upt control unit To registers Bus interface Internal peripheral module bus RTC clock output Reset Figure 22 1 Block Diagram of RTC ...

Page 827: ...TC oscillator crystal pin EXTAL2 Input Connects crystal to RTC oscillator RTC oscillator crystal pin XTAL2 Output Connects crystal to RTC oscillator Dedicated RTC power supply Vdd RTC RTC oscillator power supply pin Dedicated RTC GND pin Vss RTC RTC oscillator GND pin RTC standby XRTCSTBI Input RTC standby Note Power must be supplied to the RTC power supply pins even when the RTC is not used ...

Page 828: ...NT R W H FFF8 0018 H 1FF8 0018 8 Year counter RYRCNT R W H FFF8 001C H 1FF8 001C 16 Second alarm register RSECAR R W H FFF8 0020 H 1FF8 0020 8 Minute alarm register RMINAR R W H FFF8 0024 H 1FF8 0024 8 Hour alarm register RHRAR R W H FFF8 0028 H 1FF8 0028 8 Day of week alarm register RWKAR R W H FFF8 002C H 1FF8 002C 8 Day alarm register RDAYAR R W H FFF8 0030 H 1FF8 0030 8 Month alarm register RM...

Page 829: ...Retained Retained Retained Minute alarm register RMINAR Undefined 1 Initialized 1 Retained Retained Retained Hour alarm register RHRAR Undefined 1 Initialized 1 Retained Retained Retained Day of week alarm register RWKAR Undefined 1 Initialized 1 Retained Retained Retained Day alarm register RDAYAR Undefined 1 Initialized 1 Retained Retained Retained Month alarm register RMONAR Undefined 1 Initial...

Page 830: ...o H 00 R64CNT is not initialized by a power on or manual reset Bit 7 is always read as 0 and cannot be modified 0 1 2 3 4 5 6 7 0 64 Hz 32 Hz 16 Hz 8 Hz 4 Hz 2 Hz 1 Hz R R R R R R R R Bit Initial value R W 22 4 2 Second Counter RSECCNT RSECCNT is an 8 bit readable writable register used as a counter for setting and counting the BCD coded second value in the RTC It counts on the carry transition of...

Page 831: ...alid but the write value should always be 0 0 1 2 3 4 5 6 7 0 1 minute units 10 minute units R W R W R W R W R W R W R W R Bit Initial value R W 22 4 4 Hour Counter RHRCNT RHRCNT is an 8 bit readable writable register used as a counter for setting and counting the BCD coded hour value in the RTC It counts on the carry generated once per hour by the minute counter The setting range is decimal 00 to...

Page 832: ...tting range is decimal 0 to 6 The RTC will not operate normally if any other value is set Write processing should be performed after stopping the count with the START bit in RCR2 or by using the carry flag RWKCNT is not initialized by a power on or manual reset Bits 7 to 3 are always read as 0 A write to these bits is invalid but the write value should always be 0 0 1 2 3 4 5 6 7 0 0 0 0 0 Day of ...

Page 833: ...performed after stopping the count with the START bit in RCR2 or by using the carry flag RDAYCNT is not initialized by a power on or manual reset The setting range for RDAYCNT depends on the month and whether the year is a leap year so care is required when making the setting Taking the year counter RYRCNT value as the year leap year calculation is performed according to whether or not the value i...

Page 834: ... bits is invalid but the write value should always be 0 0 1 2 3 4 5 6 7 0 10 month unit 0 0 1 month units R W R W R W R W R W R R R Bit Initial value R W 22 4 8 Year Counter RYRCNT RYRCNT is a 16 bit readable writable register used as a counter for setting and counting the BCD coded year value in the RTC It counts on the carry generated once per year by the month counter The setting range is decim...

Page 835: ...ialized by a power on or manual reset 0 1 2 3 4 5 6 7 0 1 second units 10 second units ENB R W R W R W R W R W R W R W R W Bit Initial value R W 22 4 10 Minute Alarm Register RMINAR RMINAR is an 8 bit readable writable register used as an alarm register for the RTC s BCD coded minute value counter RMINCNT When the ENB bit is set to 1 the RMINAR value is compared with the RMINCNT value Comparison b...

Page 836: ...ialized by a power on or manual reset Bit 6 is always read as 0 A write to this bit is invalid but the write value should always be 0 0 1 2 3 4 5 6 7 0 0 1 hour units 10 hour units ENB R W R W R W R W R W R W R R W Bit Initial value R W 22 4 12 Day of Week Alarm Register RWKAR RWKAR is an 8 bit readable writable register used as an alarm register for the RTC s BCD coded day of week value counter R...

Page 837: ...ison between the counter and the alarm register is performed for those registers among RSECAR RMINAR RHRAR RWKAR RDAYAR and RMONAR in which the ENB bit is set to 1 and the RCR1 alarm flag is set when the respective values all match The setting range is decimal 01 to 31 ENB bit The RTC will not operate normally if any other value is set The setting range for RDAYAR depends on the month and whether ...

Page 838: ... 12 ENB bit The RTC will not operate normally if any other value is set The ENB bit in RMONAR is initialized by a power on reset The other fields in RMONAR are not initialized by a power on or manual reset Bits 6 and 5 are always read as 0 A write to these bits is invalid but the write value should always be 0 0 1 2 3 4 5 6 7 0 10 month unit 0 0 1 month units ENB R W R W R W R W R W R R R W Bit In...

Page 839: ...r a 64 Hz counter carry when the 64 Hz counter is read When 1 is written to CF 6 to 5 Undefined R Reserved The initial value of these bits is undefined A write to these bits is invalid but the write value should always be 0 4 CIE 0 R W Carry Interrupt Enable Flag Enables or disables interrupt generation when the carry flag CF is set to 1 0 Carry interrupt is not generated when CF flag is set to 1 ...

Page 840: ...larm registers in which the ENB bit is set to 1 and counter values match Note Writing 1 does not change the value 22 4 16 RTC Control Register 2 RCR2 RCR2 is an 8 bit readable writable register used for periodic interrupt control 30 second adjustment and frequency divider RESET and RTC count control RCR2 is basically initialized to H 09 by a power on reset except that the value of the PEF bit is u...

Page 841: ...fied by bits PES2 PES0 When 1 is written to PEF 6 to 4 PES 2 0 All 0 R W Periodic Interrupt Enable These bits specify the period for periodic interrupts 000 No periodic interrupt generation 001 Periodic interrupt generated at 1 256 second intervals 010 Periodic interrupt generated at 1 64 second intervals 011 Periodic interrupt generated at 1 16 second intervals 100 Periodic interrupt generated at...

Page 842: ...1 30 second adjustment performed 1 RESET 0 R W Reset The frequency divider circuits are initialized by writing 1 to this bit When 1 is written to the RESET bit the frequency divider circuits RTC prescaler and R64CNT are reset and the RESET bit is automatically cleared to 0 i e does not need to be written with 0 0 Normal clock operation 1 Frequency divider circuits are reset 0 START 1 R W Start Bit...

Page 843: ...t to 1 The alarm flag of RCR1 is only set to 1 when the respective values all match The setting range of RYRAR is decimal 0000 to 9999 and normal operation is not obtained if a value beyond this range is set here RCR3 is initialized by a power on reset but RYRAR will not be initialized by a power on or manual reset Bits 6 to 0 of RCR3 are always read as 0 A write to these bits is invalid If a valu...

Page 844: ...lear carry flag Write to counter register Carry flag 1 No Yes Figure 22 2 Examples of Time Setting Procedures The procedure for setting the time after stopping the clock is shown in figure 22 2 a The programming for this method is simple and it is useful for setting all the counters from second to year The procedure for setting the time while the clock is running is shown in figure 22 2 b This met...

Page 845: ...to 0 Read RCR1 register and check CF bit Clear carry flag Read counter register Disable carry interrupts Clear carry flag Enable carry interrupts Interrupt generated No Yes Clear carry flag Disable carry interrupts Read counter register Carry flag 1 No Yes Figure 22 3 Examples of Time Reading Procedures If a carry occurs while the time is being read the correct time will not be obtained and the re...

Page 846: ...ting Set RCR1 AIE to 1 Figure 22 4 Example of Use of Alarm Function An alarm can be generated by the second minute hour day of week day month or year value or a combination of these Write 1 to the ENB bit in the alarm registers involved in the alarm setting and set the alarm time in the lower bits Write 0 to the ENB bit in registers not involved in the alarm setting When the counter and the alarm ...

Page 847: ...and the periodic interrupt flag PEF is set to 1 A carry interrupt request CUI is generated when the carry flag CF in RCR1 is set to 1 while the carry interrupt enable bit CIE is also set to 1 22 7 Usage Notes 22 7 1 Register Initialization After powering on and making the RCR1 register settings reset the frequency divider by setting RCR2 RESET to 1 and make initial settings for all the other regis...

Page 848: ...itors Cin and Cout as close as possible to the chip Correct oscillation may not be possible if there is externally induced noise in the EXTAL2 and XTAL2 pins 6 Ensure that the crystal resonator connection pin EXTAL2 and XTAL2 wiring is routed as far away as possible from other power lines except GND and signal lines 7 Insert a noise filter in the RTC power supply CRTC RRTC 3 3 V VDD RTC VSS RTC Th...

Page 849: ...has an on chip TSU Transfer Switching Unit which controls transferring allowing mutual transfer of data between MAC layer controllers of ports 0 and 1 23 1 Features MAC Media Access Control function Constructs deconstructs data frames frame format conforming to IEEE802 3 2000 Edition Supports transfer at 10 100 and 1000 Mbps Supports full duplex and half duplex modes Two channels GETHER0 and GETHE...

Page 850: ... Relay FIFO Port 0 Port 1 Relay FIFO Port 0 Port 1 CAM entry tables Receive FIFO Port 1 Receive FIFO Port 0 Transmit FIFO Port 1 DMA tansfer processing Descriptor access Transmit FIFO Port 0 DMA transfer processing Descriptor access GETHER E DMAC1 E DMAC0 TSU E MAC 0 Port 0 E MAC 1 Port 1 GMII MII RMII conversion GMII MII RMII conversion Receive processing unit Transmit processing unit Transmit pr...

Page 851: ...Input Collision detection signal Transmit error ET0_TX ER Output Notifies PHY LSI of error during transmission Receive clock ET0_RX CLK Input ET0_RX DV ET0_ERXD3 to ET0_ERXD0 ET0_RX ER timing reference signal Receive data valid ET0_RX DV Input Indicates that valid receive data is on ET0_ERXD3 to ET0_ERXD0 MII GMII receive data ET0_ERXD3 to ET0_ERXD0 Input 4 bit MII receive data or lower four bits ...

Page 852: ...e clock signal for information transfer via RMII0M1_MDIO in RMII mode mirror 1 pin RMII management data I O mirror 1 pin RMII0M1_MDIO I O Bidirectional signal for exchange of management information between STA and PHY in RMII mode mirror 1 pin Link status ET0_LINKSTA Input Inputs link status from PHY LSI Wake On LAN ET0_WOL Output Signal indicating reception of Magic Packet PHY interrupt ET0_PHY I...

Page 853: ...r bits of GMII transmit data Transmit error ET1_TX ER Output Notifies PHY LSI of error during transmission Receive data valid ET1_RX DV Input Indicates that valid receive data is on ET1_ERXD3 to ET1_ERXD0 MII GMII receive data ET1_ERXD3 to ET1_ERXD0 Input 4 bit MII receive data or lower four bits of GMII receive data MII and GMII GMII receive data GET1_ERXD7 to GET1_ERXD4 Input Upper four bits of ...

Page 854: ...eceive data RMII1_RXD0 Input 2 bit receive data in RMII mode RMII receive data RMII1_RXD1 Input 2 bit receive data in RMII mode RMII transmit enable RMII1_TXD_EN Output Indicates that transmit data is ready on RMII1_TXD0 and RMII1_TXD1 in RMII mode RMII transmit data RMII1_TXD0 Output 2 bit transmit data in RMII mode RMII transmit data RMII1_TXD1 Output 2 bit transmit data in RMII mode RMII carrie...

Page 855: ...1M_TXD0 Output 2 bit transmit data in RMII mode mirror pin RMII transmit data mirror pin RMII1_TXD1 Output 2 bit transmit data in RMII mode mirror pin 125 MHz reference clock Common REF125CK Input Transmit clock generation signal in GMII mode 50 MHz reference clock Common REF50CK Input Transmit clock generation signal in RMII mode Note MII signal conforming to IEEE802 3u ...

Page 856: ...egister PIR0 R W H FEE0 0520 H 1EE0 0520 32 MAC address high register MAHR0 R W H FEE0 05C0 H 1EE0 05C0 32 MAC address low register MALR0 R W H FEE0 05C8 H 1EE0 05C8 32 Receive frame length register RFLR0 R W H FEE0 0508 H 1EE0 0508 32 PHY status register PSR0 R H FEE0 0528 H 1EE0 0528 32 PHY_INT polarity register PIPR0 R W H FEE0 052C H 1EE0 052C 32 Transmit retry over counter register TROCR0 R W...

Page 857: ... H FEE0 0D00 H 1EE0 0D00 32 E MAC status register ECSR1 R W H FEE0 0D10 H 1EE0 0D10 32 E MAC interrupt permission register ECSIPR1 R W H FEE0 0D18 H 1EE0 0D18 32 PHY interface register PIR1 R W H FEE0 0D20 H 1EE0 0D20 32 PHY_INT polarity register PIPR1 R W H FEE0 0D2C H 1EE0 0D2C 32 MAC address high register MAHR1 R W H FEE0 0DC0 H 1EE0 0DC0 32 MAC address low register MALR1 R W H FEE0 0DC8 H 1EE0...

Page 858: ...register PFRCR1 R H FEE0 0D60 H 1EE0 0D60 32 GETHER mode register GECMR1 R W H FEE0 0DB0 H 1EE0 0DB0 32 Burst cycle count upper limit register BCULR1 R W H FEE0 0DB4 H 1EE0 0DB4 32 TSU counter reset register TSU_CTRST R W H FEE0 1804 H 1EE0 1804 32 Relay enable register Port 0 to 1 TSU_FWEN0 R W H FEE0 1810 H 1EE0 1810 32 Relay enable register Port 1 to 0 TSU_FWEN1 R W H FEE0 1814 H 1EE0 1814 32 R...

Page 859: ...1864 32 CAM entry table POST1 register TSU_POST1 R W H FEE0 1870 H 1EE0 1870 32 CAM entry table POST2 register TSU_POST2 R W H FEE0 1874 H 1EE0 1874 32 CAM entry table POST3 register TSU_POST3 R W H FEE0 1878 H 1EE0 1878 32 CAM entry table POST4 register TSU_POST4 R W H FEE0 187C H 1EE0 187C 32 CAM entry table 0H register TSU_ADRH0 R W H FEE0 1900 H 1EE0 1900 32 CAM entry table 1H register TSU_ADR...

Page 860: ... H 1EE0 19C8 32 CAM entry table 26H register TSU_ADRH26 R W H FEE0 19D0 H 1EE0 19D0 32 CAM entry table 27H register TSU_ADRH27 R W H FEE0 19D8 H 1EE0 19D8 32 CAM entry table 28H register TSU_ADRH28 R W H FEE0 19E0 H 1EE0 19E0 32 CAM entry table 29H register TSU_ADRH29 R W H FEE0 19E8 H 1EE0 19E8 32 CAM entry table 30H register TSU_ADRH30 R W H FEE0 19F0 H 1EE0 19F0 32 CAM entry table 31H register ...

Page 861: ...BC H 1EE0 19BC 32 CAM entry table 24L register TSU_ADRL24 R W H FEE0 19C4 H 1EE0 19C4 32 CAM entry table 25L register TSU_ADRL25 R W H FEE0 19CC H 1EE0 19CC 32 CAM entry table 26L register TSU_ADRL26 R W H FEE0 19D4 H 1EE0 19D4 32 CAM entry table 27L register TSU_ADRL27 R W H FEE0 19DC H 1EE0 19DC 32 CAM entry table 28L register TSU_ADRL28 R W H FEE0 19E4 H 1EE0 19E4 32 CAM entry table 29L registe...

Page 862: ...MAC mode register EDMR0 R W H FEE0 0400 H 1EE0 0400 32 E DMAC transmit request register EDTRR0 R W H FEE0 0408 H 1EE0 0408 32 E DMAC receive request register EDRRR0 R W H FEE0 0410 H 1EE0 0410 32 Transmit descriptor list start address register TDLAR0 R W H FEE0 0010 H 1EE0 0010 32 Receive descriptor list start address register RDLAR0 R W H FEE0 0030 H 1EE0 0030 32 E MAC E DMAC status register EESR...

Page 863: ...egister EDRRR1 R W H FEE0 0C10 H 1EE0 0C10 32 Transmit descriptor list start address register TDLAR1 R W H FEE0 0810 H 1EE0 0810 32 Receive descriptor list start address register RDLAR1 R W H FEE0 0830 H 1EE0 0830 32 E MAC E DMAC status register EESR1 R W H FEE0 0C28 H 1EE0 0C28 32 E MAC E DMAC status interrupt permission register EESIPR1 R W H FEE0 0C30 H 1EE0 0C30 32 Transmit receive status copy...

Page 864: ... low register MALR0 H 00000000 H 00000000 Retained Retained Receive frame length register RFLR0 H 00000000 H 00000000 Retained Retained PHY status register PSR0 H 00000000 H 00000000 Retained Retained PHY_INT polarity register PIPR0 H 00000000 H 00000000 Retained Retained Transmit retry over counter register TROCR0 H 00000000 H 00000000 Retained Retained Delayed collision detect counter register C...

Page 865: ...00 Retained Retained MAC address low register MALR1 H 00000000 H 00000000 Retained Retained Receive frame length register RFLR1 H 00000000 H 00000000 Retained Retained PHY status register PSR1 H 00000000 H 00000000 Retained Retained Transmit retry over counter register TROCR1 H 00000000 H 00000000 Retained Retained Delayed collision detect counter register CDCR1 H 00000000 H 00000000 Retained Reta...

Page 866: ... port 1 TSU_BSYSL1 H 0000003F H 0000003F Retained Retained Transmit relay priority control mode register port 0 TSU_PRISL0 H 00000000 H 00000000 Retained Retained Transmit relay priority control mode register port 1 TSU_PRISL1 H 00000000 H 00000000 Retained Retained Receive relay function set register port 0 to 1 TSU_FWSL0 H 00000000 H 00000000 Retained Retained Receive relay function set register...

Page 867: ...0000 Retained Retained CAM entry table 4H register TSU_ADRH4 H 00000000 H 00000000 Retained Retained CAM entry table 5H register TSU_ADRH5 H 00000000 H 00000000 Retained Retained CAM entry table 6H register TSU_ADRH6 H 00000000 H 00000000 Retained Retained CAM entry table 7H register TSU_ADRH7 H 00000000 H 00000000 Retained Retained CAM entry table 8H register TSU_ADRH8 H 00000000 H 00000000 Retai...

Page 868: ...able 26H register TSU_ ADRH26 H 00000000 H 00000000 Retained Retained CAM entry table 27H register TSU_ ADRH27 H 00000000 H 00000000 Retained Retained CAM entry table 28H register TSU_ ADRH28 H 00000000 H 00000000 Retained Retained CAM entry table 29H register TSU_ ADRH29 H 00000000 H 00000000 Retained Retained CAM entry table 30H register TSU_ ADRH30 H 00000000 H 00000000 Retained Retained CAM en...

Page 869: ...er TSU_ ADRL13 H 00000000 H 00000000 Retained Retained CAM entry table 14L register TSU_ ADRL14 H 00000000 H 00000000 Retained Retained CAM entry table 15L register TSU_ ADRL15 H 00000000 H 00000000 Retained Retained CAM entry table 16L register TSU_ ADRL16 H 00000000 H 00000000 Retained Retained CAM entry table 17L register TSU_ ADRL17 H 00000000 H 00000000 Retained Retained CAM entry table 18L r...

Page 870: ...TXNLCR0 H 00000000 H 00000000 Retained Retained Transmit frame counter register port 0 normal and erroneous transmission TXALCR0 H 00000000 H 00000000 Retained Retained Receive frame counter register port 0 normal reception only RXNLCR0 H 00000000 H 00000000 Retained Retained Receive frame counter register port 0 normal and erroneous reception RXALCR0 H 00000000 H 00000000 Retained Retained Relay ...

Page 871: ...ansmit receive status copy enable register TRSCER0 H 00000000 H 00000000 Retained Retained Receive missed frame counter register RMFCR0 H 00000000 H 00000000 Retained Retained Transmit FIFO threshold register TFTR0 H 00000000 H 00000000 Retained Retained FIFO depth register FDR0 H 00000000 H 00000000 Retained Retained Receiving method control register RMCR0 H 00000000 H 00000000 Retained Retained ...

Page 872: ... counter register RMFCR1 H 00000000 H 00000000 Retained Retained Transmit FIFO threshold register TFTR1 H 00000000 H 00000000 Retained Retained FIFO depth register FDR1 H 00000000 H 00000000 Retained Retained Receiving method control register RMCR1 H 00000000 H 00000000 Retained Retained Receive descriptor fetch address register RDFAR1 H 00000000 H 00000000 Retained Retained Receive descriptor fin...

Page 873: ...Name Initial Value R W Description 31 to 1 All 0 R Reserved These bits are always read as 0 The write value should always be 0 0 ARST 0 R W Software Reset When 1 is written to this bit a software reset is issued to all blocks of the GETHER for 256 cycles of external bus clock Bck Writing 0 does not affect this bit This bit is always read as 0 While a software reset is issued register access to all...

Page 874: ... 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R W R R R W R R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R W R R R R W R R R W R W R R W R R W R W RCSC DPAD RZPF ZPF PFR RXF TXF MCT MPDE RE TE TRCCM ILB DM PRM Bit Bit Name Initial Value R W Description 31 to 27 All 0 R Reserv...

Page 875: ...y calculated Note that the checksum calculation of a frame with a VLAN tag is not supported 22 0 R Reserved This bit is always read as 0 The write value should always be 0 21 DPAD 0 R W Data Padding 0 Padding is inserted to data less than 60 bytes so it is transmitted as 60 byte data 1 Padding is not inserted to data less than 60 bytes and it is transmitted without changes 20 RZPF 0 R W PAUSE Fram...

Page 876: ...he time specified by the Timer value elapses an automatic PAUSE frame with a Timer value of 0 is transmitted On receiving a PAUSE frame with a Timer value of 0 the transmission wait state is canceled Lost carrier Error Detection Enable In half duplex mode 0 A lost carrier error is checked during frame transmission 1 A lost carrier error is not checked during frame transmission Lost carrier error d...

Page 877: ...ays read as 0 The write value should always be 0 13 MCT 0 R W Multicast Address Frame Receive Mode 0 Frames other than the multicast address set by the CAM entry table 0 to 31 H L registers are received However if the on chip CAM entry table reference is disabled all multicast address frames are received 1 Only the multicast address set by the CAM entry table 0 to 31 H L registers is received 12 t...

Page 878: ...abled TE 1 to disabled TE 0 while a frame is being transmitted the transmitting function will be enabled until transmission of the corresponding frame is completed 0 Transmitting function is disabled 1 Transmitting function is enabled 4 0 R Reserved This bit is always read as 0 The write value should always be 0 3 ILB 0 R W Internal Loop Back Mode Specifies loopback mode in the GETHER 0 Normal dat...

Page 879: ...et frames to be received All Ethernet frames means all receivable frames irrespective of differences or enabled disabled status destination address broadcast address multicast bit etc 0 GETHER performs normal operation 1 GETHER performs promiscuous mode operation Note All bits except for TE and RE should be changed while the transmitting function is disabled TE 0 and the receiving function is disa...

Page 880: ...of the E DMAC0 for port 0 and the E DMAC1 for port 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R W R R W R W R W PFROI PHYI LCHNG MPD ICD Bit Bit Name Initial Value R W Description 31 to 5 All 0...

Page 881: ...IO To check the current Link state refer to the LMON bit in the PHY status register PSR 0 Change in the ET_LNKSTA signal has not been detected 1 Change in the ET_LNKSTA signal has been detected high to low or low to high 1 MPD 0 R W Magic Packet Detection Indicates that a Magic Packet has been detected on the line 0 Magic Packet has not been detected 1 Magic Packet has been detected 0 ICD 0 R W Il...

Page 882: ...tion 31 to 5 All 0 R Reserved These bits are always read as 0 The write value should always be 0 4 PFROIP 0 R W PAUSE Frame Retransmit Interrupt Enable 0 Interrupt notification by the PFROI bit is disabled 1 Interrupt notification by the PFROI bit is enabled 3 PHYIP 0 R W ET_PHY INT Pin Interrupt Enable 0 Interrupt notification by the PHYI bit is disabled 1 Interrupt notification by the PHYI bit i...

Page 883: ...Value R W Description 31 to 4 All 0 R Reserved These bits are always read as 0 The write value should always be 0 3 MDI Undefined R GMII MII RMII Management Data In Indicates the level of the ET_MDIO pin 2 MDO 0 R W GMII MII RMII Management Data Out Outputs the value set in this bit from the ET_MDIO pin when the MMD bit is 1 1 MMD 0 R W GMII MII RMII Management Mode Specifies the data read write d...

Page 884: ...r initial states by means of the SWRT and SWRR bits in EDMR before making settings again 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R...

Page 885: ... of the SWRT and SWRR bits in EDMR before making settings again 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W MA 15 0 Bit Bit Name Initial Value R W Descrip...

Page 886: ... R W R W R W R W R W R W R W R W R W R W R W R W R W R W RFL 17 16 RFL 15 0 Bit Bit Name Initial Value R W Description 31 to 18 All 0 R Reserved These bits are always read as 0 The write value should always be 0 17 to 0 RFL 17 0 All 0 R W Receive Frame Length The frame data described here refers to all fields from the destination address up to the CRC data Frame contents from the destination addre...

Page 887: ... 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R LMON Bit Bit Name Initial Value R W Description 31 to 1 All 0 R Reserved These bits are always read as 0 The write value should always be 0 0 LMON 0 R ET_LNKSTA Pin Status The Link status can be read by connecting the Link signal output from...

Page 888: ...W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R W PHYIP Bit Bit Name Initial Value R W Description 31 to 1 All 0 R Reserved These bits are always read as 0 The write value should always be 0 0 PHYIP 0 R W ET_PHY INT Input Pin Polarity 0 ET_PHY INT pin is low active enters the interrupt state at low 1 ET_PHY INT pin i...

Page 889: ...ECMR set to 1 When the TRCCM bit in ECMR is 0 this register is cleared to 0 by writing H 11111111 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W TROC 15 0 Bi...

Page 890: ...M bit in ECMR is 0 this register is cleared to 0 by writing H 11111111 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W COSDC 15 0 Bit Bit Name Initial Value R...

Page 891: ...MR is 0 this register is cleared to 0 by writing H 11111111 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W LCC 15 0 Bit Bit Name Initial Value R W Descriptio...

Page 892: ...CCM bit in ECMR is 0 this register is cleared to 0 by writing H 11111111 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W CEFC 15 0 Bit Bit Name Initial Value ...

Page 893: ...d with the TRCCM bit in ECMR set to 1 When the TRCCM bit in ECMR is 0 this register is cleared to 0 by writing H 11111111 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W ...

Page 894: ...MR is 0 this register is cleared to 0 by writing H 11111111 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W TSFC 15 0 Bit Bit Name Initial Value R W Descripti...

Page 895: ...egister RFCR This register is cleared to 0 when it is read with the TRCCM bit in ECMR set to 1 When the TRCCM bit in ECMR is 0 this register is cleared to 0 by writing H 11111111 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 896: ...CM bit in ECMR is 0 this register is cleared to 0 by writing H 11111111 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W RFC 15 0 Bit Bit Name Initial Value R ...

Page 897: ... this register is cleared to 0 by writing H 11111111 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W CERC 15 0 Bit Bit Name Initial Value R W Description 31 t...

Page 898: ...MR is 0 this register is cleared to 0 by writing H 11111111 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W CEEC 15 0 Bit Bit Name Initial Value R W Descripti...

Page 899: ...e TRCCM bit in ECMR is 0 this register is cleared to 0 by writing H 11111111 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W MAFC 15 0 Bit Bit Name Initial Va...

Page 900: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W AP 15 0 Bit Bit Name Initial Value R W Description 31 to 16 All 0 R Reserved These bits are always read as 0 The write value should always be 0 15 to 0 AP 15 0 All 0 R W Automatic PAUSE These bits set the TIME parameter value of an automatic PAUSE frame One bit is equivalent to 512 bit time When flow contro...

Page 901: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W MP 15 0 Bit Bit Name Initial Value R W Description 31 to 16 All 0 R Reserved These bits are always read as 0 The write value should always be 0 15 to 0 MP 15 0 All 0 R W Manual PAUSE These bits set the TIME parameter value of a manual PAUSE fra...

Page 902: ...21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W TPAUSE 15 0 Bit Bit Name Initial Value R W Description 31 to 16 All 0 R Reserved These bits are always read as 0 The write value should alwa...

Page 903: ...0 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R PFTXC 15 0 Bit Bit Name Initial Value R W Description 31 to 16 All 0 R Reserved These bits are always read as 0 The write value should always be 0 15 to 0 PFTXC 15 0 All 0 R PA...

Page 904: ... 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R PFRXC 15 0 Bit Bit Name Initial Value R W Description 31 to 16 All 0 R Reserved These bits are always read as 0 The write value should always be 0 15 to 0 PFRXC 15 0 All 0 R PAUSE Frame ...

Page 905: ...R W SPEED 0 SPEED 1 BSE Bit Bit Name Initial Value R W Description 31 to 3 All 0 R Reserved These bits are always read as 0 The write value should always be 0 2 SPEED 1 0 R W Transfer Speed Sets the transfer speed in combination with the SPEED 0 bit Refer to the SPEED 0 bit 1 BSE 0 R W Burst Transfer Enable 0 Burst transfer is not performed 1 Burst transfer is performed when the transfer speed is ...

Page 906: ...STLMT 11 0 Bit Bit Name Initial Value R W Description 31 to 12 All 0 R Reserved These bits are always read as 0 The write value should always be 0 11 to 0 BSTLMT 11 0 All 0 R W Burst Cycle Upper Limit These bits set the upper limit for burst cycles Burst transfer is finished when the burst timer exceeds the value set in this register If the burst timer exceeds the value set in this register while ...

Page 907: ...R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R W R R R R R R R R CTRST Bit Bit Name Initial Value R W Description 31 to 9 All 0 R Reserved These bits are always read as 0 The write value should always be 0 8 CTRST 0 R W TSU Counter Reset When 1 is written to this bit the values of registers TXNLCR0 TXNLCR1 TXALCR0 TXALCR1 RXNLCR0 RXNLCR1 RXALCR0 RXALCR1 FWNLCR0 FWNLCR1 and F...

Page 908: ... 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R FWEN0 Bit Bit Name Initial Value R W Description 31 FWEN0 0 R W Port 0 to 1 Relay Operation Enable 0 Port 0 to 1 relay is disabled 1 Port 0 to 1 relay is enabled When the value of bits FCM 2 0 in the relay FIFO size select register T...

Page 909: ... 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R FWEN1 Bit Bit Name Initial Value R W Description 31 FWEN1 0 R W Port 1 to 0 Relay Operation Enable 0 Port 1 to 0 relay is disabled 1 Port 1 to 0 relay is enabled When the value of bits FCM 2 0 in the relay FIFO size select register T...

Page 910: ...l 0 R Reserved These bits are always read as 0 The write value should always be 0 2 to 0 FCM 2 0 All 0 R W Relay FIFO Size H 0 Port 0 to 1 3 Kbytes Port 1 to 0 3 Kbytes H 1 Port 0 to 1 4 Kbytes Port 1 to 0 2 Kbytes H 2 Port 0 to 1 5 Kbytes Port 1 to 0 1 Kbyte H 3 Port 0 to 1 6 Kbytes Port 1 to 0 Not used H 4 Port 0 to 1 Not used Port 1 to 0 6 Kbytes H 5 Port 0 to 1 1 Kbyte Port 1 to 0 5 Kbytes H 6...

Page 911: ...eshold TSU_BSYSL0 sets the threshold of the relay FIFO when the TSU alerts the E MAC 0 that writing in the relay FIFO will be disabled during relay operations 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 R R R R R R R R...

Page 912: ...AC 0 that writing in the relay FIFO will be disabled Thereafter alerting will be stopped when the data volume written in the relay FIFO becomes 16 bytes smaller than this threshold When H 00 is set the TSU always alerts the E MAC 0 that writing to the relay FIFO will be disabled When the value set is equal to or higher than the port 0 to 1 relay FIFO size set by bits FCM 2 0 in TSU_FCM the TSU doe...

Page 913: ...eshold TSU_BSYSL1 sets the threshold of the relay FIFO when the TSU alerts the E MAC 1 that writing in the relay FIFO will be disabled during relay operations 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 R R R R R R R R...

Page 914: ... 1 that writing in the relay FIFO will be disabled Thereafter alerting will be stopped when the data volume written in the relay FIFO becomes 16 bytes smaller than this threshold When H 00 is set the TSU always alerts the E MAC 1 that writing to the relay FIFO will be disabled When the value set is equal to or higher than the port 1 to 0 relay FIFO size set by bits FCM 2 0 in TSU_FCM the TSU does ...

Page 915: ... 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R W R W R W R R R R R W R W R W R W R W R W R W R W PRIMD0 2 0 PRISL0 7 0 Bit Bit Name Initial Value R W Description 31 to 15 All 0 R Reserved These bits are always read as 0 The write value should always be 0 14 to 12 PRIMD0 2 0 All 0 R W These bits set the priority control mode of E MAC 0 transmission and port 1...

Page 916: ...f switching to relay priority when bits PRIMD0 2 0 are set to H 4 or H 5 H 00 0 byte H 01 64 bytes H 02 128 bytes H 5E 6 016 bytes H 5F 6 080 bytes Settings are disabled for H 60 to H FF When H 00 is set in these bits relay always takes priority When the value set is equal to or above the port 1 to 0 relay FIFO size set by bits FCM 2 0 in TSU_FCM if bits PRIMD0 2 0 are H 4 round robin will always ...

Page 917: ... 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R W R W R W R R R R R W R W R W R W R W R W R W R W PRIMD1 2 0 PRISL1 7 0 Bit Bit Name Initial Value R W Description 31 to 15 All 0 R Reserved These bits are always read as 0 The write value should always be 0 14 to 12 PRIMD1 2 0 All 0 R W These bits set the priority control mode of E MAC 1 transmission and port 0...

Page 918: ...f switching to relay priority when bits PRIMD1 2 0 are set to H 4 or H 5 H 00 0 byte H 01 64 bytes H 02 128 bytes H 5E 6 016 bytes H 5F 6 080 bytes Settings are disabled for H 60 to H FF When H 00 is set in these bits relay always takes priority When the value set is equal to or above the port 0 to 1 relay FIFO size set by bits FCM 2 0 in TSU_FCM if bits PRIMD1 2 0 are H 4 round robin will always ...

Page 919: ...s set to 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R W R W R W R W R W R R R R W R R R R FW50 FW40 FW30 FW20 FW10 RMSA0 Bit Bit Name Initial Value R W Description 31 to 13 All 0 R Reserved These bits are alwa...

Page 920: ...ishit Frames are not relayed 1 CAM hit Frames are not relayed CAM mishit Frames are relayed to port 1 7 to 5 All 0 R Reserved These bits are always read as 0 The write value should always be 0 4 RMSA0 0 R W Sets the processing method when the SA source address of a frame received from port 0 is not registered in the entry table 0 Frame is not received 1 Frame is received However a frame discarded ...

Page 921: ...s set to 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R W R W R W R W R W R R R R W R R R R FW51 FW41 FW31 FW21 FW11 RMSA1 Bit Bit Name Initial Value R W Description 31 to 13 All 0 R Reserved These bits are alwa...

Page 922: ...ishit Frames are not relayed 1 CAM hit Frames are not relayed CAM mishit Frames are relayed to port 0 7 to 5 All 0 R Reserved These bits are always read as 0 The write value should always be 0 4 RMSA1 0 R W Sets the processing method when the SA source address of a frame received from port 1 is not registered in the entry table 0 Frame is not received 1 Frame is received However a frame discarded ...

Page 923: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R W R W R R R R R R R R R R R R POST ENL POST ENU Bit Bit Name Initial Value R W Description 31 to 14 All 0 R Reserved These bits are always read as 0 The write value should always be 0 13 POSTENU 0 R W Enables the settings of the POST field of CAM entry tables 0 to 15 settings by the TSU_POST1 and TSU_POST2 registers 0 Disables the settings of the POST field The CA...

Page 924: ...it Ethernet Controller GETHER Rev 1 00 Oct 01 2007 Page 858 of 1956 REJ09B0256 0100 Bit Bit Name Initial Value R W Description 11 to 0 All 0 R Reserved These bits are always read as 0 The write value should always be 0 ...

Page 925: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R W R W R W QTAG0 2 0 Bit Bit Name Initial Value R W Description 31 to 3 All 0 R Reserved These bits are always read as 0 The write value should always be 0 2 to 0 QTAG0 2 0 All 0 R W These bits set Qtag adding and deleting functions during port 0 to 1 relay operations H 0 Disab...

Page 926: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R W R W R W QTAG1 2 0 Bit Bit Name Initial Value R W Description 31 to 3 All 0 R Reserved These bits are always read as 0 The write value should always be 0 2 to 0 QTAG1 2 0 All 0 R W These bits set Qtag adding and deleting functions during port 1 to 0 relay operations H 0 Disab...

Page 927: ...ring relay operations the corresponding relay frame is discarded 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R W R W R W R W R W R W R W R W OVF0 RBSY 0 RINT 60 RINT 61 RINT 10 RINT 20 R...

Page 928: ...om the PHY LSI in the E MAC 0 16 RINT10 0 R W E MAC 0 CRC Error Frame Receive Set to 1 when a receive frame results in a CRC error in the E MAC 0 15 to 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7 OVF1 0 R W Port 1 to 0 Relay FIFO Overflow Detect Set to 1 when the port 1 to 0 relay FIFO overflows 6 RBSY1 0 R W E MAC 1 Overflow Alert Signal Output Set to 1...

Page 929: ...Too Short Frame Receive Set to 1 when a frame with a length of less than 64 bytes is received in the E MAC 1 1 RINT21 0 R W E MAC 1 Frame Receive Error Set to 1 when a receive error is detected on the ET1_RX ER pin input from the PHY LSI in the E MAC 1 0 RINT11 0 R W E MAC 1 CRC Error Frame Receive Set to 1 when a receive frame results in a CRC error in the E MAC 1 ...

Page 930: ... 10 RINTM 20 RINTM 30 RINTM 40 RINTM 50 RINTM 11 RINTM 21 RINTM 31 RINTM 41 RINTM 51 OVFM 1 RBSYM 1 Bit Bit Name Initial Value R W Description 31 to 24 All 0 R Reserved These bits are always read as 0 The write value should always be 0 23 OVFM0 0 R W Port 0 to 1 Relay FIFO Overflow Detect Interrupt Mask 0 Interrupts disabled 1 Interrupts enabled 22 RBSYM0 0 R W E MAC 0 Overflow Alert Signal Output...

Page 931: ...ys read as 0 The write value should always be 0 7 OVFM1 0 R W Port 1 to 0 Relay FIFO Overflow Detect Interrupt Mask 0 Interrupts disabled 1 Interrupts enabled 6 RBSYM1 0 R W E MAC 1 Overflow Alert Signal Output Interrupt Mask 0 Interrupts disabled 1 Interrupts enabled 5 RINTM61 0 R W E MAC 1 Carrier Extension Loss Error Detect Interrupt Mask 0 Interrupts disabled 1 Interrupts enabled 4 RINTM51 0 R...

Page 932: ...6 of 1956 REJ09B0256 0100 Bit Bit Name Initial Value R W Description 1 RINTM21 0 R W E MAC 1 Frame Receive Error Interrupt Mask 0 Interrupts disabled 1 Interrupts enabled 0 RINTM11 0 R W E MAC 1 CRC Error Frame Receive Interrupt Mask 0 Interrupts disabled 1 Interrupts enabled ...

Page 933: ...R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R R W R W R W R W R W R W R W R W R W R W R W R W QTAG0 31 16 QTAG0 15 13 QTAG0 11 0 Bit Bit Name Initial Value R W Description 31 to 16 QTAG0 31 16 H 8100 R W Be sure to set the value of the upper 16 bits QTAG0 31 16 as H 8100 indicates the Qtag extension frame format is used The value read...

Page 934: ...R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R R W R W R W R W R W R W R W R W R W R W R W R W QTAG1 31 16 QTAG1 15 13 QTAG1 11 0 Bit Bit Name Initial Value R W Description 31 to 16 QTAG1 31 16 H 8100 R W Be sure to set the value of the upper 16 bits QTAG1 31 16 as H 8100 indicates the Qtag extension frame format is used The value read...

Page 935: ...alue R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R W R W R W R W R W R W R W R W R W R W R W R W VTAG 0 VID0 11 0 Bit Bit Name Initial Value R W Description 31 VTAG0 0 R W Port 0 VLANtag Evaluation Function 0 Disables receive discard evaluation for frames based on the VLAN number 1 Enables receive discard evaluation for frames based...

Page 936: ...alue R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R W R W R W R W R W R W R W R W R W R W R W R W VTAG 1 VID1 11 0 Bit Bit Name Initial Value R W Description 31 VTAG1 0 R W Port 1 VLANtag Evaluation Function 0 Disables receive discard evaluation for frames based on the VLAN number 1 Enables receive discard evaluation for frames based...

Page 937: ...tten to 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R ADS BSY Bit Bit Name Initial Value R W Description 31 to 1 All 0 R Reserved These bits are always read as 0 The write value should alw...

Page 938: ... W R W R W R W R W R W R W R W R W R W R W R W R W R W R W TEN0 TEN1 TEN2 TEN8 TEN9 TEN10 TEN11 TEN12 TEN13 TEN14 TEN15 TEN16 TEN17 TEN18 TEN19 TEN20 TEN21 TEN22 TEN23 TEN24 TEN25 TEN26 TEN27 TEN3 TEN4 TEN5 TEN6 TEN7 TEN28 TEN29 TEN30 TEN31 Bit Bit Name Initial Value R W Description 31 TEN0 0 R W CAM Entry Table 0 TSU_ADRH0 and TSU_ADRL0 Setting 0 Disabled 1 Enabled 30 TEN1 0 R W CAM Entry Table 1...

Page 939: ...TEN7 0 R W CAM Entry Table 7 TSU_ADRH7 and TSU_ADRL7 Setting 0 Disabled 1 Enabled 23 TEN8 0 R W CAM Entry Table 8 TSU_ADRH8 and TSU_ADRL8 Setting 0 Disabled 1 Enabled 22 TEN9 0 R W CAM Entry Table 9 TSU_ADRH9 and TSU_ADRL9 Setting 0 Disabled 1 Enabled 21 TEN10 0 R W CAM Entry Table 10 TSU_ADRH10 and TSU_ADRL10 Setting 0 Disabled 1 Enabled 20 TEN11 0 R W CAM Entry Table 11 TSU_ADRH11 and TSU_ADRL11...

Page 940: ...N15 0 R W CAM Entry Table 15 TSU_ADRH15 and TSU_ADRL15 Setting 0 Disabled 1 Enabled 15 TEN16 0 R W CAM Entry Table 16 TSU_ADRH16 and TSU_ADRL16 Setting 0 Disabled 1 Enabled 14 TEN17 0 R W CAM Entry Table 17 TSU_ADRH17 and TSU_ADRL17 Setting 0 Disabled 1 Enabled 13 TEN18 0 R W CAM Entry Table 18 TSU_ADRH18 and TSU_ADRL18 Setting 0 Disabled 1 Enabled 12 TEN19 0 R W CAM Entry Table 19 TSU_ADRH19 and ...

Page 941: ...EN23 0 R W CAM Entry Table 23 TSU_ADRH23 and TSU_ADRL23 Setting 0 Disabled 1 Enabled 7 TEN24 0 R W CAM Entry Table 24 TSU_ADRH24 and TSU_ADRL24 Setting 0 Disabled 1 Enabled 6 TEN25 0 R W CAM Entry Table 25 TSU_ADRH25 and TSU_ADRL25 Setting 0 Disabled 1 Enabled 5 TEN26 0 R W CAM Entry Table 26 TSU_ADRH26 and TSU_ADRL26 Setting 0 Disabled 1 Enabled 4 TEN27 0 R W CAM Entry Table 27 TSU_ADRH27 and TSU...

Page 942: ...t Bit Name Initial Value R W Description 2 TEN29 0 R W CAM Entry Table 29 TSU_ADRH29 and TSU_ADRL29 Setting 0 Disabled 1 Enabled 1 TEN30 0 R W CAM Entry Table 30 TSU_ADRH30 and TSU_ADRL30 Setting 0 Disabled 1 Enabled 0 TEN31 0 R W CAM Entry Table 31 TSU_ADRH31 and TSU_ADRL31 Setting 0 Disabled 1 Enabled ...

Page 943: ... W R W R W R W R W R W R W R W POST0 3 0 POST7 3 0 POST6 3 0 POST5 3 0 POST4 3 0 POST3 3 0 POST2 3 0 POST1 3 0 Bit Bit Name Initial Value R W Description 31 to 28 POST0 3 0 All 0 R W These bits set the conditions for referring to CAM entry table 0 By setting multiple bits to 1 multiple conditions can be selected POST0 3 CAM entry table 0 is referred to in port 0 reception POST0 2 CAM entry table 0...

Page 944: ...hese bits set the conditions for referring to CAM entry table 3 By setting multiple bits to 1 multiple conditions can be selected POST3 3 CAM entry table 3 is referred to in port 0 reception POST3 2 CAM entry table 3 is referred to in port 0 to 1 relay POST3 1 CAM entry table 3 is referred to in port 1 reception POST3 0 CAM entry table 3 is referred to in port 1 to 0 relay 15 to 12 POST4 3 0 All 0...

Page 945: ...ese bits set the conditions for referring to CAM entry table 6 By setting multiple bits to 1 multiple conditions can be selected POST6 3 CAM entry table 6 is referred to in port 0 reception POST6 2 CAM entry table 6 is referred to in port 0 to 1 relay POST6 1 CAM entry table 6 is referred to in port 1 reception POST6 0 CAM entry table 6 is referred to in port 1 to 0 relay 3 to 0 POST7 3 0 All 0 R ...

Page 946: ... R W R W R W R W R W R W R W POST8 3 0 POST15 3 0 POST14 3 0 POST13 3 0 POST12 3 0 POST11 3 0 POST10 3 0 POST9 3 0 Bit Bit Name Initial Value R W Description 31 to 28 POST8 3 0 All 0 R W These bits set the conditions for referring to CAM entry table 8 By setting multiple bits to 1 multiple conditions can be selected POST8 3 CAM entry table 8 is referred to in port 0 reception POST8 2 CAM entry tab...

Page 947: ... bits set the conditions for referring to CAM entry table 11 By setting multiple bits to 1 multiple conditions can be selected POST11 3 CAM entry table 11 is referred to in port 0 reception POST11 2 CAM entry table 11 is referred to in port 0 to 1 relay POST11 1 CAM entry table 11 is referred to in port 1 reception POST11 0 CAM entry table 11 is referred to in port 1 to 0 relay 15 to 12 POST12 3 0...

Page 948: ...bits set the conditions for referring to CAM entry table 14 By setting multiple bits to 1 multiple conditions can be selected POST14 3 CAM entry table 14 is referred to in port 0 reception POST14 2 CAM entry table 14 is referred to in port 0 to 1 relay POST14 1 CAM entry table 14 is referred to in port 1 reception POST14 0 CAM entry table 14 is referred to in port 1 to 0 relay 3 to 0 POST15 3 0 Al...

Page 949: ... W R W R W R W R W POST16 3 0 POST23 3 0 POST22 3 0 POST21 3 0 POST20 3 0 POST19 3 0 POST18 3 0 POST17 3 0 Bit Bit Name Initial Value R W Description 31 to 28 POST16 3 0 All 0 R W These bits set the conditions for referring to CAM entry table 16 By setting multiple bits to 1 multiple conditions can be selected POST16 3 CAM entry table 16 is referred to in port 0 reception POST16 2 CAM entry table ...

Page 950: ... bits set the conditions for referring to CAM entry table 19 By setting multiple bits to 1 multiple conditions can be selected POST19 3 CAM entry table 19 is referred to in port 0 reception POST19 2 CAM entry table 19 is referred to in port 0 to 1 relay POST19 1 CAM entry table 19 is referred to in port 1 reception POST19 0 CAM entry table 19 is referred to in port 1 to 0 relay 15 to 12 POST20 3 0...

Page 951: ...bits set the conditions for referring to CAM entry table 22 By setting multiple bits to 1 multiple conditions can be selected POST22 3 CAM entry table 22 is referred to in port 0 reception POST22 2 CAM entry table 22 is referred to in port 0 to 1 relay POST22 1 CAM entry table 22 is referred to in port 1 reception POST22 0 CAM entry table 22 is referred to in port 1 to 0 relay 3 to 0 POST23 3 0 Al...

Page 952: ... W R W R W R W R W POST24 3 0 POST31 3 0 POST30 3 0 POST29 3 0 POST28 3 0 POST27 3 0 POST26 3 0 POST25 3 0 Bit Bit Name Initial Value R W Description 31 to 28 POST24 3 0 All 0 R W These bits set the conditions for referring to CAM entry table 24 By setting multiple bits to 1 multiple conditions can be selected POST24 3 CAM entry table 24 is referred to in port 0 reception POST24 2 CAM entry table ...

Page 953: ... bits set the conditions for referring to CAM entry table 27 By setting multiple bits to 1 multiple conditions can be selected POST27 3 CAM entry table 27 is referred to in port 0 reception POST27 2 CAM entry table 27 is referred to in port 0 to 1 relay POST27 1 CAM entry table 27 is referred to in port 1 reception POST27 0 CAM entry table 27 is referred to in port 1 to 0 relay 15 to 12 POST28 3 0...

Page 954: ...bits set the conditions for referring to CAM entry table 30 By setting multiple bits to 1 multiple conditions can be selected POST30 3 CAM entry table 30 is referred to in port 0 reception POST30 2 CAM entry table 30 is referred to in port 0 to 1 relay POST30 1 CAM entry table 30 is referred to in port 1 reception POST30 0 CAM entry table 30 is referred to in port 1 to 0 relay 3 to 0 POST31 3 0 Al...

Page 955: ...0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W ADRHn 15 0 n 0 to 31 ADRHn 31 16 n 0 to 31 Bit Bit Name Initial Value R W Description 31 to 0 ADRHn 31 0 n 0 to 31 All 0 R W MAC Address Bits These bits set the upper 32 bits of the MAC address When the MAC address is 01 23 ...

Page 956: ...R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W ADRLn 15 0 n 0 to 31 Bit Bit Name Initial Value R W Description 31 to 16 All 0 R Reserved These bits are always read as 0 The write value should always be 0 15 to 0 ADRLn 15 0 n 0 to 31 All 0 R W MAC Address Bits These bits set the lower 16 bits of the MAC address When the MA...

Page 957: ...lted The counter is cleared to 0 by reading from this register This register cannot be written to 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R R R R R R Bit Initial value R W Bit Initial value R W NTC0 31 16 NTC0 15 0 Bit Bit Name Initial Va...

Page 958: ...ount up is halted The counter is cleared to 0 by reading from this register This register cannot be written to 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R R R R R R Bit Initial value R W Bit Initial value R W TC0 31 16 TC0 15 0 Bit Bit Name...

Page 959: ...ted The counter is cleared to 0 by reading from this register This register cannot be written to 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R R R R R R Bit Initial value R W Bit Initial value R W NRC0 31 16 NRC0 15 0 Bit Bit Name Initial Val...

Page 960: ...unt up is halted The counter is cleared to 0 by reading from this register This register cannot be written to 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R RC0 15 0 RC0 31 16 Bit Bit Name ...

Page 961: ...is halted The counter is cleared to 0 by reading from this register This register cannot be written to 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R NFC0 15 0 NFC0 31 16 Bit Bit Name Initi...

Page 962: ...FFFFFFF count up is halted The counter is cleared to 0 by reading from this register This register cannot be written to 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R FC0 15 0 FC0 31 16 Bit...

Page 963: ...lted The counter is cleared to 0 by reading from this register This register cannot be written to 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R NTC1 15 0 NTC1 31 16 Bit Bit Name Initial Va...

Page 964: ...ount up is halted The counter is cleared to 0 by reading from this register This register cannot be written to 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R TC1 15 0 TC1 31 16 Bit Bit Name...

Page 965: ...ted The counter is cleared to 0 by reading from this register This register cannot be written to 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R NRC1 15 0 NRC1 31 16 Bit Bit Name Initial Val...

Page 966: ...unt up is halted The counter is cleared to 0 by reading from this register This register cannot be written to 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R RC1 15 0 RC1 31 16 Bit Bit Name ...

Page 967: ...is halted The counter is cleared to 0 by reading from this register This register cannot be written to 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R NFC1 15 0 NFC1 31 16 Bit Bit Name Initi...

Page 968: ...FFFFFFF count up is halted The counter is cleared to 0 by reading from this register This register cannot be written to 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R FC1 15 0 FC1 31 16 Bit...

Page 969: ... W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R W W ENT ENR Bit Bit Name Initial Value R W Description 31 to 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 ENT 0 W E DMAC Transmitting Unit Start 0 Stops the E DMAC transm...

Page 970: ... written to both the SWRT and SWRR bits simultaneously Writing 1 to the SWRT and SWRR bits initializes the E MAC registers and E DMAC registers except for TDLAR RDLAR and RMFCR of the E DMAC The TSU registers registers whose names are prefixed with TSU_ are not initialized Writing 1 to the SWRT and SWRR bits in EDMR0 initializes the registers related to the E DMAC0 and E MAC 0 whereas writing 1 to...

Page 971: ... 4 DL 1 0 00 R W Transmit Receive Descriptor Length These bits specify the descriptor length See section 23 4 1 Descriptors and Descriptor List 00 16 bytes 01 32 bytes 10 64 bytes 11 Setting prohibited 3 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 SWRT 0 R W Software Reset of Transmit FIFO Controller Writing 0 Disabled 1 Software reset started Reading 0 ...

Page 972: ...1 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R W R W TR 1 0 Bit Bit Name Initial Value R W Description 31 to 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 0 TR 1 0 00 R W Transmit ...

Page 973: ...ive FIFO holds no receive data the E DMAC places receive DMA operation in the standby state If the RACT bit of the receive descriptor is cleared to 0 invalid the E DMAC clears the RR bit and stops receive DMAC operation 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R ...

Page 974: ...itable register that specifies the start address of the transmit descriptor list Descriptors have a boundary configuration in accordance with the descriptor length indicated by the DL bits in EDMR This register must not be modified during transmission Modifications to this register should only be made in the transmission halted state specified by bits TR 1 0 00 in the E DMAC transmit request regis...

Page 975: ...e reception is disabled by the RR bit 0 in the E DMAC receive request register EDRRR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R...

Page 976: ...eption Handling and Priority in section 9 Interrupt Controller INTC GEINT2 is an interrupt generated by TSU_FWSR in the TSU 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R R R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R W R W R W ...

Page 977: ...ocessing based on single frame multi descriptor operation After frame transmission has completed the E DMAC writes the transmission status back to the relevant descriptor TC 1 0 00 Transmission has not completed or no transmission directive 11 Transmission has completed Others Setting disabled 28 TUC 0 R W Transmit Underflow Frame Write Back Complete 0 Write back has not completed for the frame ca...

Page 978: ...receive FIFO has overflowed 0 Receive frame counter has not overflowed 1 Receive frame counter has overflowed 23 0 R Reserved This bit is always read as 0 The write value should always be 0 22 ECI 0 R E MAC Status Register Source This bit is a read only bit When the source of an ECSR interrupt is cleared this bit is also cleared 0 E MAC status interrupt source has not been detected 1 E MAC status ...

Page 979: ...ored in the transmit descriptor list start address register TDLAR 19 TFUF 0 R W Transmit FIFO Underflow Indicates that an underflow has occurred in the transmit FIFO during frame transmission Incomplete data is sent onto the line 0 Underflow has not occurred 1 Underflow has occurred 18 FR 0 R W Frame Reception Indicates that a frame has been received and the receive descriptor has been updated Thi...

Page 980: ... a delayed collision has been detected during frame transmission 0 Delayed collision has not been detected 1 Delayed collision has been detected 8 TRO 0 R W Transmit Retry Over Indicates that a retry over condition has occurred during frame transmission Total 16 transmission retries including 15 retries based on the back off algorithm have failed after the E MAC transmission starts 0 Transmit retr...

Page 981: ... has not been received 1 Residual bit frame has been received 3 RTLF 0 R W Receive Too Long Frame Indicates that a frame whose byte size exceeds the upper limit for the receive frame length set by RFLR has been received 0 Too long frame has not been received 1 Too long frame has been received 2 RTSF 0 R W Receive Too Short Frame Indicates that a frame of fewer than 64 bytes has been received 0 Too...

Page 982: ...IP TWB0 IP TC1 IP ECI IP TC0 IP TDE IP TFUF IP FR IP RDE IP RFE IP DLC IP CD IP TRO IP RMAF IP RRF IP TUC IP ROC IP TABT IP RABT IP RFCOF IP RTLF IP RTSF IP PRE IP CERF IP CEEF IP CELF IP Bit Bit Name Initial Value R W Description 31 TWB1IP 0 R W Write Back Complete Interrupt Enable 0 Write back complete interrupt is disabled 1 Write back complete interrupt is enabled 30 TWB0IP 0 R W Write Back Co...

Page 983: ...Enable 0 Receive frame counter overflow interrupt is disabled 1 Receive frame counter overflow interrupt is enabled 23 0 R Reserved This bit is always read as 0 The write value should always be 0 22 ECIIP 0 R W E MAC Status Register Source Interrupt Enable 0 E MAC status interrupt is disabled 1 E MAC status interrupt is enabled 21 TC0IP 0 R W Frame Transmission Complete Interrupt Enable 0 Frame tr...

Page 984: ...Detect Interrupt Enable 0 Delayed collision detect interrupt is disabled 1 Delayed collision detect interrupt is enabled 8 TROIP 0 R W Transmit Retry Over Interrupt Enable 0 Transmit retry over interrupt is disabled 1 Transmit retry over interrupt is enabled 7 RMAFIP 0 R W Receive Multicast Address Frame Interrupt Enable 0 Receive multicast address frame interrupt is disabled 1 Receive multicast a...

Page 985: ...too long frame interrupt is enabled 2 RTSFIP 0 R W Receive Too Short Frame Interrupt Enable 0 Receive too short frame interrupt is disabled 1 Receive too short frame interrupt is enabled 1 PREIP 0 R W PHY LSI Receive Error Interrupt Enable 0 PHY LSI receive error interrupt is disabled 1 PHY LSI receive error interrupt is enabled 0 CERFIP 0 R W CRC Error on Received Frame Interrupt Enable 0 CRC err...

Page 986: ...ding source is not reflected in the descriptor After this LSI is reset all bits are cleared to 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R W R W R W R W R W R W R W R W R W R W R W DLC CE CD CE TRO CE...

Page 987: ...criptor 8 TROCE 0 R W TRO Bit Copy Directive 0 Reflects the TRO bit status in the TFE bit of the transmit descriptor 1 Occurrence of the corresponding source is not reflected in the TFE bit of the transmit descriptor 7 RMAFCE 0 R W RMAF Bit Copy Directive 0 Reflects the RMAF bit status in the RFE bit of the receive descriptor 1 Occurrence of the corresponding source is not reflected in the RFE bit...

Page 988: ...ng source is not reflected in the RFE bit of the receive descriptor 2 RTSFCE 0 R W RTSF Bit Copy Directive 0 Reflects the RTSF bit status in the RFE bit of the receive descriptor 1 Occurrence of the corresponding source is not reflected in the RFE bit of the receive descriptor 1 PRECE 0 R W PRE Bit Copy Directive 0 Reflects the PRE bit status in the RFE bit of the receive descriptor 1 Occurrence o...

Page 989: ...FF count up is halted Clear the counter by writing H 0000 in this register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W MCF 15 0 Bit Bit Name Initial Value...

Page 990: ... TR 1 0 in EDTRR 11 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R W R W R W R W R W R W R W R W R W R W R W TFT 10 0 Bit Bit Name Initial Value R W Description 31 to 11 All 0 R Reserved These bits are always ...

Page 991: ...R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 1 1 1 0 0 0 1 1 1 1 1 R R R R R R W R W R W R R R R W R W R W R W R W TFD 2 0 RFD 4 0 Bit Bit Name Initial Value R W Description 31 to 11 All 0 R Reserved These bits are always read as 0 The write value should always be 0 10 to 8 TFD 2 0 All 1 R W Transmit FIFO Size Specifies 256 bytes to 2 Kbytes in 256 byte units as th...

Page 992: ...0 Receiving Method Control Register RMCR RMCR is a 32 bit readable writable register that specifies the control method for the RE bit in ECMR while a frame is received This register must be set during the receiving halted state 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R ...

Page 993: ...mation from the receive descriptor Which receive descriptor information is used for processing by the E DMAC can be recognized by monitoring addresses displayed in this register The address from which the E DMAC is actually fetching a descriptor may be different from the value read from this register In the initial setting set the address of the receive descriptor at which receive processing is to...

Page 994: ...al setting set the address of the descriptor immediately before the descriptor that is pointed to by the address in RDFAR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W ...

Page 995: ... 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R W RDLF Bit Bit Name Initial Value R W Description 31 to 1 All 0 R Reserved These bits are always read as 0 The write value should always be 0 0 RDLF 0 R W Receive Descriptor Queue Last Flag Indicates whether the receive descriptor for whic...

Page 996: ...ing a descriptor may be different from the value read from this register In the initial setting set the address of the transmit descriptor at which transmit processing is to be started 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R...

Page 997: ...setting set the address of the transmit descriptor immediately before the descriptor that is pointed to by the address in TDFAR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R ...

Page 998: ...4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R W TDLF Bit Bit Name Initial Value R W Description 31 to 1 All 0 R Reserved These bits are always read as 0 The write value should always be 0 0 TDLF 0 R W Transmit Descriptor Queue Last Flag Indicates whether the transmit descriptor for whi...

Page 999: ...an that set in the RFD bits in FDR Flow control is turned on when either of the setting conditions of bits RFF 4 0 and bits RFD 7 0 is satisfied Flow control is turned off when neither of the conditions is satisfied release 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 R R R R R R R ...

Page 1000: ... are always read as 0 The write value should always be 0 7 to 0 RFD 7 0 H FF R W Receive FIFO Overflow Alert Signal Output Threshold H 00 When 256 32 bytes of data is stored in the receive FIFO H 01 When 512 32 bytes of data is stored in the receive FIFO H 06 When 1 792 32 bytes of data is stored in the receive FIFO H 07 When 2 048 64 bytes of data is stored in the receive FIFO ...

Page 1001: ...8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W PADS 4 0 PADR 15 0 Bit Bit Name Initial Value R W Description 31 to 21 All 0 R Reserved These bits are always read as 0 The write value should always be 0 20 to 16 PADS 4 0 H 00 R W Padding ...

Page 1002: ...ed The E DMAC reads transmit data from the transmit buffer or writes receive data to the receive buffer according to the descriptor information By arranging multiple descriptors as a descriptor row list to be placed in a readable writable memory space multiple Ethernet frames can be transmitted or received continuously The E DMAC consists of two systems one for port 0 and the other for port 1 and ...

Page 1003: ... 1956 REJ09B0256 0100 Receives data and writes to the receive FIFO Transfers data and writes to the transfer FIFO Receives data and writes to the receive FIFO and transfer FIFO Discards data The TSU performs transfers from port 0 to port 1 and from port 1 to port 0 independently ...

Page 1004: ...RISL1 ECMR1 TE 1 ECMR1 RE 1 E MAC 0 E MAC 1 32 entries 48 bits Transmit request EDTRR0 TR 11 Receive request EDRRR0 RR 1 Transmitter startup EDSR0 ENT 1 Receiver startup EDSR0 ENR 1 Transmission enabled Reception enabled Transmit receive descriptor Transmit FIFO Receive FIFO Transmit data buffer Descriptor access DMA transfer Receive data buffer SuperHyway SHwy bridge bus E DMAC 1 Transmit request...

Page 1005: ...laced in continuous addresses memory according to the descriptor length set in the DL0 and DL1 bits in EDMR The E DMAC consists of two systems one for port 0 and the other for port 1 The DMAC for transmission and the DMAC for reception operate independently and the DMAC for port 0 and the DMAC for port 1 operate independently Place descriptors for transmission and reception and descriptors for por...

Page 1006: ...25 26 27 29 28 30 31 12 11 0 31 0 T F E T F P Note According to the descripotr lenght set by the DL0 and DL 1 bits in EDMR the padding size is detemined as follows For 16 bytes Padding 4 bytes For 32 bytes padding 20bytes For 64 bytes Padding 52bytes Figure 23 3 Relationship between Transmit Descriptor and Transmit Buffer a Transmit Descriptor 0 TD0 Before the TR bits in EDTRR are set to 11 the us...

Page 1007: ... recognized when the E DMAC reads a descriptor the E DMAC clears the TR bit in EDTRR to 0 and halts transfer operation related to transmission by the E DMAC 1 Indicates that this transmit descriptor is valid After the user writes 1 to this bit this bit indicates that data is not transferred yet or data is being transferred When there is a descriptor row descriptor list consisting of multiple conti...

Page 1008: ...nts information about the start of the frame 11 The information of the descriptor represents all information about the frame single frame single descriptor single buffer Reference When one frame is divided for use the method of specifying this bit for a descriptor row according to the number of divisions is described below For single frame single descriptor operation First descriptor TFP 1 0 11 Fo...

Page 1009: ...omplete this bit sets the TWB1 and TWB0 bits in EESR to 11 and notifies the CPU of a write back completion interrupt This bit is valid only for the descriptor including the end of transmit frame TFP 01 or 11 This bit is cleared to 0 by the E DMAC write back operation 25 to 12 All 0 R Reserved These bits are always read as 0 The write value should always be 0 11 to 0 TFS 11 0 All 0 R W Transmit Fra...

Page 1010: ... be 0 c Transmit Descriptor 2 TD2 TD2 indicates the start address of the corresponding 32 bit width transmit buffer An address value should be specified in a longword boundary Bit Bit Name Initial Value R W Description 31 to 0 TBA All 0 R W Transmit Buffer Start Address These bits set the start address of the corresponding transmit buffer in a 16 bit boundary If descriptors are set below the E DMA...

Page 1011: ...ied by the DL0 and DL1 bits in EDMR RD0 indicates whether the receive descriptor is valid or invalid and information about descriptor configuration and status RD1 indicates the length of data that can be received in the receive buffer specified by the descriptor RBL and the length of the received frame data RDL RD2 indicates the start address of the receive buffer for storing receive data RBA Depe...

Page 1012: ...lenght set by the DL0 and DL 1 bits in EDMR the padding size is detemined as follows For 16 bytes Padding 4 bytes For 32 bytes padding 20bytes For 64 bytes Padding 52bytes Figure 23 4 Relationship between Receive Descriptor and Receive Buffer a Receive Descriptor 0 RD0 The user sets whether the bits of the descriptor are valid or invalid and whether the descriptor represents the end of the descrip...

Page 1013: ... state is recognized when the E DMAC reads a descriptor the E DMAC clears the RR bit in EDRRR to 0 and halts transfer operation related to reception by the E DMAC 1 Indicates that this receive descriptor is valid Indicates that data is not transferred yet after the user writes 1 to this bit or that data is being transferred When there is a descriptor row descriptor list consisting of multiple cont...

Page 1014: ...formation about the frame single frame single descriptor single buffer Reference The relationship between a frame after reception of one frame and a descriptor is described below For single frame single descriptor operation First descriptor RFP 1 0 11 For single frame two descriptor operation First descriptor RFP 1 0 10 Second descriptor RFP 1 0 01 For single frame three descriptor operation First...

Page 1015: ...of the corresponding event If an event indicated by any of RFS9 to RFS0 occurs the frame is not received completely RFS 11 10 Reserved RFS 9 Receive FIFO overflow corresponding to the RFOF bit in EESR RFS 8 Detection of reception abort Corresponding to the RABT bit in EESR RFS 7 Multicast address frame received corresponding to the RMAF bit in EESR RFS 6 Carrier extension error corresponding to th...

Page 1016: ...r with an integral multiple of 32 bytes The maximum receive buffer data length is between 64 kbytes and 32 bytes H FFE0 15 to 0 RDL All 0 R Receive Data Length These bits indicate the data length of a receive frame stored in the receive buffer Receive data transferred to the receive buffer does not include CRC data 4 bytes placed at the end of a frame As a receive frame length the number of bytes ...

Page 1017: ...ceive buffer capacity is 192 bytes 32 bytes 6 the sixth DMA transfer causes invalid data to be written to the receive buffer In the 32 byte DMA data the former 10 bytes are valid and the latter 22 bytes are invalid Padding of the value 0 can be inserted into only one position in the receive frame by setting RPADIR The padding size can be selected from 1 byte to 31 bytes in byte units When padding ...

Page 1018: ...8 Transmit frame E Transmit buffer 1 Transmit frame A Transmit frame B Transimit buffer 2 Transimit buffer 2 Transmit buffer 4 Transmit buffer 4 Transmit buffer 5 Transmit buffer 6 Transmit buffer 8 Transmit buffer 7 Transmit buffer 8 Transmit buffer 3 Transmit buffer 3 Transmit buffer 6 Transmit buffer 5 Transmit buffer 2 to 4 are connected to be one frame transmit frame B and output to the GMII ...

Page 1019: ...ve frame ength is not a multiple of 32 bytes an undefined value is written Underfined value Receive frame A 29 bytes 32 bytes of unused area Receive frame B Former 32 bytes Receive frame B Former 32 bytes 53 bytes Padding data Receive frame C Receive frame D Former 29 bytes Padding data Receive frame D Latter 35 bytes Receive frame A 64 bytes 63 bytes 29 bytes 53 bytes A frame input from the GMII ...

Page 1020: ...hen the TDLE RDLE value of the processed transmit receive descriptor is 0 the next descriptor will be processed The next descriptor is the transmit receive descriptor at the address obtained by adding the processed transmit receive descriptor address to the descriptor length specified by the DL bit in EDMR When the TDLE RDLE value of the processed transmit receive descriptor is 1 the transmit desc...

Page 1021: ...tor 7 Transmit descriptor 8 1 0 0 0 0 0 1 0 1 0 1 0 1 1 1 0 Receive descriptor ring in memory Receive descriptor list start address register RDLAR Receive descriptor processed address register RDFXR Receive descriptor fetch address register RDFAR in processing The receive descriptor final flag register RDFFR is set to H 00000001 Note Addresses in the descriptor list are shown as an example when th...

Page 1022: ...After DMA transfer of data equivalent to the buffer length specified in the descriptor the following processing is carried out according to the TFP value TFP 10 start of a frame Descriptor write back writing 0 to the TACT bit is performed after completion of DMA transfer TFP 01 or 11 end of a frame Descriptor write back writing 0 to the TACT bit and writing status is performed after completion of ...

Page 1023: ...ansmit processing section reads transmit data from the transmit FIFO to configure a frame and transmits the frame to the GMII MII RMII The amount of data in the transmit FIFO exceeds the number of bytes specified by TFTR One or more frame of data is stored in the transmit FIFO The transmit FIFO has no space full of transmit wait data for the GMII MII RMII ...

Page 1024: ...GETHER initialization Executes a software reset with the SWR bit in EDMR set to 1 Transmit descriptor and transmit setting Setes transmit descriptors and transmit buffer and sets E MAC Start of transmission Occurs when 1 is written to the TE bit in ECMR and 11 is written to the TR bit in EDTRR Transmit descriptor read The E DMAC reads a transmit descriptor Transmit data transfer Writes transmit da...

Page 1025: ...y caused by the carrier detection and frame interval time If full duplex transfer is selected which does not require carrier detection the preamble is sent as soon as a transmit request is issued by the E DMAC 3 The transmitter sends the SFD data and CRC sequentially At the end of transmission the transmit E DMAC generates a transmission complete interrupt TC If a collision or the carrier not dete...

Page 1026: ...transmission of data oreater than 512 bits only jam is transmitted and transmission based on the back off algorithm is not retried FDPX Full duplex HDPX Half duplex Carrier detection Retransfer processing 1 Failure of 15 retransfer attempts or collision after 512 bit time CRC transmission Reset TE reset TE set Transmission halted ldle FDPX HDPX FDPX Error Error Error Collision 2 Collision Carrier ...

Page 1027: ...II RMII At this time the frame that the E MAC receives from the E DMAC is cut off halfway Then the E MAC performs the following operation Writes the TFUF bit in EESR to 1 and generates an interrupt to the CPU Performs a write back operation to the transmit descriptor corresponding to the transmit frame Following the write back operation writes the TUC bit in EESR and generates an interrupt to the ...

Page 1028: ... state 2 When an SFD start frame delimiter is detected after a receive packet preamble the receiver starts receive processing A frame with an invalid pattern is discarded 3 In normal mode if the destination of the frame address is this LSI the receiver starts data reception when broadcast or multicast transmission is specified In promiscuous mode data reception starts regardless of the frame type ...

Page 1029: ...MAC reads the descriptor following the previously used descriptor from the receive descriptor list or the descriptor indicated by RDLAR at the initial startup then enters the receive wait state If 32 bytes or more of data or the last byte of the receive frame is stored in the receive FIFO the E DMAC transfers receive FIFO data to the receive buffer specified by RD2 according to the receive descrip...

Page 1030: ...r more of data or the last byte of the receive frame is stored in the receive FIFO the next receive descriptor process is performed continuously When the TACT bit of the read receive descriptor is 0 invalid the receive descriptor empty state is determined and the RDE bit in EESR is written to 1 and then an interrupt is issued to the CPU To receive frames continuously set the RNC bit in RMCR to 1 T...

Page 1031: ...e descriptor read Legend GETHER initialization Receive descriptor and receive buffer setting Start of Reception Receive descriptor read Receive data transfer Receive descriptor write back Executes a software reset with the SWR bit in EDMR set to 1 Sets receive descriptors and receive buffers and sets E MAC and E DMAC registers then writes 1 to the RE bit in ECMR and the RR bit in EDRRR Occurs when...

Page 1032: ...receive frame information managing area has no empty space up to 24 frames can be managed If an overflow occurs due to the former case the RFE bit in EESR is set to 1 and an interrupt is generated to the CPU If an overflow occurs due to the latter case the RFCOF bit in EESR is set to 1 and an interrupt is generated to the CPU Each time a receive frame is discarded due to an overflow RMFCR is incre...

Page 1033: ... frames can be set in a range from 1 to 24 frames by the frame in frame units d Receive Descriptor Empty When the RACT bit of the read descriptor is 0 invalid the receive descriptor empty state is determined and DMA transfer is stopped Then the following operation is performed Writes the RR bit in EDRRR to 0 Sets the RDE bit in EESR to 1 and generates an interrupt to the CPU To resume the DMA tran...

Page 1034: ... E MAC 1 in a relay from E MAC0 to E MAC1 from E MAC0 in a relay from E MAC1 to E MAC0 At this time collision with the relay frames from the E DMAC may occur The priority of the process when collision occurs can be set by TSU_PRISL0 1 When the relay FIFO use exceeds the TSU_PRISL0 1 setting frame transmission from the relay FIFO takes priority By using this function lost frames due to relay FIFO o...

Page 1035: ...ive and relay In other words when the corresponding bit of the POST table is cleared to 0 receive and relay evaluation will be the same as when CAM is not used shown in table 23 4 The on chip CAM has entry tables which can register the MAC address of 32 entries the details of which can be set by TSU_ADRH0 to TSU_ADRH31 and TSU_ADRL0 to TSU_ADRL31 The setting to enable disable referencing of the on...

Page 1036: ...scarded Received Discarded CAM mishit when addresses do not match Frames having destinations other than this LSI Discarded Received Legend MCT Bit 13 in ECMR Multicast receive mode 0 Receive when CAM mishit 1 Receive when CAM hit Table 23 6 Relay Frame Process With CAM Frame Relay Function Setting Register Bit CAM Hit CAM Mishit FW40 1 0 Relayed Discarded Multicast frame FW40 1 1 Discarded Relayed...

Page 1037: ...01 In the case of a continuing descriptor the TACT bit is cleared to 0 and the next descriptor is read immediately If the descriptor is the final descriptor not only is the TACT bit cleared to 0 but write back is also performed to the TFE and TFS bits at the same time Data in the buffer is not transmitted between the occurrence of an error and write back to the final descriptor If error interrupts...

Page 1038: ...ed buffers If a frame receive error occurs with a descriptor shown in the figure the status is written back to the corresponding descriptor If error interrupts are enabled in EESIPR an interrupt is generated immediately after the write back If there is a new frame receive request reception is continued from the buffer after that in which the error occurred E DMAC Descriptors Inactivates RATC and w...

Page 1039: ...frame enables data following the MAC header to set in 4 byte boundary 16 byte boundary MAC header 14 bytes MAC header 14 bytes MAC header 14 bytes 4 bytes Receive buffer area Padding for separation at 16 byte boundary 16 byte boundary 16 byte boundary No padding 16 byte boundary MAC header 14 bytes MAC header 14 bytes MAC header 14 bytes 4 bytes Receive buffer area Insert 2 byte padding after 14th...

Page 1040: ...urce ECI bit are cleared by writing a 1 to the corresponding source bit The E MAC status register source ECI bit is cleared by writing a 1 to the corresponding source bit in ECSR Interrupt source bits retain the values until they are cleared GEINT0 or GEINT1 interrupt source is allowed to issue interrupts by setting the corresponding bit in EESIPR0 or EESIPR1 Each E MAC state register source ECI b...

Page 1041: ...hen the interrupt source is detected E MAC status register source EESR0 ECI When the interrupt source is detected Frame transmission completed EESR0 TUC After write back Transmit descriptor empty EESR0 TDE When the interrupt source is detected Transmit FIFO underflow EESR0 TFUF When the interrupt source is detected Frame reception EESR0 FR After write back Receive descriptor empty EESR0 RDE When t...

Page 1042: ...ed EESR1 TUC After write back Receive Overflow Frame Write Back Completed EESR1 ROC After write back Transmit Abort Detect EESR1 TABT After write back Receive Abort Detect EESR1 RABT After write back Receive Frame Counter Overflow EESR1 RFCOF When the interrupt source is detected E MAC Status Register Source EESR1 ECI When the interrupt source is detected Frame Transmission Completed EESR1 TUC Aft...

Page 1043: ...ert Signal Output TSU_FWSR RBSY0 When the interrupt source is detected E MAC 0 Carrier Extension Loss Error Detect TSU_FWSR RINT60 When the interrupt source is detected E MAC 0 Residual Bit Frame Receive TSU_FWSR RINT50 When the interrupt source is detected E MAC 0 Too Long Frame Receive TSU_FWSR RINT40 When the interrupt source is detected E MAC 0 Too Short Frame Receive TSU_FWSR RINT30 When the ...

Page 1044: ...tected 23 4 9 Activation Procedure The GETHER should be activated by the following procedure 1 Reset 1 Perform a power on reset 2 Start the E DMAC transmitter and receiver activation of descriptor engine Set ENT to 1 and ENR to 1 in EDSR 3 Perform a software reset Set SWRR to 1 and SWRT to 1 in EDMR simultaneously 4 Initialize the descriptor entry table 5 Confirm cancellation of the software reset...

Page 1045: ...TR Transmit FIFO threshold Set FDR External FIFO size Set RMCR Reset method for reception activation Set RPADIR Padding insertion into receive data Set FCFTR Receive BSY output threshold 2 E MAC related registers Set ECMR setting Transmission reception specifications Set ECSIPR setting Interrupt masks Set MAHR MAC address Set MALR MAC address Set RFLR Maximum receive frame length Set PIPR ET_PHY_I...

Page 1046: ...ed in the PAUSE frame is set by APR The automatic PAUSE frame transmission is repeated until the number of data in the receive FIFO becomes less than the value set in FCFTR as the receive data is read from the FIFO Using TPAUSER the upper limit of retransmission counts of the PAUSE frames can also be set in the range from 1 to 65535 In this case PAUSE frame transmission is repeated until the numbe...

Page 1047: ... PAUSE frame control with the TIME parameter value set to 0 is disabled A PAUSE frame with the TIME parameter value set to 0 is not transmitted When a PAUSE frame with the TIME parameter value set to 0 is received the PAUSE frame is discarded 23 4 11 Magic Packet Detection The GETHER has a Magic Packet detection function This function provides a Wake On LAN WOL facility that starts each peripheral...

Page 1048: ...tion for IEEE802 1Q Qtag The GETHER supports IEEE802 1Q frame processing It can add or delete Qtags to or from frames processed in relay This function can also transmit and receive QoS frames During relay if the Ethernet device connected to one E MAC controller cannot transmit or receive QoS frames the frames can converted to the normal IEEE802 3 frames and relayed in this LSI Whether to add or de...

Page 1049: ...ame Delimiter DA Destination Address SA Source Address L T Length or Type FCS Frame Check Sequence Qtag setting TSU_ADQT0 1 PRT Proprity CFI Fixed at 0 VID V LAN ID setting PRT CFI VID L T Data Data FCS FCS 7 oct 1 oct 7 oct 1 oct 6 oct 6 oct 2 oct 2 oct 8 bit 8 bit Extension code Fixed 3 bit 1 bit 12 bit 6 oct 6 oct 4 oct 46 to 1500 oct 42 to 1500 oct 4 oct 4 oct Figure 23 16 Comparison of Normal...

Page 1050: ...sion Reception Timing Each MII frame transmission reception timing is shown in figures 23 17 to 23 22 ET_TX CLK ET_TX EN ET_TXD3 to 0 ET_TX ER ET_CRS ET_COL SFD Preamble Data CRC Figure 23 17 MII Frame Transmit Timing Normal Transmission ET_TX CLK ET_TX EN ET_TXD3 to 0 ET_TX ER ET_CRS ET_COL Preamble JAM Figure 23 18 MII Frame Transmit Timing Collision ...

Page 1051: ...II Frame Transmit Timing Transmit Error ET_RX CLK ET_RX DV ET_RXD3 to 0 ET_RX ER Preamble Data CRC SFD Figure 23 20 MII Frame Receive Timing Normal Reception ET_RX CLK ET_RX DV ET_RXD3 to 0 ET_RX ER Preamble Data XXXX SFD Figure 23 21 MII Frame Receive Timing Reception Error 1 ET_RX CLK ET_RX DV ET_RXD3 to 0 ET_RX ER XXXX 1110 XXXX Figure 23 22 MII Fame Receive Timing Reception Error 2 ...

Page 1052: ...LK ET_RX DV ET_ERXD3 to 0 ET_RX ER ET_RX CRS Preamble Data CRC SFD GET_ERXD7 to 4 Figure 23 23 GMII MII Fame Receive Timing Normal Reception 0F CRC ET_RX CLK ET_RX DV ET_ERXD3 to 0 ET_RX ER ET_RX CRS GET_ERXD7 to 4 Figure 23 24 GMII MII Fame Receive Timing with Carrier Extension 0F CRC ET_RX CLK ET_RX DV ET_ERXD3 to 0 ET_RX ER ET_RX CRS GET_ERXD7 to 4 Preamble Figure 23 25 GMII MII Fame Receive Ti...

Page 1053: ...eamble SFD GET_ERXD7 to 4 X Figure 23 26 GMII MII Fame Receive Timing Reception Error 1F CRC ET_RX CLK ET_RX DV ET_ERXD3 to 0 ET_RX ER ET_RX CRS GET_ERXD7 to 4 Figure 23 27 GMII MII Fame Receive Timing Error with Carrier Extension ET_RX CLK ET_RX DV ET_ERXD3 to 0 ET_RX ER GET_ERXD7 to 4 X Figure 23 28 GMII MII Fame Receive Timing False Carrier Indication ...

Page 1054: ... I J 0 nibble boundary J K Preamble SFD Data Figure 23 29 RMII Fame Receive Timing Normal 100 Mbps Reception REF50CK False Carrier detected RMII_CRS_DV RMII_RXD1 RMII_RXD0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 23 30 RMII Fame Receive Timing 100 Mbps Reception with Illegal Carrier Detected REF50CK RMII_TX_EN RMII_TXD1 RMII_TXD0 0 0 0 0 0 0 0 0 0 0 0 ...

Page 1055: ...RRRR TA 2 Z0 10 DATA 16 D D D D IDLE X PRE ST OP PHYAD REGAD TA DATA IDLE 32 consecutive 1s Write of 01 indicating start of frame Write of code indicating access type Write of 0001 if the PHY LSI address is 1 sequential write starting with the MSB This bit changes depending on the PHY LSI address Write of 000q if the register address is 1 sequential write starting with the MSB This bit changes dep...

Page 1056: ... PHY LSI type ET_MDC ET_MDO 1 bit data write timing relationship 1 2 3 Write to PHY interface register 1 ET_MMD 1 ET_MDO write data ET_MDC 0 Write to PHY interface register 2 ET_MMD 1 ET_MDO write data ET_MDC 1 Write to PHY interface register 3 ET_MMD 1 ET_MDO write data ET_MDC 0 Figure 23 33 1 Bit Data Write Flowchart ET_MDC ET_MDO Bus release timing relationship 1 2 3 1 Write to PHY interface re...

Page 1057: ...MD 0 ET_MDC 0 Figure 23 35 1 Bit Data Read Flowchart Independent bus release timing relationship ET_MDC ET_MDO 1 1 Write to PHY interface register ET_MMD 0 ET_MDC 0 Figure 23 36 Independent Bus Release Flowchart IDLE in Write in Figure 23 33 23 5 5 Mll RMII Interface Conversion This LSI supports an RMII interface The RMII signals are generated by converting the MII signals in the MII RMII conversi...

Page 1058: ...it waveforms from the MII interface is converted to the RMII interface waveforms and output 10 Mbps or 100 Mbps The collision signal ET_COL is generated by AND operation of the ET_CRS and ET_TX EN signals 4 Full Duplex Half Duplex Selection In full duplex transfer mode the assertion of the COL is suppressed Figure 23 37 shows a schematic of the conversion cicuit RMII_CRS DV MII RMII conversion ET_...

Page 1059: ... the 15th byte from the top and the following bytes before the CRC field are subject to calculation Data subject to checksum calculation Destination address Source address 6 bytes 6 bytes Type 2 bytes CRC 4 bytes Data 46 to 1500 bytes Data subject to checksum calculation Destination address Source address 6 bytes 6 bytes VLANtag 4 bytes Type 2 bytes CRC 4 bytes Data 60 bytes Schematic of an Ethern...

Page 1060: ...Section 23 Gigabit Ethernet Controller GETHER Rev 1 00 Oct 01 2007 Page 994 of 1956 REJ09B0256 0100 ...

Page 1061: ...URITY Rev 1 00 Oct 01 2007 Page 995 of 1956 REJ09B0256 0100 Section 24 IP Security Accelerator SECURITY This section will be made available on conclusion of a nondisclosure agreement For details contact your Renesas Technology sales agency ...

Page 1062: ...Section 24 IP Security Accelerator SECURITY Rev 1 00 Oct 01 2007 Page 996 of 1956 REJ09B0256 0100 ...

Page 1063: ...ion Input output packet length 188 or 192 bytes is selectable The external pin input or peripheral clock 0 Pck0 can be selected as the stream data transfer clock source Transmit receive FIFO size 768 bytes Time stamp adding function Includes a free running timer for time stamp The free running timer input clock can be selected from among 1 2 1 4 and 1 8 of peripheral clock 0 At reception The free ...

Page 1064: ...ce STIF Peripheral bus interface ST0_CLK ST0_STRB ST0_REQ ST0_START ST0_VALID ST0_D7 to ST0_D0 FIFO register ST1_CLK ST1_STRB ST1_REQ ST1_START ST1_VALID ST1_D7 to ST1_D0 ST0M_CLKIO ST0M_STRBI ST0M_REQO ST0M_STARTI ST0M_VALIDI ST0M_D7I to ST0M_D0I Peripheral bus interface FIFO register Stream interface control unit Channel 1 Channel 0 Perioheral clock 0 Pck 0 Figure 25 1 Block Diagram of STIF ...

Page 1065: ...ription ST0_CLK ST0_STRB I O Stream data clock strobe ST0_REQ I O Stream data receive ready request ST0_START I O Stream data synchronization ST0_VALID I O Stream data valid Normal I O pins ST0_D7 to ST0_D0 I O Stream data input output ST0M_CLKIO ST0M_STRBI I O Stream data clock strobe ST0M_REQO Output Stream data receive ready request ST0M_STARTI Input Stream data synchronization input ST0M_VALID...

Page 1066: ... H FFEE 0010 H 1FEE 0010 32 Transmit receive packet count register 0 STIPNR0 R W H FFEE 0018 H 1FEE 0018 32 Transmit receive packet counter register 0 STIPCR0 R W H FFEE 0014 H 1FEE 0014 32 Transmit receive FIFO data register 0 STIFIFO0 R W H FFEE 0400 H 1FEE 0400 32 Mode register 1 STIMDR1 R W H FFEE 8000 H 1FEE 8000 32 Control register 1 STICR1 R W H FFEE 8004 H 1FEE 8004 32 Interrupt status reg...

Page 1067: ...00000000 Retained Retained Transmit receive packet counter register 0 STIPCR0 H 00000000 H 00000000 Retained Retained Transmit receive FIFO data register 0 STIFIFO0 H 00000000 H 00000000 Retained Retained Mode register 1 STIMDR1 H 00000000 H 00000000 Retained Retained Control register 1 STICR1 H 00000000 H 00000000 Retained Retained Interrupt status register 1 STIISR1 H 00000000 H 00000000 Retaine...

Page 1068: ... 0 PLEN REQ REQ EN STRB VLD CKSL STAT FRC 1 0 CKDV 1 0 WORK 1 0 Bit Bit Name Initial Value R W Description 31 0 R Reserved This bit is always read as 0 The write value should always be 0 30 to 28 MD 2 0 000 R W Stream Data Transfer Interface 000 Clock valid reception 010 Strobe reception 100 Clock valid transmission 101 Strobe transmission Other than above Setting prohibited 27 to 25 All 0 R Reser...

Page 1069: ...0 Transfers the receive packet to external memory without any changes only when the packet size is 192 bytes 11 Setting prohibited At transmission These bits select the packet interval for transmitting the transmit packet 00 Packet interval is in accordance with the ICYC bits in STICR 01 Packet interval is in accordance with the time stamp 10 11 Setting prohibited 19 18 All 0 R Reserved These bits...

Page 1070: ...d always be 0 13 12 CKDV 1 0 00 R W Operating Clock Division Ratio These bits specify the division ratio when peripheral clock 0 is selected as the stream data transfer clock 00 Stream data transfer clock is 1 2 of peripheral clock 0 01 Stream data transfer clock is 1 4 of peripheral clock 0 10 Stream data transfer clock is 1 8 of peripheral clock 0 11 Setting prohibited 11 to 9 All 0 R Reserved T...

Page 1071: ... Timer input clock is 1 4 of peripheral clock 0 10 Timer input clock is 1 8 of peripheral clock 0 11 Setting prohibited 3 STRB 0 R W ST_STRB Pin Polarity 0 Data is transferred received on the rising edge of ST_STRB 1 Data is transferred received on the falling edge of ST_STRB 2 REQ 0 R W ST_REQ Pin Polarity 0 ST_REQ is active high 1 ST_REQ is active low 1 VLD 0 R W ST_VALID Pin Polarity 0 ST_VALID...

Page 1072: ...W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 28 All 0 R Reserved These bits are always read as 0 The write value should always be 0 27 to 16 ICYC 11 0 All 0 R W Number of Cycles between Transmit Packets These bits set the fixed value when a fixed value is used as the number of cycles between packets during transmission 1 to 4096 cycles of peripheral clock 0 can be inser...

Page 1073: ...o 29 All 0 R Reserved These bits are always read as 0 The write value should always be 0 28 TPN 0 R W Transmit Packet Count Interrupt 0 Transmit packet count register value Transmit packet counter value 1 Transmit packet count register value Transmit packet counter value After an interrupt is issued the transmit packet counter is cleared to 0 and continues counting 27 to 13 All 0 R Reserved These ...

Page 1074: ...t less than 188 or 192 bytes has not been not received 1 Packet less than 188 or 192 bytes has been received When a packet less than 188 or 192 bytes is received the short packet counter is incremented by one and the packet is discarded 7 to 5 All 0 R Reserved These bits are always read as 0 The write value should always be 0 4 ROVF 0 R W Receive FIFO Overflow Interrupt 0 Receive FIFO has not over...

Page 1075: ...0 The write value should always be 0 28 TPNE 0 R W Transmit Packet Count Interrupt Enable 0 Transmit packet count interrupt is disabled 1 Transmit packet count interrupt is enabled 27 to 13 All 0 R Reserved These bits are always read as 0 The write value should always be 0 12 RPNE 0 R W Receive Packet Count Interrupt Enable 0 Receive packet count interrupt is disabled 1 Receive packet count interr...

Page 1076: ...d always be 0 4 ROVFE 0 R W Receive FIFO Overflow Interrupt Enable 0 Receive FIFO overflow interrupt is disabled 1 Receive FIFO overflow interrupt is enabled 3 to 1 All 0 R Reserved These bits are always read as 0 The write value should always be 0 0 TSTOE 0 R W Time Stamp Counter Overflow Interrupt Enable 0 Time stamp counter overflow interrupt is disabled 1 Time stamp counter overflow interrupt ...

Page 1077: ... W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 0 TS 31 0 All 0 R W Time Stamp Counter When time stamp is used At reception Starts counting from reception of the first packet Counting can be started from any desired value by setting the value before reception However this register cannot be written to during reception of a packet At transmission Starts counting from trans...

Page 1078: ...W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W PN 20 16 PN 15 0 Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 21 All 0 R Reserved These bits are always read as 0 The write value should always be 0 20 to 0 PN 20 0 All 0 R W Number of Transmit Receive Packets These bits set the number of packets for tra...

Page 1079: ...ived are also set in this register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R PC 20 16 PC 15 0 LC 3 0 SC 3 0 Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 28 SC 3 0 All 0 R Number of...

Page 1080: ...2 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W STD 31 16 STD 15 0 Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 0 STD 31 0 All 0 R W Transmit Receive Stream Data At transmission tr...

Page 1081: ... in STIMDR If addition of time stamp or fixed value is selected and the data length is 192 bytes the first four bytes of the received data will be overwritten 0 16 20 208 Data 188 bytes Work area Work area 2 TS or fixed value 2 Data length 192 bytes Time stamp TS or fixed value added 0 16 208 Data 192 bytes Work area Work area 2 3 Data length 192 bytes Time stamp TS or fixed value added 0 16 20 20...

Page 1082: ... TCR according to the following equation Only the value calculated below should be set Transfer count 192 bytes work area byte count 16 bytes transmit receive packet count Set H 0001 0001 in TCRB The upper bits indicate the transfer count until reloading is performed and the lower bits indicate the transfer counter value Set H 0E20 5819 in CHCR Set the module ID and register ID H D3 when STIF chan...

Page 1083: ...SL bit in STIMDR maximum frequency is 33 MHz Active level setting for ST_START ST_VALID and ST_REQ pins The active levels of the ST_START ST_VALID and ST_REQ pins can be set by the STAT VLD and REQ bits in STIMDR respectively Selection of ST_REQ pin usage Whether or not to use the ST_REQ pin can be selected by the REQEN bit in STIMDR When usage of the ST_REQ pin is enabled the ST_REQ pin is assert...

Page 1084: ... are overwritten with the fixed value Reception with a time stamp added When the packet length is 188 bytes the time stamp counter value is added to the front of the packet When the packet length is 192 bytes data at the beginning of the packet is overwritten with the time stamp counter value The time stamp counter starts counting from reception of the first packet Counting can be started from any...

Page 1085: ...bits in STIMDR respectively Selection of ST_REQ pin usage Whether or not to use the ST_REQ pin can be selected by the REQEN bit in STIMDR When usage of the ST_REQ pin is enabled the ST_REQ pin is asserted when the free space in the transmit receive FIFO for stream data becomes eight bytes or less After assertion up to eight bytes of data can be received The ST_REQ pin is negated when the free spac...

Page 1086: ...e FIFO overflow interrupt 25 3 12 Stream Data Transmit Operation 1 DMAC Register Setting When starting the stream data transmit processing set the following DMAC registers Set the external memory address in SAR Set the P4 area address for the data register of the transmit receive FIFO of the STIF in DAR Set the DMA transfer count in TCR according to the following equation Only the value calculated...

Page 1087: ...s of the ST_START ST_VALID and ST_REQ pins can be set by the STAT VLD and REQ bits in STIMDR respectively Selection of ST_REQ pin usage Whether or not to use the ST_REQ pin can be selected by the REQEN bit in STIMDR When usage of the ST_REQ pin is enabled the ST_VALID pin is negated within four bytes after assertion of the ST_REQ pin When usage of the ST_REQ pin is disabled the ST_VALID pin is not...

Page 1088: ...ission Transmission is performed using the value set in the ICYC 11 0 bits in STICR as the packet interval 1 to 4096 cycles of peripheral clock 0 can be set Time stamp transmission Transmission is performed with time stamp based packet intervals The time stamp counter starts counting from transmission of the first packet Counting can be started from any desired value by setting the value before tr...

Page 1089: ...ID and ST_REQ pins can be set by the STRB STAT VLD and REQ bits in STIMDR respectively Selection of ST_REQ pin usage When strobe transmission is selected the ST_REQ pin always functions as an input pin regardless of the REQEN bit setting in STIMDR b Transmit Packet Length The transmit packet length can be selected from 188 and 192 bytes Since the packet length is handled as 192 bytes in external m...

Page 1090: ...nsmission can be selected Set the STMP 1 0 bits in STIMDR to 00 Fixed interval transmission Transmission is performed using the value set in the ICYC 11 0 bits in STICR as the packet interval Cycles of half the frequency of peripheral clock 0 are counted and 1 to 4096 cycles can be set e Interrupt Source during Transmission During strobe transmission the following interrupt source is available Tra...

Page 1091: ...lips I2 C bus interface Multi master compatible Seven or ten bit address compatible master Seven bit slave address Fast mode compatible Variable clock frequencies Figure 26 1 shows a block diagram for the I2 C bus interface Tx Data Rx Data Control Status Register Master Slave IIC_SCL IIC_SCL IIC_SDA Clock Generator Clock Filter Data Filter IIC_SDA IO Bus Figure 26 1 Block Diagram for I2 C Bus Inte...

Page 1092: ... 26 2 Register Configuration Channel Register Name Abbreviation R W Area P4 Address 1 Area 7 Address 1 Access Size Slave control register 0 ICSCR0 R W H FFE7 0000 H 1FF7 0000 8 Master control register 0 ICMCR0 R W H FFE7 0004 H 1FF7 0004 8 Slave status register 0 ICSSR0 R W 2 H FFE7 0008 H 1FF7 0008 8 Master status register 0 ICMSR0 R W 3 H FFE7 000C H 1FF7 000C 8 Slave interrupt enable register 0...

Page 1093: ...8 Master interrupt enable register 1 ICMIER1 R W H FFE7 8014 H 1FF7 8014 8 Clock control register 1 ICCCR1 R W H FFE7 8018 H 1FF7 8018 8 Slave address register 1 ICSAR1 R W H FFE7 801C H 1FF7 801C 8 Master address register 1 ICMAR1 R W H FFE7 8020 H 1FF7 8020 8 Receive data register 1 ICRXD1 R W H FFE7 8024 H 1FF7 8024 8 1 Transmit data register 1 ICTXD1 R W H FFE7 8024 H 1FF7 8024 8 Notes 1 P4 ad...

Page 1094: ... 00 H 00 Retained Retained Master address register 0 ICMAR0 H 00 H 00 Retained Retained Receive data register 0 ICRXD0 H 00 H 00 Retained Retained 0 Transmit data register 0 ICTXD0 H 00 H 00 Retained Retained Slave control register 1 ICSCR1 H 00 H 00 Retained Retained Master control register 1 ICMCR1 H x0 H x0 Retained Retained Slave status register 1 ICSSR1 H 00 H 00 Retained Retained Master stat...

Page 1095: ...selected During a reception as long as both buffers are full and the SDR flag has not been cleared SCL is held low When the SDR flag is cleared the low level state of SCL is released When this bit is set to 1 the single buffer mode is selected SCL will be held low from the timing when the receive data register acquires the data packet until the SDR flag is cleared 0 Double buffer mode 1 Single buf...

Page 1096: ...et to 0 during the period that the data packet is being received and set to 1 on completion of data reception Forced non acknowledgement is returned to the master during slave reception When the slave has received the last byte of data in a data packet the slave communicates with the master by sending a nack meaning that the acknowledgement is not driven The master issues a stop on the bus after r...

Page 1097: ...6 GCAR 0 R General Call Address Received Indicates that the address received from the bus is a general call address 00H This status bit does not cause an interrupt This bit is automatically cleared by hardware when the SIE bit bit 2 in the slave control register is set to 0 or when the SSR bit bit 4 in this register is set to 1 5 STM 0 R Slave Transmit Mode Indicates whether the current slave tran...

Page 1098: ...edge of SCL before the first data bit During the single buffer mode this bit must be reset every time new data has been written to the ICTXD register This is because the slave holds SCL low to stop the bus while this bit is set to 1 even if a slave transmission cycle is started 2 SDT 0 R W Slave Data Transmitted A byte of data has been transmitted to the bus This bit becomes active after the falli...

Page 1099: ...gister then this status bit is also set to 1 even if the address on the bus is a general call address In this case the GCAR bit in this register is used to determine whether or not the address is a general call address The STM bit indicates whether the access is read high or write low This status becomes active after the falling edge of SCL during the last address bit The slave holds SCL low durin...

Page 1100: ...e 0 4 SSRE 0 R W Slave Stop Received Interrupt Enable 0 Disables the SSR interrupt 1 Enables the SSR interrupt 3 SDEE 0 R W Slave Data Empty Interrupt Enable 0 Disables the SDE interrupt 1 Enables the SDE interrupt 2 SDTE 0 R W Slave Data Transmitted Interrupt Enable 0 Disables the SDT interrupt 1 Enables the SDT interrupt 1 SDRE 0 R W Slave Data Received Interrupt Enable 0 Disables the SDR interr...

Page 1101: ...W SADDO 6 0 BIt Initial value R W Bit Bit Name Initial Value R W Description 7 0 R Reserved The write value should always be 0 6 to 0 SADD0 6 0 All 0 R W Slave Address This is the unique 7 bit address allocated to the slave on the I 2 C bus The slave interface compares this address with the first seven bits transmitted as the slave address at the beginning of a data packet transmission ...

Page 1102: ...gle buffer mode is selected SCL will be held low from the timing when the receive data register acquires the data packet until the MDR flag is cleared 0 Double buffer mode 1 Single buffer mode 6 FSCL R W Forced SCL This bit controls the status of the I2C_SCL pin reading reflects the current level on the I2 C bus When the OBPC bit is set this bit directly controls the SCL line on the bus During a r...

Page 1103: ...en this bit is set to 1 the master transmits a STOP condition on the bus at the end of the current transfer If ESG is also set the master immediately transmits a START condition and begins transmitting a new data packet If ESG is not set state the master enters the idle state 0 ESG 0 R W Enable Start Generation When this bit is set to 1 the master starts transmission of a data packet If the bus is...

Page 1104: ...aster Nack Received When this bit is set to 1 this bit indicates that the master has received a nack response the SDA line is high during the acknowledge cycle on the bus to either an address or data transmission 5 MAL 0 R W Master Arbitration Lost In a multi master system when this bit is set to 1 it indicates that the master has lost arbitration to one of other masters on the bus At this point M...

Page 1105: ... edge of SCL during the last data bit 1 MDR 0 R W Master Data Received Byte data has been received from the bus and is in the receive data register This status bit becomes active after the falling edge of SCL during the last data bit During single buffer mode this status bit must be reset after data has been read from the receive data register When MDBS is set to 1 SCL will be held low from the ti...

Page 1106: ...5 MALE 0 R W Master Arbitration Lost Interrupt Enable 0 Disables the MAL interrupt 1 Enables the MAL interrupt 4 MSTE 0 R W Master Stop Transmitted Interrupt Enable 0 Disables the MST interrupt 1 Enables the MST interrupt 3 MDEE 0 R W Master Data Empty Interrupt Enable 0 Disables the MDE interrupt 1 Enables the MDE interrupt 2 MDTE 0 R W Master Data Transmitted Interrupt Enable 0 Disables the MDT ...

Page 1107: ...e Transfer Mode This bit specifies the mode in which the slave operates Bit STM1 sets the operating mode transmit or receive mode of the slave which is an external slave device whose address matches the slave address SADD1 sent from the master The slave device is automatically set to transmit receive mode by hardware on reception of the STM1 signal When this bit is set to 1 it indicates a read ope...

Page 1108: ...internal clock frequency Suggested settings for CDF and SCGD for various CPU speeds and the two I 2 C bus speeds are given in table 26 4 1 0 CDF All 0 R W Clock Division Factor The internal clock used in most blocks in the I 2 C module is a divided peripheral clock The internal I 2 C clock is generated from the peripheral clock using the CDF as the division ratio Equation 1 I 2 C internal clock fr...

Page 1109: ...en data is to be transmitted the contents of the shift register are loaded via TXD After data has been received into the shift register from the I2 C bus it is then loaded into RXD Receive Data Register ICRXD 7 6 5 4 3 2 1 0 BIt Initial value R W 0 0 0 0 0 0 0 0 R R R R R R R R RXD 7 0 Bit Bit Name Initial Value R W Description 7 to 0 RXD 7 0 All 0 R Read Receive Data Data received by master or sl...

Page 1110: ...ve Interfaces These two interfaces run independently and in parallel The master interface controls the transmission of address and data on the I2 C bus The slave interface monitors the I2 C bus and takes part in transmissions if its programmed address is seen on the bus The interfaces communicate with the control status registers independently There is only one interrupt line output from the I2 C ...

Page 1111: ...r is reset At this point master mode is invalid and the I2 C bus interface enters the slave mode When master operation is restarted data transfer from the master begins after the MAL bit has been cleared 4 SAR The SAR status bit is set when the slave identifies its address on the I2 C bus At this point the slave interface forces the SCL line low until the SAR status bit is reset This is particular...

Page 1112: ...changes SDA from high to low while SCL is high level SLA Indicates a slave address A slave address is used when a master device selects a slave device R W Indicates the direction of data transmission If the R W bit is 1 the data flows from the slave to the master device If the bit is 0 the data flows from the master to the slave device A Indicates data acknowledge Data receiving device makes SDA l...

Page 1113: ... ADDRESS A P A A DATA DATA R W A Data transferres n Bytes ACKNOWLEDGE Figure 26 3 Master Data Transmit Format 1 Read S SLAVE ADDRESS A P A A DATA DATA R W A Data transferred n Bytes ACKNOWLEDGE Figure 26 4 Master Data Receive Format Figure 26 5 shows the combined format when the data transfer direction changes during one transfer When changing the direction after the first transfer the repeated ST...

Page 1114: ...s transfer format Figure 26 6 shows the data transmit format The set value in the master address register is output in one byte following the first START condition S The value set in the transmit data register TXD is transmitted as a slave address in the second byte Data on and after the third byte is transferred in the same way as the 7 bit address data 0 Write SLAVE ADDRESS A2 P A A DATA DATA R ...

Page 1115: ...ive combined format In the data transmit receive combined format data is transmitted after an address is transmitted with the first two bytes Then the repeated START condition Sr is transmitted instead of STOP condition P After Sr is transmitted the procedure is the same as that in the data receive format 0 Write SLAVE ADDRESS R W A1 SLAVE ADDRESS S 2nd Byte 1st Byte 7 Bits 1 1 1 1 0 X X SLAVE ADD...

Page 1116: ...smission at the timing of 7 in figure 26 9 The slave device drives IIC_SDA low at the ninth clock and returns ACK 5 Data is transmitted in units of nine bits 8 bit data and 1 bit ACK An interrupt of MDE bit 3 is generated at the ninth clock before data transfer at the timing of 2 in figure 26 9 An interrupt of MDT bit 2 is generated at the eighth clock after 1 byte data transfer at the timing of 4...

Page 1117: ...nal level changes of 1 to 6 in figure 26 9 are generated after the falling edge of the clock S ACK 1 2 3 4 5 6 7 8 9 1 IIC_SDA bit7 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 IIC_SCL IIC_SDA MASTER output IIC_SDA SLAVE output MASTER IRQ SLAVE IRQ 1 7 3 ACK IIC_SDA 1 2 3 4 5 6 7 8 9 1 9 4 2 5 IIC_SCL IIC_SDA Master output IIC_SDA Slave output MASTER IRQ SLA...

Page 1118: ...f this processing is delayed the slave device extends the SCL period to suspend data transmission as shown at the timing of 3 in figure 26 10 3 The slave device generates an interrupt of the status SDT bit 2 indicating 1 byte data transfer end at the eighth clock at the timing of 2 in figure 26 10 and an interrupt of the status SDE bit 3 indicating data empty at the ninth clock at the timing of 1 ...

Page 1119: ...007 Page 1053 of 1956 REJ09B0256 0100 IIC_SDA 1 2 3 4 5 6 7 8 9 1 9 IIC_SCL Master IRQ 2 Slave IRQ IIC_SDA Slave output IIC_SDA Master output ACK 1 3 1 bit 7 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Figure 26 10 Data Receive Mode Operation Timing ...

Page 1120: ...e being accessed and STM1 bit write mode 0 2 Transmit data register first data byte to be transmitted 3 Master control register H 89 MDBS 1 MIE 1 ESG 1 3 Wait for Outputting Address 1 Wait for master event an interrupt of the MAT and MDE bits in the master status register 2 Set the master control register to H 88 To suspend the data transmission the master device will hold the SCL low until the MD...

Page 1121: ... clock generation divider SCGD H 03 SCL frequency of 400 kHz 2 Clock division ratio CDF H 3 The peripheral clock is 66 7 MHz and the IIC s internal clock IICck is 16 7 MHz 2 Load Master Control Register and Address 1 Set master address register to address of slave being accessed and STM1 bit read mode 1 2 Set master control register to H 89 MDBS 1 MIE 1 ESG 1 3 Wait for Outputting Address 1 Wait f...

Page 1122: ...or master event MST in the master status register 3 Reset the MST bit 26 5 3 Master Transmitter Restart Master Receiver In order to set up the master interface to transmit a data packet on the I2 C bus issue a restart then read byte data back from the slave follow the following procedure 1 Load Clock Control Register 1 Set the SCL clock generation divider SCGD to H 03 SCL frequency of 400 kHz 2 Se...

Page 1123: ... control register to H 88 To suspend stop the data transmission the master device will hold the IIC_SCL low until the MDR bit is cleared 3 Reset the MAT bit 5 Monitor of Data 1 Wait for master event the MDR bit in the master status register Read data from the received data register If the next byte of data is the second to last byte but one to be transmitted by the slave device the following appli...

Page 1124: ...Section 26 I 2 C Bus Interface IIC Rev 1 00 Oct 01 2007 Page 1058 of 1956 REJ09B0256 0100 ...

Page 1125: ...aracter by character Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver Transmitter UART or Asynchronous Communication Interface Adapter ACIA There is a choice of 8 serial data transfer formats Data length 7 or 8 bits Stop bit length 1 or 2 bits Parity Even odd none Receive error detection Parity framing and overrun...

Page 1126: ...ta full and receive error that can issue requests independently The DMA controller DMAC can be activated to execute a data transfer by issuing a DMA transfer request in the event of a transmit FIFO data empty or receive FIFO data full interrupt When not in use the SCIF can be stopped by halting its clock supply to reduce power consumption In asynchronous mode modem control functions SCIF0_RTS SCIF...

Page 1127: ...O data register Transmit shift register Transmit FIFO data register Serial mode register Serial control register Serial status register SCBRRn SCSPTRn SCFCRn SCTFDRn SCRFDRn SCLSRn SCRERn Bit rate register Serial port register FIFO control register Transmit FIFO data count register Receive FIFO data count register Line status register Serial error register SCRSRn SCTSRn SCSMRn SCLSRn SCTFDRn SCRFD...

Page 1128: ...ock diagrams of the I O ports in SCIF Reset Peripheral bus SPTRW D7 D6 R Q D RTSIO C Reset SPTRR SPTRW R Q D RTSDT C SPTRW SCIFn_RTS SCIF_RTS signal Write to SCSPTR SPTRR Read from SCSPTR Notes n 0 1 The SCIFn_RTS pin function is designated as modem control by the MCE bit in SCFCR Modem control enable signal Figure 27 2 SCIFn_RTS Pin n 0 1 ...

Page 1129: ...0100 Reset Peripheral bus SPTRW D5 D4 R Q D CTSIO C Reset SPTRR SPTRW R Q D CTSDT C SPTRW SCIFn_CTS SCIF_CTS signal Write to SCSPTR SPTRR Read from SCSPTR Notes n 0 1 The SCIFn_CTS pin function is designated as modem control by the MCE bit in SCFCR Modem control enable signal Figure 27 3 SCIFn_CTS Pin n 0 1 ...

Page 1130: ...signal Serial clock output signal Serial clock input signal Serial input enable signal Note The SCIFn_CLK pin function is designated as internal clock output or external clock input by the C A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR SPTRR Figure 27 4 SCIFn_SCK Pin n 0 1 Reset Peripheral bus SPTRW R Q D D1 D0 SPB2IO C Reset SPTRW R Q D SPB2DT C SCIFn_TXD SPTRW Write to SCSPTR Transmit enab...

Page 1131: ...27 1 Pin Configuration Pin Name Function I O Description SCIFn_SCK n 0 1 Serial clock pin I O Clock input output SCIFn_RXD n 0 1 Receive data pin Input Receive data input SCIFn_TXD n 0 1 Transmit data pin Output Transmit data output SCIFn_CTS n 0 1 Modem control pin I O Transmission enabled SCIFn_RTS n 0 1 Modem control pin I O Transmission request Note These pins are made to function as serial pi...

Page 1132: ...gister 0 SCRFDR0 R H FFE0 0020 H 1FE0 0020 16 Serial port register 0 SCSPTR0 R W H FFE0 0024 H 1FE0 0024 16 Line status register 0 SCLSR0 R W 2 H FFE0 0028 H 1FE0 0028 16 Serial error register 0 SCRER0 R H FFE0 002C H 1FE0 002C 16 1 Serial mode register 1 SCSMR1 R W H FFE0 8000 H 1FE0 8000 16 Bit rate register 1 SCBRR1 R W H FFE0 8004 H 1FE0 8004 8 Serial control register 1 SCSCR1 R W H FFE0 8008 ...

Page 1133: ... register 0 SCSPTR0 H 0000 1 H 0000 1 Retained Retained Line status register 0 SCLSR0 H 0000 H 0000 Retained Retained Serial error register 0 SCRER0 H 0000 H 0000 Retained Retained 1 Serial mode register 1 SCSMR1 H 0000 H 0000 Retained Retained Bit rate register 1 SCBRR1 H FF H FF Retained Retained Serial control register 1 SCSCR1 H 0000 H 0000 Retained Retained Transmit FIFO data register 1 SCFTD...

Page 1134: ...t Initial value R W 27 3 2 Receive FIFO Data Register SCFRDR SCFRDR is an 8 bit FIFO register of 64 stages that stores received serial data When the SCIF has received one byte of serial data it transfers the received data from SCRSR to SCFRDR where it is stored and completes the receive operation SCRSR is then enabled for reception and consecutive receive operations can be performed until SCFRDR i...

Page 1135: ...R and transmission started automatically SCTSR cannot be directly read from and written to by the CPU 0 1 2 3 4 5 6 7 BIt Initial value R W 27 3 4 Transmit FIFO Data Register SCFTDR SCFTDR is an 8 bit FIFO register of 64 stages that stores data for serial transmission If SCTSR is empty when transmit data has been written to SCFTDR the SCIF transfers the transmit data written in SCFTDR to SCTSR and...

Page 1136: ...R R W R W R W R W R W R R R R R R R R BIt Initial value R W Bit Bit Name Initial Value R W Description 15 to 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7 C A 0 R W Communication Mode Selects asynchronous mode or clocked synchronous mode as the SCIF operating mode 0 Asynchronous mode 1 Clocked synchronous mode 6 CHR 0 R W Character Length Selects 7 or 8 bi...

Page 1137: ...0 R W Parity Mode Selects either even or odd parity for use in parity addition and checking In asynchronous mode the O E bit setting is only valid when the PE bit is set to 1 enabling parity bit addition and checking In clocked synchronous mode or when parity addition and checking is disabled in asynchronous mode the O E bit setting is invalid 0 Even parity 1 Odd parity When even parity is set par...

Page 1138: ...e start bit of the next transmit character Note 1 In transmission a single 1 bit stop bit is added to the end of a transmit character before it is sent 2 In transmission two 1 bits stop bits are added to the end of a transmit character before it is sent 2 0 R Reserved This bit is always read as 0 The write value should always be 0 1 0 CKS1 CKS0 0 0 R W R W Clock Select 1 and 0 These bits select th...

Page 1139: ...e R W Description 15 to 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7 TIE 0 R W Transmit Interrupt Enable Enables or disables transmit FIFO data empty interrupt TXI request generation when serial transmit data is transferred from SCFTDR to SCTSR the number of data bytes in SCFTDR falls to or below the transmit trigger set number and the TDFE flag in SCFSR ...

Page 1140: ...st disabled 1 Receive data full interrupt RXI request receive error interrupt ERI request and break interrupt BRI request enabled Note An RXI interrupt request can be cleared by reading 1 from the RDF or DR flag then clearing the flag to 0 or by clearing the RIE bit to 0 ERI and BRI interrupt requests can be cleared by reading 1 from the ER BRK or ORER flag then clearing the flag to 0 or by cleari...

Page 1141: ...ion format decided and the receive FIFO reset before the RE bit is set to 1 3 REIE 0 R W Receive Error Interrupt Enable Enables or disables generation of receive error interrupt ERI and break interrupt BRI requests The REIE bit setting is valid only when the RIE bit is 0 Receive error interrupt ERI and break interrupt BRI requests can be cleared by reading 1 from the ER BRK or ORER flag then clear...

Page 1142: ... an internal clock is selected as the SCIF clock source CKE1 0 When an external clock is selected CKE1 1 the CKE0 bit setting is invalid The CKE1 and CKE0 bits must be set before determining the SCIF s operating mode with SCSMR Asynchronous mode 00 Internal clock SCIF_SCK pin functions as port 01 Internal clock SCIF_SCK pin functions as clock output 1 1x External clock SCIF_SCK pin functions as cl...

Page 1143: ...tten to flags ER TEND TDFE BRK RDF and DR Also note that in order to clear these flags they must be read as 1 beforehand The FER flag and PER flag are read only flags and cannot be modified 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 DR RDF PER FER BRK TDFE TEND ER R W R W R R R W R W R W R W R R R R R R R R BIt Initial value R W Note Only 0 can be written to clear the fl...

Page 1144: ...R 1 1 A framing error or parity error occurred during reception Setting conditions When the SCIF checks whether the stop bit at the end of the receive data is 1 when reception ends and the stop bit is 0 2 When in reception the number of 1 bits in the receive data plus the parity bit does not match the parity setting even or odd specified by the O E bit in SCSMR 6 TEND 1 R W 1 Transmit End Indicate...

Page 1145: ... SCFTDR after reading TDFE 1 and 0 is written to TDFE When transmit data exceeding the transmit trigger set number is written to SCFTDR by the DMAC 1 The number of transmit data bytes in SCFTDR does not exceed the transmit trigger set number Initial value Setting conditions Power on reset or manual reset When the number of SCFTDR transmit data bytes falls to or below the transmit trigger set numbe...

Page 1146: ... next from SCFRDR 1 There is a framing error that is to be read from SCFRDR Setting condition When there is a framing error in the data that is to be read next from SCFRDR 2 PER 0 R Parity Error In asynchronous mode indicates whether or not a parity error has been found in the data that is to be read next from SCFRDR 0 There is no parity error that is to be read from SCFRDR Clearing conditions Pow...

Page 1147: ...ber of receive data bytes in SCFRDR is less than the receive trigger set number Clearing conditions Power on reset or manual reset When SCFRDR is read until the number of receive data bytes in SCFRDR falls below the receive trigger set number after reading RDF 1 and 0 is written to RDF When SCFRDR is read by the DMAC until the number of receive data bytes in SCFRDR falls below the receive trigger ...

Page 1148: ...s and no further data has arrived for at least 15 etu after the stop bit of the last data received 6 Legend etu Elementary time unit time for transfer of 1 bit Notes 1 Only 0 can be written to clear the flag 2 In 2 stop bit mode only the first stop bit is checked for a value of 1 the second stop bit is not checked 3 As SCFTDR is a 64 byte FIFO register the maximum number of bytes that can be writt...

Page 1149: ... SCBRR setting is found from the following equation Asynchronous mode N 106 1 Pck0 64 22n 1 B Clocked synchronous mode N 106 1 Pck0 8 22n 1 B Where B Bit rate bits s N SCBRR setting for baud rate generator 0 N 255 Pck0 Peripheral module operating frequency MHz n Baud rate generator input clock n 0 to 3 See table 27 4 for the relation between n and the clock Table 27 4 SCSMR Settings SCSMR Setting ...

Page 1150: ...W R W R R R R R BIt Initial value R W Bit Bit Name Initial Value R W Description 15 to 11 All 0 R Reserved These bits are always read as 0 The write value should always be 0 10 9 8 RSTRG2 RSTRG1 RSTRG0 0 0 0 R W R W R W SCIF_RTS Output Active Trigger The SCIF_RTS signal becomes high when the number of receive data stored in SCFRDR exceeds the trigger number shown below 000 63 001 1 010 8 011 16 10...

Page 1151: ...L 0 R W Transmit FIFO Data Register Reset Invalidates the transmit data in the transmit FIFO data register and resets it to the empty state 0 Reset operation disabled 3 1 Reset operation enabled 1 RFCL 0 R W Receive FIFO Data Register Reset Invalidates the receive data in the receive FIFO data register and resets it to the empty state 0 Reset operation disabled 3 1 Reset operation enabled 0 LOOP 0...

Page 1152: ...ntransmitted data bytes in SCFTDR A value of H 0000 indicates that there is no transmit data and a value of H 0040 indicates that SCFTDR is full of transmit data 27 3 11 Receive FIFO Data Count Register SCRFDR SCRFDR is a 16 bit register that indicates the number of receive data bytes stored in SCFRDR SCRFDR can always be read from the CPU 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 ...

Page 1153: ...PB2 DT SPB2 IO SCK DT SCK IO CTS DT CTS IO RTS DT RTS IO R W R W R W R W R W R W R W R W R R R R R R R R BIt Initial value R W Bit Bit Name Initial Value R W Description 15 to 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7 RTSIO 0 R W Serial Port SCIF_RTS Port Input Output Specifies the serial port SCIF_RTS pin input output condition When actually setting t...

Page 1154: ...the value of the CTSIO bit The initial value of this bit after a power on reset or manual reset is undefined 0 Input output data is low level 1 Input output data is high level 3 SCKIO 0 R W Serial Port Clock Port Input Output Specifies the serial port SCIF_SCK pin input output condition When actually setting the SCIF_SCK pin as a port output pin to output the value set by the SCKDT bit the CKE1 an...

Page 1155: ...value is not output to the SCIF_TXD pin 1 SPB2DT bit value is output to the SCIF_TXD pin 0 SPB2DT R W Serial Port Break Data Specifies the serial port SCIF_RXD pin input data and SCIF_TXD pin output data The SCIF_TXD pin output condition is specified by the SPB2IO bit When the SCIF_TXD pin is designated as an output the value of the SPB2DT bit is output to the SCIF_TXD pin The SCIF_RXD pin value i...

Page 1156: ...run error occurred during reception causing abnormal termination 0 Reception in progress or reception has ended normally 2 Clearing conditions Power on reset or manual reset When 0 is written to ORER after reading ORER 1 1 An overrun error occurred during reception 3 Setting condition When the next serial reception is completed while SCFRDR receives 64 byte data SCFRDR is full Notes 1 Only 0 can b...

Page 1157: ...its indicate the number of data bytes in which a parity error occurred in the receive data stored in SCFRDR After the ER bit in SCFSR is set the value indicated by bits PER5 to PER0 is the number of data bytes in which a parity error occurred If all 64 bytes of receive data in SCFRDR have parity errors the value indicated by bits PER5 to PER0 will be 0 7 6 All 0 R Reserved These bits are always re...

Page 1158: ...wn in table 27 6 Asynchronous Mode Data length Choice of 7 or 8 bits Choice of parity addition and addition of 1 or 2 stop bits the combination of these parameters determines the transfer format and character length Detection of framing errors parity errors receive FIFO data full state overrun errors receive data ready state and breaks during reception Indication of the number of data bytes stored...

Page 1159: ... 0 1 bit 0 1 1 8 bit data Yes 2 bits 0 0 1 bit 1 No 2 bits 0 1 bit 0 1 1 1 Asynchronous mode 7 bit data Yes 2 bits 1 x x x Clocked synchronous mode 8 bit data No No Note x Don t care Table 27 6 SCSMR and SCSCR Settings for SCIF Clock Source Selection SCSMR SCSCR Settings Bit 7 C A Bit 1 CKE1 Bit 0 CKE0 Mode Clock Source SCK Pin Function 0 SCIF does not use SCIF_SCK pin 0 1 Internal Outputs clock w...

Page 1160: ...n In asynchronous serial communication the transmission line is usually held in the mark state high level The SCIF monitors the transmission line and when it goes to the space state low level recognizes a start bit and starts serial communication One character in serial communication consists of a start bit low level followed by transmit receive data LSB first from the lowest bit a parity bit high...

Page 1161: ...ording to the SCSMR settings Table 27 7 Serial Transfer Formats Asynchronous Mode SCSMR Settings Serial Transfer Format and Frame Length CHR PE STOP 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 S 8 bit data STOP 0 0 1 S 8 bit data STOP STOP 0 1 0 S 8 bit data P STOP 0 1 1 S 8 bit data P STOP STOP 1 0 0 S 7 bit data STOP 1 0 1 S 7 bit data STOP STOP 1 1 0 S 7 bit data P STOP 1 1 1 S 7 bit data P STOP STOP Lege...

Page 1162: ...receiving data it is necessary to clear the TE and RE bits in SCSCR to 0 then initialize the SCIF as described below When the operating mode or transfer format etc is changed the TE and RE bits must be cleared to 0 before making the change using the following procedure 1 When the TE bit is cleared to 0 SCTSR is initialized Note that clearing the TE and RE bits to 0 does not change the contents of ...

Page 1163: ... to 0 Set TE and RE bits in SCSCR to 1 and set TIE RIE and REIE bits End of initialization Wait No Yes Set the clock selection in SCSCR Be sure to clear bits TIE RIE TE and RE to 0 Set the data transfer format in SCSMR Write a value corresponding to the bit rate into SCBRR Not necessary if an external clock is used Wait at least one bit interval then set the TE bit or RE bit in SCSCR to 1 Also set...

Page 1164: ...ck and transmit data write Read SCFSR and check that the TDFE flag is set to 1 then write transmit data to SCFTDR and clear the TDFE and TEND flags to 0 The number of transmit data bytes that can be written is 64 transmit trigger set number write 2 Serial transmission continuation procedure To continue serial transmission read 1 from the TDFE flag to confirm that writing is possible then write dat...

Page 1165: ...in SCSCR is set to 1 at this time a transmit FIFO data empty interrupt TXI request is generated The serial transmit data is sent from the SCIF_TXD pin in the following order a Start bit One 0 bit is output b Transmit data 8 bit or 7 bit data is output in LSB first order c Parity bit One parity bit even or odd parity is output A format in which a parity bit is not output can also be selected d Stop...

Page 1166: ...rrupt request Figure 27 10 Sample SCIF Transmission Operation Example with 8 Bit Data Parity One Stop Bit 4 When modem control is enabled transmission can be stopped and restarted in accordance with the SCIF_CTS input value When SCIF_CTS is set to 1 during transmission the line goes to the mark state after transmission of one frame When SCIF_CTS is set to 0 the next transmit data is output startin...

Page 1167: ...BRK flags in SCFSR and the ORER flag in SCLSR to identify any error perform the appropriate error handling then clear the DR ER BRK and ORER flags to 0 In the case of a framing error a break can also be detected by reading the value of the SCIF_RXD pin 2 SCIF status check and receive data read Read SCFSR and check that RDF 1 then read the receive data in SCFRDR read 1 from the RDF flag and then cl...

Page 1168: ...Yes Yes No Overrun error handling ORER 1 Yes No No No 1 Whether a framing error or parity error has occurred in the receive data that is to be read from SCFRDR can be ascertained from the FER and PER bits in SCFSR 2 When a break signal is received receive data is not transferred to SCFRDR while the BRK flag is set However note that the last data in SCFRDR is H 00 and the break data in which a fram...

Page 1169: ... that the break state is not set If b c and d checks are passed the receive data is stored in SCFRDR Note Reception continues even when a parity error or framing error occurs 4 If the RIE bit in SCSCR is set to 1 when the RDF or DR flag changes to 1 a receive FIFO data full interrupt RXI request is generated If the RIE bit or REIE bit in SCSCR is set to 1 when the ER flag changes to 1 a receive er...

Page 1170: ...y bit Stop bit Start bit Figure 27 14 Sample Operation Using Modem Control SCIF0_RTS Only in Channel 0 27 4 3 Operation in Clocked Synchronous Mode Clocked synchronous mode in which data is transmitted or received in synchronization with clock pulses is suitable for fast serial communication Since the transmitter and receiver are independent units in the SCIF full duplex communication can be achie...

Page 1171: ...and the CKE1 and CKE0 bits in SCSCR For details of SCIF clock source selection see table 27 6 When the SCIF is operated on an internal clock the synchronization clock is output from the SCIF_SCK pin Eight synchronization clock pulses are output in the transfer of one character and when no transfer is performed the clock is fixed high When an internal clock is selected in a receive operation only a...

Page 1172: ...ation almost ends Be sure to clear the TIE RIE TE and RE bits to 0 Set the CKE1 and CKE0 bits Set the data transfer format in SCSMR Write a value corresponding to the bit rate into SCBRR This is not necessary if an external clock is used Wait at least one bit interval after this write before moving to the next step Set the external pins to be used Set SCIF_RXD input for reception and SCIF_TXD outp...

Page 1173: ...to SCFTDR and clear the TDFE flag to 0 The transition of the TDFE flag from 0 to 1 can also be identified by a TXI interrupt 3 Serial transmission continuation procedeure To continue serial transmission read 1 from the TDFE flag to confirm that writing is possible them write data to SCFTDR and then clear the TDFE flag to 0 1 3 2 Figure 27 17 Sample Serial Transmission Flowchart In serial transmiss...

Page 1174: ...e timing for sending the last bit If data is present the data is transferred from SCFTDR to SCTSR and then serial transmission of the next frame is started If there is no transmit data the TEND flag in SCFSR is set to 1 after the last bit is sent and the transmit data pin SCIF_TXD pin retains the output state of the last bit 4 After serial transmission ends the CLK pin is fixed high Figure 27 18 s...

Page 1175: ...of reception Yes No Yes Yes No No Error handling 1 SCIF initialization See Sample SCIF Initialization Flowchart in figure 27 16 2 Receive error handling Read the ORER flag in SCLSR to identify any error perform the appropriate error handling then clear the ORER flag to 0 Transmission reception cannot be resumed while the ORER flag is set to 1 3 SCIF status check and receive data read Read SCFSR an...

Page 1176: ... output of the synchronization clock 2 The received data is stored in SCRSR in LSB to MSB order After receiving the data the SCIF checks whether the receive data can be transferred from SCRSR to SCFRDR If this check is passed the receive data is stored in SCFRDR If an overrun error is detected in the error check reception cannot continue 3 If the RIE bit in SCSCR is set to 1 when the RDF flag chan...

Page 1177: ... reception in clocked synchronous mode Synchronization clock Serial data RDF ORER Data read from SCFRDR and RDF flag cleared to 0 by RXI interrupt handler One frame Bit 7 LSB RXI interrupt request MSB Bit 0 Bit 6 Bit 7 Bit 7 Bit 0 Bit 1 RXI interr upt BRI interrupt request by overrun error Figure 27 20 Sample SCIF Reception Operation in Clocked Synchronous Mode ...

Page 1178: ...to 0 The transition of the TDFE flag from 0 to 1 can also be identified by a TXI interrupt 3 Receive error handling Read the ORER flag in SCLSR to identify any error perform the appropriate error handling then clear the ORER flag to 0 Transmission reception cannot be resumed while the ORER flag is set to 1 4 SCIF status check and receive data read Read SCFSR and check that RDF 1 then read the rece...

Page 1179: ...orm data transfer If the RDF or DR flag in SCFSR is set to 1 when an RXI interrupt is enabled by the RIE bit an RXI interrupt request and a receive FIFO data full request for DMA transfer are generated If the RDF or DR flag is set to 1 when an RXI interrupt is disabled by the RIE bit only a receive FIFO data full request for DMA transfer is generated A receive FIFO data full request can activate t...

Page 1180: ...ease ERI Interrupt initiated by receive error flag ER Not possible High RXI Interrupt initiated by receive FIFO data full flag RDF or receive data ready flag DR Possible BRI Interrupt initiated by break flag BRK or overrun error flag ORER Not possible TXI Interrupt initiated by transmit FIFO data empty flag TDFE Possible Low Note An RXI interrupt by setting of the DR flag is available only in asyn...

Page 1181: ...eading and the RDF Flag The RDF flag in SCFSR is set when the number of receive data bytes in SCFRDR has become equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in SCFCR After RDF is set receive data equivalent to the trigger number can be read from SCFRDR allowing efficient continuous reception However if the number of data bytes read in SCFRDR is equal to or greate...

Page 1182: ...ing low level and then clear the TE bit to 0 halting transmission When the TE bit is cleared to 0 the transmitter is initialized regardless of the current transmission state and 0 is output from the SCIF_TXD pin 5 Receive Data Sampling Timing and Receive Margin in Asynchronous Mode In asynchronous mode the SCIF operates on a base clock with a frequency of 16 times the bit rate In reception the SCI...

Page 1183: ... formula 2 When D 0 5 and F 0 M 0 5 1 2 16 100 46 875 2 However this is a theoretical value A reasonable margin to allow in system designs is 20 to 30 6 When Using the DMAC When using an external clock as the synchronization clock after SCFTDR is updated by the DMAC an external clock should be input after at least five peripheral clock Pck cycles A malfunction may occur when the transfer clock is ...

Page 1184: ...Section 27 Serial Communication Interface with FIFO SCIF Rev 1 00 Oct 01 2007 Page 1118 of 1956 REJ09B0256 0100 ...

Page 1185: ...Features The SCIF IrDA has the following features Infrared data communication function Infrared data communication compliant with the IrDA standard 1 0 can be performed This function modulates and demodulates the data format supported by serial communication to the data format supported by infrared data communication Asynchronous serial communication mode Serial data communication is executed usin...

Page 1186: ... continuous serial data transmission and reception The LSB is transmitted and received first LSB first On chip baud rate generator allows any bit rate to be selected Choice of clock source internal clock from the baud rate generator based on the peripheral clock Pck0 or external clock from the SCIF2_SCK pin Four interrupt sources There are four interrupt sources transmit FIFO data empty break rece...

Page 1187: ...e FIFO data register Transmit shift register Transmit FIFO data register Serial mode register Serial control register Serial status register SCBRR2 SCSPTR2 SCFCR2 SCLSR2 BRGDL2 BRGCKS2 SCSMRIR Bit rate register Serial port register FIFO control register Line status register BRG frequency division register BRG clock select register IrDA serial mode register SCTSR2 SCFRDR2 16 stage SCRSR2 SCSMR2 SCL...

Page 1188: ... to SCSPTR SPTRR Read from SCSPTR Note Clock output enable signal Serial clock output signal Serial clock input signal Serial clock input enable signal The SCIF2_CLK pin function is designated as internal clock output or external clock input by the C A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR K Figure 28 2 SCIF2_SCK Pin SCIF2_TXD Reset Peripheral bus SPTRW D1 D0 R Q D SPB2IO C Reset SPTRW ...

Page 1189: ...Table 28 1 Pin Configuration Pin Name Function I O Description SCIF2_SCK Serial clock pin I O Clock input output SCIF2_RXD Receive data pin Input Receive data input SCIF2_TXD Transmit data pin Output Transmit data output Notes These pins are made to function as serial pins by performing SCIF operation settings with the C A bit in SCSMR and the TE RE CKE1 and CKE0 bits in SCSCR Break state transmis...

Page 1190: ... FIFO data register 2 SCFTDR2 W H FFE1 000C H 1FE1 000C 8 Serial status register 2 SCFSR2 R W 1 H FFE1 0010 H 1FE1 0010 16 Receive FIFO data register 2 SCFRDR2 R H FFE1 0014 H 1FE1 0014 8 FIFO control register 2 SCFCR2 R W H FFE1 0018 H 1FE10018 16 FIFO data count register 2 SCFDR2 R H FFE1 001C H 1FE1 001C 16 Serial port register 2 SCSPTR2 R W H FFE1 0020 H 1FE1 0020 16 Line status register 2 SCL...

Page 1191: ...R2 Undefined Undefined Retained Retained Serial status register 2 SCFSR2 H 0060 H 0060 Retained Retained Receive FIFO data register 2 SCFRDR2 Undefined Undefined Retained Retained FIFO control register 2 SCFCR2 H 0000 H 0000 Retained Retained FIFO data count register 2 SCFDR2 H 0000 H 0000 Retained Retained Serial port register 2 SCSPTR2 H 0000 H 0000 Retained Retained Line status register 2 SCLSR...

Page 1192: ... 28 3 2 Receive FIFO Data Register SCFRDR SCFRDR is an 8 bit FIFO register of 16 stages that stores received serial data When the SCIF has received one byte of serial data it transfers the received data from SCRSR to SCFRDR where it is stored and completes the receive operation SCRSR is then enabled for reception and consecutive receive operations can be performed until SCFRDR is full 16 data byte...

Page 1193: ...started automatically SCTSR cannot be directly read from and written to by the CPU 0 1 2 3 4 5 6 7 Bit Initial value R W 28 3 4 Transmit FIFO Data Register SCFTDR SCFTDR is an 8 bit FIFO register of 16 stages that stores data for serial transmission If SCTSR is empty when transmit data has been written to SCFTDR the SCIF transfers the transmit data written in SCFTDR to SCTSR and starts serial tran...

Page 1194: ...A R W R W R R W R W R W R W R W R R R R R R R R Bit Initial value R W Bit Bit Name Initial Value R W Description 15 to 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7 C A 0 R W Communication Mode Selects asynchronous mode or clocked synchronous mode as the SCIF operating mode 0 Asynchronous mode 1 Clocked synchronous mode 6 CHR 0 R W Character Length Selects...

Page 1195: ...bit 4 O E 0 R W Parity Mode Selects either even or odd parity for use in parity addition and checking In asynchronous mode the O E bit setting is only valid when the PE bit is set to 1 enabling parity bit addition and checking In clocked synchronous mode or when parity addition and checking is disabled in asynchronous mode the O E bit setting is invalid 0 Even parity 1 Odd parity When even parity ...

Page 1196: ...ated as the start bit of the next transmit character Note 1 In transmission a single 1 bit stop bit is added to the end of a transmit character before it is sent 2 In transmission two 1 bits stop bits are added to the end of a transmit character before it is sent 2 0 R Reserved This bit is always read as 0 The write value should always be 0 1 0 CKS1 CKS0 0 0 R W R W Clock Select 1 and 0 These bits...

Page 1197: ...itial Value R W Description 15 to 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7 TIE 0 R W Transmit Interrupt Enable Enables or disables transmit FIFO data empty interrupt TXI request generation when serial transmit data is transferred from SCFTDR to SCTSR the number of data bytes in SCFTDR falls to or below the transmit trigger set number and the TDFE flag...

Page 1198: ... BRI request disabled 1 Receive data full interrupt RXI request receive error interrupt ERI request and break interrupt BRI request enabled Note An RXI interrupt request can be cleared by reading 1 from the RDF or DR flag then clearing the flag to 0 or by clearing the RIE bit to 0 ERI and BRI interrupt requests can be cleared by reading 1 from the ER BRK or ORER flag then clearing the flag to 0 or...

Page 1199: ...the reception format decided and the receive FIFO reset before the RE bit is set to 1 3 REIE 0 R W Receive Error Interrupt Enable Enables or disables generation of receive error interrupt ERI and break interrupt BRI requests The REIE bit setting is valid only when the RIE bit is 0 Receive error interrupt ERI and break interrupt BRI requests can be cleared by reading 1 from the ER BRK or ORER flag ...

Page 1200: ...F clock source CKE1 0 When an external clock is selected CKE1 1 the CKE0 bit setting is invalid In clock synchronous mode to select synchronization clock output set the C A bit in SCSMR to 1 then set the CKE1 and CKE0 bits Asynchronous mode 00 The SCIF_SCK pin is not used The SCIF_SCK pin functions as an input pin Input signals are ignored 01 The SCIF_SCK pin functions as clock output 1 10 Externa...

Page 1201: ... 7 8 9 10 11 12 13 15 14 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 DR RDF PER FER BRK TDFE TEND ER FERN 3 0 PERN 3 0 R R R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R R R R R R R R Bit Initial value R W Bit Bit Name Initial Value R W Description 15 to 12 PERN 3 0 All 0 R Number of Parity Errors These bits indicate the number of parity errors in data received and stored in SCFRDR After the ER bit in SCFSR is set the...

Page 1202: ... reading ER 1 1 A framing error or parity error occurred during reception Setting conditions When the SCIF checks whether the stop bit at the end of the receive data is 1 when reception ends and the stop bit is 0 2 When in reception the number of 1 bits in the receive data plus the parity bit does not match the parity setting even or odd specified by the O E bit in SCSMR 6 TEND 1 R W 1 Transmit En...

Page 1203: ...written to SCFTDR after reading TDFE 1 and 0 is written to TDFE When transmit data exceeding the transmit trigger set number is written to SCFTDR by the DMAC 1 The number of transmit data bytes in SCFTDR does not exceed the transmit trigger set number Initial value Setting conditions Power on reset or manual reset When the number of SCFTDR transmit data bytes falls to or below the transmit trigger...

Page 1204: ...to be read next from SCFRDR 1 There is a framing error that is to be read from SCFRDR Setting condition When there is a framing error in the data that is to be read next from SCFRDR 2 PER 0 R Parity Error In asynchronous mode indicates whether or not a parity error has been found in the data that is to be read next from SCFRDR 0 There is no parity error that is to be read from SCFRDR Clearing cond...

Page 1205: ... 0 The number of receive data bytes in SCFRDR is less than the receive trigger set number Clearing conditions Power on reset or manual reset When SCFRDR is read until the number of receive data bytes in SCFRDR falls below the receive trigger set number after reading RDF 1 and 0 is written to RDF When SCFRDR is read by the DMAC until the number of receive data bytes in SCFRDR falls below the receiv...

Page 1206: ...e data bytes and no further data has arrived for at least 15 etu after the stop bit of the last data received 6 Legend etu Elementary time unit time for transfer of 1 bit Notes 1 Only 0 can be written to clear the flag 2 In 2 stop bit mode only the first stop bit is checked for a value of 1 the second stop bit is not checked 3 As SCFTDR is a 16 byte FIFO register the maximum number of bytes that c...

Page 1207: ...nded for Pck0 Pck0 4 Pck0 16 and Pck0 64 For details on the baud rate generator for external clock see section 28 6 Baud Rate Generator for External Clock BRG The SCBRR setting is found from the following equation Asynchronous mode N 106 1 Pck0 64 22n 1 B Clocked synchronous mode N 106 1 Pck0 8 22n 1 B Where B Bit rate bits s N SCBRR setting for baud rate generator 0 N 255 Pck0 Peripheral module o...

Page 1208: ...ten to by the CPU 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOOP RFCL TFCL TTRG 1 0 RTRG 1 0 R W R W R W R W R W R W R W R R R R R R R R R Bit Initial value R W Bit Bit Name Initial Value R W Description 15 to 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7 6 RTRG 1 0 All 0 R W Receive FIFO Data Number Trigger These bits are used ...

Page 1209: ...its are always read as 0 The write value should always be 0 2 TFRST 0 R W Transmit FIFO Data Register Reset Invalidates the transmit data in the transmit FIFO data register and resets it to the empty state 0 Reset operation disabled 1 Reset operation enabled Note A reset operation is performed in the event of a power on reset or manual reset 1 RFRST 0 R W Receive FIFO Data Register Reset Invalidat...

Page 1210: ...ame Initial Value R W Description 15 to 13 All 0 R Reserved These bits are always read as 0 The write value should always be 0 12 to 8 TDN 4 0 All 0 R These bits show the number of untransmitted data bytes in SCFTDR A value of H 00 indicates that there is no transmit data and a value of H 10 indicates that SCFTDR is full of transmit data 16 bytes 7 to 5 All 0 R Reserved These bits are always read ...

Page 1211: ...W R W R R R R 0 0 0 0 R R R R R R R R Bit Initial value R W Bit Bit Name Initial Value R W Description 15 to 4 All 0 R Reserved These bits are always read as 0 The write value should always be 0 3 SCKIO 0 R W Serial Port Clock Port Input Output Specifies the serial port SCIF_SCK pin input output condition When actually setting the SCIF_SCK pin as a port output pin to output the value set by the SC...

Page 1212: ...PB2DT bit value is not output to the SCIF_TXD pin 1 SPB2DT bit value is output to the SCIF_TXD pin 0 SPB2DT R W Serial Port Break Data Specifies the serial port SCIF_RXD pin input data and SCIF_TXD pin output data The SCIF_TXD pin output condition is specified by the SPB2IO bit When the SCIF_TXD pin is designated as an output the value of the SPB2DT bit is output to the SCIF_TXD pin The SCIF_RXD p...

Page 1213: ...r reception has ended normally 2 Clearing conditions Power on reset or manual reset When 0 is written to ORER after reading ORER 1 1 An overrun error occurred during reception 3 Setting condition When the next serial reception is completed while SCFRDR receives 16 byte data SCFRDR is full Notes 1 Only 0 can be written to clear the flag 2 The ORER flag is not affected and retains its previous state...

Page 1214: ...ratios when a 3 686 MHz crystal resonator is used 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRGDL 15 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W BIt Initial value R W Bit Bit Name Initial Value R W Description 15 to 0 BRGDL 15 0 All 0 R W Division Ratio of BRG Generated Clock These bits specify the division ratio of the division clocks generated by...

Page 1215: ...hes output clock between the division clock generated by the BRG and the external clock SCIF2_SCK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRG CKS R R R R R R R R R R R R R R R W R Bit Initial value R W Bit Bit Name Initial Value R W Description 15 BRGCKS 0 R W Switches output clock between the division clock and external clock SCIF2_SCK 0 Selects division clock 1 Sele...

Page 1216: ... R R R R R R R W LOOP R W IRMOD R W R BIt Initial value R W Bit Bit Name Initial Value R W Description 31 to 10 All 0 R Reserved These bits are always read as 0 The write value should always be 0 9 EDGEN 0 R W SCIF2_RXD Pin Sampling Mode 0 The SCIF2_RXD pin is sample by an edge 1 The SCIF2_RXD pin is sample by both an edge and level 8 LOOP 0 R W IrDA Loop back Test 0 Normal operation 1 Loop back o...

Page 1217: ...ned by the combination of the C A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR as shown in Table 28 7 Asynchronous Mode Data length Choice of 7 or 8 bits Choice of parity addition and addition of 1 or 2 stop bits the combination of these parameters determines the transfer format and character length Detection of framing errors parity errors receive FIFO data full state overrun errors receive d...

Page 1218: ...te generator clock and a serial clock is output to external devices When external clock SCIF_SCK is selected The on chip baud rate generator is not used and the SCIF operates on the input serial clock Table 28 6 SCSMR Settings for Serial Transfer Format Selection SCSMR Settings SCIF Transfer Format Bit 7 C A Bit 6 CHR Bit 5 PE Bit 3 STOP Mode Data Length Parity Bit Stop Bit Length 0 1 bit 0 1 No 2...

Page 1219: ... SCK pin inputs the clock with a frequency 16 times the bit rate When SC_CLK is selected the SCK pin inputs the clock Input signals are ignored 1 0 Asynchronous Input SC_CLK to baud rate generator for external clock SCIF_CLK Pck0 or SCK switched by baud rate generator s CKS register Set the SCK input or SC_CLK so that the frequency of BRGCLK is 16 times the bit rate When selecting SC_CLK set the f...

Page 1220: ...Bit 7 Bit 1 Bit 0 C A CKE1 CKE0 Mode Clock Source Description of SCK Pin SCK input switched by baud rate generator s CKS register The SCK pin outputs the synchronization clock 1 0 Clock synchronous Input SC_CLK to baud rate generator for external clock SCIF_CLK Pck0 SC_CLK cannot be used as an input clock for synchronous communication 1 1 1 Prohibited ...

Page 1221: ...mmunication In asynchronous serial communication the transmission line is usually held in the mark state high level The SCIF monitors the transmission line and when it goes to the space state low level recognizes a start bit and starts serial communication One character in serial communication consists of a start bit low level followed by transmit receive data LSB first from the lowest bit a parit...

Page 1222: ...lected according to the SCSMR settings Table 28 8 Serial Transfer Formats Asynchronous Mode SCSMR Settings Serial Transfer Format and Frame Length CHR PE STOP 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 S 8 bit data STOP 0 0 1 S 8 bit data STOP STOP 0 1 0 S 8 bit data P STOP 0 1 1 S 8 bit data P STOP STOP 1 0 0 S 7 bit data STOP 1 0 1 S 7 bit data STOP STOP 1 1 0 S 7 bit data P STOP 1 1 1 S 7 bit data P STOP...

Page 1223: ...ting and receiving data it is necessary to clear the TE and RE bits in SCSCR to 0 then initialize the SCIF as described below When the operating mode or transfer format etc is changed the TE and RE bits must be cleared to 0 before making the change using the following procedure 1 When the TE bit is cleared to 0 SCTSR is initialized Note that clearing the TE and RE bits to 0 does not change the con...

Page 1224: ...SCSCR to 1 and set TIE RIE and REIE bits End of initialization Wait No Yes Set the clock selection in SCSCR Be sure to clear bits TIE RIE TE and RE to 0 Set the data transfer format in SCSMR Write a value corresponding to the bit rate into SCBRR Not necessary if an external clock is used Wait at least one bit interval then set the TE bit or RE bit in SCSCR to 1 Also set the RIE REIE and TIE bits S...

Page 1225: ...nsmit data write Read SCFSR and check that the TDFE flag is set to 1 then write transmit data to SCFTDR and clear the TDFE and TEND flags to 0 The number of transmit data bytes that can be written is 16 transmit trigger set number 2 Serial transmission continuation procedure To continue serial transmission read 1 from the TDFE flag to confirm that writing is possible then write data to SCFTDR and ...

Page 1226: ...e TIE bit in SCSCR is set to 1 at this time a transmit FIFO data empty interrupt TXI request is generated The serial transmit data is sent from the SCIF_TXD pin in the following order a Start bit One 0 bit is output b Transmit data 8 bit or 7 bit data is output in LSB first order c Parity bit One parity bit even or odd parity is output A format in which a parity bit is not output can also be selec...

Page 1227: ... mode 1 0 D0 D1 D7 0 1 1 0 D0 D1 D7 0 1 1 1 TDFE flag Serial data SCIF_TXD TEND flag Start bit Data Parity bit Stop bit Start bit Idle state mark state Data Parity bit Stop bit TXI interrupt request Data written to SCFTDR and TDFE flag read as 1 then cleared to 0 by TXI interrupt handler One frame TXI interrupt request Figure 28 8 Sample SCIF Transmission Operation Example with 8 Bit Data Parity O...

Page 1228: ...ad the DR ER and BRKflags in SCFSR and the ORER flag in SCLSR to identify any error perform the appropriate error handling then clear the DR ER BRK and ORER flags to 0 In thecase of a framing error a break can also be detected by reading the value of the SCIF_RXD pin 2 SCIF status check and receive data read Read SCFSR and check that RDF 1 then read the receive data in SCFRDR read 1 from the RDF f...

Page 1229: ... 1 Break handling DR 1 Read receive data in SCFRDR Clear DR ER BRK flags in SCFSR and ORER flag in SCLSR to 0 End Yes Yes Yes No Overrun error handling ORER 1 Yes No No No 1 Whether a framing error or parity error has occurred in the receive data that is to be read from SCFRDR can be ascertained from the FER and PER bits in SCFSR Figure 28 10 Sample Serial Reception Flowchart 2 ...

Page 1230: ...hecks whether receive data can be transferred from SCRSR to SCFRDR c Overrun error check The SCIF checks that the ORER flag is 0 indicating that no overrun error has occurred d Break check The SCIF checks that the BRK flag is 0 indicating that the break state is not set If b c and d checks are passed the receive data is stored in SCFRDR Note Reception continues even when a parity error or framing ...

Page 1231: ...tion in Clocked Synchronous Mode Clocked synchronous mode in which data is transmitted or received in synchronization with clock pulses is suitable for fast serial communication Since the transmitter and receiver are independent units in the SCIF full duplex communication can be achieved by sharing the clock Both the transmitter and receiver have a 16 stage FIFO buffer structure so that data can b...

Page 1232: ...o the settings of the C A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR For details of SCIF clock source selection see table 28 7 When the SCIF is operated on an internal clock the synchronization clock is output from the SCIF_SCK pin Eight synchronization clock pulses are output in the transfer of one character and when no transfer is performed the clock is fixed high When an internal clock is...

Page 1233: ...s in SCSCR to 1 and set TIE RIE and REIE bits End of initialization Wait No Yes Leave the TE and RE bits cleared to 0 until the initialization almost ends Set the CKE1 and CKE0 bits Set the data transfer receive format in SCSMR Write a value corresponding to the bit rate into SCBRR This is not necessary if an external clock is used Wait at least one bit interval after this write before moving to t...

Page 1234: ...DR by the DMAC the TEND flag may no be cleared Therefore if the DMAC is used for transmission in clock synchronous mode read the TEND flag in the following method 1 Confirm data transfer completion on the DMAC side 2 Read the TEND flag 3 Clear the TEND flag to 0 when TEND 1 4 Read the TEND flag again 5 Use the TEND flag read for the second time No Yes No Yes No Yes 1 SCIF initialization See sample...

Page 1235: ...rrupt TXI request is generated When the external clock is selected data is output in synchronization with the input clock The serial transmit data is sent from the SCIF_TXD pin in the LSB first order 3 The SCIF checks the SCFTDR transmit data at the timing for sending the last bit If data is present the data is transferred from SCFTDR to SCTSR and then serial transmission of the next frame is star...

Page 1236: ...on See Sample SCIF Initialization Flowchart in figure 28 13 2 Receive error handling Read the ORER flag in SCLSR to identify any error perform the appropriate error handling then clear the ORER flag to 0 Transmission reception cannot be resumed while the ORER flag is set to 1 3 SCIF status check and receive data read Read SCFSR and check that RDF 1 then read the receive data in SCFRDR and clear th...

Page 1237: ...e input or output of the synchronization clock 2 The received data is stored in SCRSR in LSB to MSB order After receiving the data the SCIF checks whether the receive data can be transferred from SCRSR to SCFRDR If this check is passed the receive data is stored in SCFRDR If an overrun error is detected in the error check reception cannot continue 3 If the RIE bit in SCSCR is set to 1 when the RDF...

Page 1238: ...ception in clocked synchronous mode Synchronization clock Serial data SCIF_RXD RDF flag ORER flag Data read from SCFRDR and RDF flag cleared to 0 by RXI interrupt handler One frame Bit 7 LSB RXI interrupt request MSB Bit 0 Bit 6 Bit 7 Bit 7 Bit 0 Bit 1 RXI interrupt request BRI interrupt request by overrun error Figure 28 18 Sample SCIF Reception Operation in Clocked Synchronous Mode ...

Page 1239: ...TDFE flag to 0 The transition of the TDFE flag from 0 to 1 can also be identified by a TXI interrupt 3 Receive error handling Read the ORER flag in SCLSR to identify any error perform the appropriate error handling then clear the ORER flag to 0 Transmission reception cannot be resumed while the ORER flag is set to 1 4 SCIF status check and receive data read Read SCFSR and check that RDF 1 then rea...

Page 1240: ...MAC to perform data transfer If the RDF or DR flag in SCFSR is set to 1 when an RXI interrupt is enabled by the RIE bit an RXI interrupt request and a receive FIFO data full request for DMA transfer are generated If the RDF or DR flag is set to 1 when an RXI interrupt is disabled by the RIE bit only a receive FIFO data full request for DMA transfer is generated A receive FIFO data full request can...

Page 1241: ... Reset Release ERI Interrupt initiated by receive error flag ER Not possible High RXI Interrupt initiated by receive FIFO data full flag RDF or receive data ready flag DR Possible BRI Interrupt initiated by break flag BRK or overrun error flag ORER Not possible TXI Interrupt initiated by transmit FIFO data empty flag TDFE Possible Low Note An RXI interrupt by setting of the DR flag is available on...

Page 1242: ... 2 SCFRDR Reading and the RDF Flag The RDF flag in SCFSR is set when the number of receive data bytes in SCFRDR has become equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in SCFCR After RDF is set receive data equivalent to the trigger number can be read from SCFRDR allowing efficient continuous reception However if the number of data bytes read in SCFRDR is equal t...

Page 1243: ...to 0 designating low level and then clear the TE bit to 0 halting transmission When the TE bit is cleared to 0 the transmitter is initialized regardless of the current transmission state and 0 is output from the SCIF_TXD pin 5 Receive Data Sampling Timing and Receive Margin in Asynchronous Mode In asynchronous mode the SCIF operates on a base clock with a frequency of 16 times the bit rate In rece...

Page 1244: ...to 30 6 Reception margin and baud rate error The 46 875 in formula 2 is the reception margin when the baud rate error is 0 F 0 In other words reception is possible even with a misalignment of approximately half a bit if there is no reception or transmission baud rate error If baud rate error is present in reception or transmission the error accumulates until the stop bit is received reducing the r...

Page 1245: ...ts demodulates the infrared communication data transmitted from the infrared sensor emitter to the SCIF2_RXD pin into the data format used by the serial data communication and transmits the data to the SCIF2 channel 28 5 1 Infrared Data Communication Format Figure 28 21 shows the data format used by the infrared data communication Transmit data from SCIF2 chaannel Transmit data to SCIF2_TXD pin in...

Page 1246: ...is bypassed to the SCIF2_TXD SCIF2_RXD pin When the LOOP bit in SCSMRIR is set to active output from the infrared data modulation unit is directly input to the demodulation unit for loopback testing The selector does not use clocks for its logic Therefore the status of the selector after a reset or in standby depends on only the value of SCSMRIR Note This module can detect short pulses such as cha...

Page 1247: ...IrDA block with a sampling clock BRGCLK which is derived from the external clock SCIF_CLK or internal clock Pck0 divided by the division ratio from 1 through 2 to the sixteenth power minus 1 28 6 1 BRG Block Diagram Figure 28 23 shows a block diagram of the BRG SC_CLK selected from among SCIF_CLK and Pck0 Infrared data Communication Inteface IrDA BRGCLK IO BUS IF SCIF_SCK BRG block SCIF IrDA Base ...

Page 1248: ...rator The trigger generator generates rising edge falling edge triggers for a frequency divided clock taking timing according to values of the frequency division register and base counter The triggers generate the frequency divided clock The trigger generator also switches the output between SCIF2_CLK external clock input and the frequency divided clock 28 6 2 Restrictions on the BRG 1 Notes on Fr...

Page 1249: ...nput SCIF Register Bit Name Setting Value BRG Register Name Setting Value SCSMR C A 0 BSGCKS2 0000 SCSCR CKE1 1 BSGDL2 1 to FFFF Asynchronous mode SCK external input SCIF Register Bit Name Setting Value BRG Register Name Setting Value SCSMR C A 0 BSGCKS2 8000 SCSCR 1 BSGDL2 Don t care Clock synchronous mode external input SCIF Register Bit Name Setting Value BRG Register Name Setting Value SCSMR 1...

Page 1250: ...Section 28 Serial Communication Interface with FIFO IrDA Interface SCIF IrDA Rev 1 00 Oct 01 2007 Page 1184 of 1956 REJ09B0256 0100 ...

Page 1251: ...other Supports 8 bit data 16 bit data 16 bit stereo audio input output MSB first for data transmission Supports a maximum of 48 kHz sampling rate Synchronization by either frame synchronization pulse or left right channel switch Supports CODEC control data interface Connectable to linear audio or A Law or µ Law CODEC chip Supports both master and slave modes Serial clock An external pin input or p...

Page 1252: ...f the SIOF P S S P Pck0 1 nMCLK SIOF_MCLK SIOF_SCK SIOF_SYNC SIOF_TXD SIOF_RXD Timing control SIOF interrupt request SIOFI Peripheral bus Bus interface Control registers Transmit FIFO 32 bits 16 stages Receive FIFO 32 bits 16 stages Transmit control data Receive control data Baud rate generator Figure 29 1 Block Diagram of SIOF ...

Page 1253: ... data pin 0 SIOF0_RXD Receive data Input Receive data pin SIOF1_MCLK Master clock Input Master clock input pin SIOF1_SCK Serial clock I O Serial clock pin common to transmission reception SIOF1_SYNC Frame synchronous signal I O Frame synchronous signal common to transmission reception SIOF1_TXD Transmit data Output Transmit data pin 1 SIOF1_RXD Receive data Input Receive data pin SIOF2_MCLK Master...

Page 1254: ... H 1FE3 000C 16 FIFO control register 0 SIFCTR0 R W H FFE3 0010 H 1FE3 0010 16 Status register 0 SISTR0 R W H FFE3 0014 H 1FE3 0014 16 Interrupt enable register 0 SIIER0 R W H FFE3 0016 H 1FE3 0016 16 Transmit data register 0 SITDR0 W H FFE3 0020 H 1FE3 0020 32 Receive data register 0 SIRDR0 R H FFE3 0024 H 1FE3 0024 32 Transmit control data register 0 SITCR0 R W H FFE3 0028 H 1FE3 0028 32 0 Recei...

Page 1255: ...sign register 2 SITDAR2 R W H FFE4 0004 H 1FE4 0004 16 Receive data assign register 2 SIRDAR2 R W H FFE4 0006 H 1FE4 0006 16 Control data assign register 2 SICDAR2 R W H FFE4 0008 H 1FE4 0008 16 Control register 2 SICTR2 R W H FFE4 000C H 1FE4 000C 16 FIFO control register 2 SIFCTR2 R W H FFE4 0010 H 1FE4 0010 16 Status register 2 SISTR2 R W H FFE4 0014 H 1FE4 0014 16 Interrupt enable register 2 S...

Page 1256: ...R0 H xxxx xxxx H xxxx xxxx Retained Retained Transmit control data register 0 SITCR0 H 0000 0000 H 0000 0000 Retained Retained 0 Receive control data register 0 SIRCR0 H xxxx xxxx H xxxx xxxx Retained Retained Mode register 1 SIMDR1 H 8000 H 8000 Retained Retained Clock select register 1 SISCR1 H C000 H C000 Retained Retained Transmit data assign register 1 SITDAR1 H 0000 H 0000 Retained Retained ...

Page 1257: ...d Control data assign register 2 SICDAR2 H 0000 H 0000 Retained Retained Control register 2 SICTR2 H 0000 H 0000 Retained Retained FIFO control register 2 SIFCTR2 H 1000 H 1000 Retained Retained Status register 2 SISTR2 H 0000 H 0000 Retained Retained Interrupt enable register 2 SIIER2 H 0000 H 0000 Retained Retained Transmit data register 2 SITDR2 H xxxx xxxx H xxxx xxxx Retained Retained Receive...

Page 1258: ...n table 29 4 00 Slave mode 1 01 Slave mode 2 10 Master mode 1 11 Master mode 2 13 SYNCAT 0 R W SIOF_SYNC Pin Valid Timing Indicates the position of the SIOF_SYNC signal to be output as a synchronization pulse 0 At the start bit data of frame 1 At the last bit data of slot 12 REDG 0 R W Receive Data Sampling Edge 0 The SIOF_RXD signal is sampled at the falling edge of SIOF_SCK 1 The SIOF_RXD signal...

Page 1259: ...ontents of SIRCR change 1 Sets the RCRDY bit in SISTR each time when the SIRCR receives the control data 5 SYNCAC 0 R W SIOF_SYNC Pin Polarity Valid when the SIOF_SYNC signal is output as a synchronous pulse 0 Active high 1 Active low 4 SYNCDL 0 R W Data Pin Bit Delay for SIOF_SYNC Pin Valid when the SIOF_SYNC signal is output as synchronous pulse Only one bit delay is valid for transmission in sl...

Page 1260: ... sets the serial clock generation conditions for the master clock SISCR can be specified when the bits TRMD 1 0 in SIMDR are specified as B 10 or B 11 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 BRDV 2 0 BRPS 4 0 MSSEL MSIMM R W R W R W R R R R R R W R W R W R W R W R R W R W BIt Initial value R W Bit Bit Name Initial Value R W Description 15 MSSEL 1 R W Master Clock Sour...

Page 1261: ...lways read as 0 The write value should always be 0 2 to 0 BRDV 2 0 000 R W Baud rate generator s Division Ratio Setting Set the frequency division ratio for the output stage of the baud rate generator 000 Prescalar output 1 2 001 Prescalar output 1 4 010 Prescalar output 1 8 011 Prescalar output 1 16 100 Prescalar output 1 32 101 Setting prohibited 110 Setting prohibited 111 Prescalar output 1 1 S...

Page 1262: ...able This bit is valid in master mode 0 Disables the SIOF_SCK output outputs 0 1 Enables the SIOF_SCK output If this bit is set to 1 the SIOF initializes the baud rate generator and initiates the operation At the same time the SIOF outputs the clock generated by the baud rate generator to the SIOF_SCK pin 14 FSE 0 R W Frame Synchronous Signal Output Enable This bit is valid in master mode 0 Disabl...

Page 1263: ...ting of the TFWM bit in SIFCTR When transmit data is stored in the transmit FIFO transmission of data from the SIOF_TXD pin begins This bit is initialized upon a transmit reset 8 RXE 0 R W Receive Enable 0 Disables data reception from SIOF_RXD 1 Enables data reception from SIOF_RXD This bit setting becomes valid at the start of the next frame at the rising edge of the SIOF_SYNC signal When the 1 s...

Page 1264: ...sets transmit operation This bit setting becomes valid immediately For details of transmit reset refer to table 29 13 SIOF automatically clears this bit upon the completion of reset Thus this bit is always read as 0 0 RXRST 0 R W Receive Reset 0 Does not reset receive operation 1 Resets receive operation This bit setting becomes valid immediately For details of receive reset refer to table 29 13 S...

Page 1265: ...e R W Description 31 to 16 SITDL 15 0 Undefined W Left Channel Transmit Data Specify data to be output from the SIOF_TXD pin as left channel data The position of the left channel data in the transmit frame is specified by the TDLA bit in SITDAR These bits are valid only when the TDLE bit in SITDAR is set to 1 15 to 0 SITDR 15 0 Undefined W Right Channel Transmit Data Specify data to be output from...

Page 1266: ...It Initial value R W Bit Bit Name Initial Value R W Description 31 to 16 SIRDL 15 0 Undefined R Left Channel Receive Data Store data received from the SIOF_RXD pin as left channel data The position of the left channel data in the receive frame is specified by the RDLA bit in SIRDAR These bits are valid only when the RDLE bit in SIRDAR is set to 1 15 to 0 SIRDR 15 0 Undefined R Right Channel Receiv...

Page 1267: ...W R W R W R W R W R W R W R W R W R W R W BIt Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 SITC1 15 0 BIt Initial value R W Bit Bit Name Initial Value R W Description 31 to 16 SITC0 15 0 H 0000 R W Control Channel 0 Transmit Data Specify data to be output from the SIOF_TXD pin as control channel 0 transmit data The position of the control channel 0 data in the transmit or receive frame ...

Page 1268: ... 9 10 11 12 13 15 14 SIRC1 15 0 BIt Initial value R W Bit Bit Name Initial Value R W Description 31 to 16 SIRC0 15 0 Undefined R W Control Channel 0 Receive Data Store data received from the SIOF_RXD pin as control channel 0 receive data The position of the control channel 0 data in the transmit or receive frame is specified by the CD0A bit in SICDAR These bits are valid only when the CD0E bit in ...

Page 1269: ...lways be 0 14 TCRDY 0 R Transmit Control Data Ready 0 Indicates that a write to SITCR is disabled 1 Indicates that a write to SITCR is enabled If SITCR is written when this bit is cleared to 0 SITCR is over written and the previous contents of SITCR are not output from the SIOF_TXD pin This bit is valid when the TXE bit in SITCR is set to 1 This bit indicates a state of the SIOF If SITCR is writte...

Page 1270: ...nditions for setting this bit are satisfied the SIOF again indicates 1 for this bit This bit is valid when the TXE bit in SICTR is 1 This bit indicates a state if the size of empty space in the transmit FIFO is less than the size specified by the TFWM bit in SIFCTR the SIOF clears this bit If the issue of interrupts by this bit is enabled an SIOF interrupt is issued 11 0 R Reserved This bit is alw...

Page 1271: ...d space in the receive FIFO exceeds the size specified by the RFWM bit in SIFCTR A receive data transfer request is issued when the valid data space in the receive FIFO exceeds the size specified by the RFWM bit in SIFCTR When using receive data transfer through the DMAC this bit is always cleared by one DMAC access After DMAC access when conditions for setting this bit are satisfied the SIOF agai...

Page 1272: ...XE bit in SICTR is 1 When 1 is written to this bit the contents are cleared If the issue of interrupts by this bit is enabled an SIOF interrupt is issued 4 FSERR 0 R W Frame Synchronization Error 0 Indicates that no frame synchronization error occurs 1 Indicates that a frame synchronization error occurs A frame synchronization error occurs when the next frame synchronization timing appears before ...

Page 1273: ...1 When 1 is written to this bit the contents are cleared Writing 0 to this bit is invalid If the issue of interrupts by this bit is enabled an SIOF interrupt is issued 2 TFUDF 0 R W Transmit FIFO Underflow 0 No transmit FIFO underflow 1 Transmit FIFO underflow A transmit FIFO underflow means that loading for transmission has occurred when the transmit FIFO is empty When a transmit FIFO underflow o...

Page 1274: ...ICTR is 1 When 1 is written to this bit the contents are cleared Writing 0 to this bit is invalid If the issue of interrupts by this bit is enabled an SIOF interrupt is issued 0 RFOVF 0 R W Receive FIFO Overflow 0 No receive FIFO overflow 1 Receive FIFO overflow A receive FIFO overflow means that writing has occurred when the receive FIFO is full When a receive FIFO overflow occurs the SIOF indica...

Page 1275: ...mits an interrupt as an interrupt to the CPU DMA transfer request The TDREQE bit can be set as transmit interrupts 0 Used as a CPU interrupt 1 Used as a DMA transfer request to the DMAC 14 TCRDYE 0 R W Transmit Control Data Ready Enable 0 Disables interrupts due to transmit control data ready 1 Enables interrupts due to transmit control data ready 13 TFEMPE 0 R W Transmit FIFO Empty Enable 0 Disab...

Page 1276: ... 5 SAERRE 0 R W Slot Assign Error Enable 0 Disables interrupts due to slot assign error 1 Enables interrupts due to slot assign error 4 FSERRE 0 R W Frame Synchronization Error Enable 0 Disables interrupts due to frame synchronization error 1 Enables interrupts due to frame synchronization error 3 TFOVFE 0 R W Transmit FIFO Overflow Enable 0 Disables interrupts due to transmit FIFO overflow 1 Enab...

Page 1277: ... 100 Issue a transfer request when 12 or more stages of the transmit FIFO are empty 101 Issue a transfer request when 8 or more stages of the transmit FIFO are empty 110 Issue a transfer request when 4 or more stages of the transmit FIFO are empty 111 Issue a transfer request when 1 or more stages of transmit FIFO are empty A transfer request to the transmit FIFO is issued by the TDREQE bit in SIS...

Page 1278: ...f the receive FIFO are valid 101 Issue a transfer request when 8 or more stages of the receive FIFO are valid 110 Issue a transfer request when 12 or more stages of the receive FIFO are valid 111 Issue a transfer request when 16 stages of the receive FIFO are valid A transfer request to the receive FIFO is issued by the RDREQE bit in SISTR The receive FIFO is always used as 16 stages of the FIFO r...

Page 1279: ...n 14 to 12 All 0 R Reserved These bits are always read as 0 The write value should always be 0 11 to 8 TDLA 3 0 0000 R W Transmit Left Channel Data Assigns 3 to 0 Specify the position of left channel data in a transmit frame as B 0000 0 to B 1110 14 1111 Setting prohibited Transmit data for the left channel is specified in the SITDL bit in SITDR 7 TDRE 0 R W Transmit Right Channel Data Enable 0 Di...

Page 1280: ...itable register that specifies the position of the receive data in a frame 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDRA 3 0 RDRE RDLA 3 0 RDLE R W R W R W R W R R R R W R W R W R W R W R R R W R BIt Initial value R W Bit Bit Name Initial Value R W Description 15 RDLE 0 R W Receive Left Channel Data Enable 0 Disables left channel data reception 1 Enables left channel d...

Page 1281: ...channel is stored in the SIRDR bit in SIRDR 29 3 13 Control Data Assign Register SICDAR SICDAR is a 16 bit readable writable register that specifies the position of the control data in a frame SICDAR can be specified only when the FL bit in SIMDR is specified as 1xxx x don t care 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CD1A 3 0 CD1E CD0A 3 0 CD0E R W R W R W R W R R R...

Page 1282: ...ta is stored in the SIRD0 bit in SIRCR 7 CD1E 0 R W Control Channel 1 Data Enable 0 Disables transmission and reception of control channel 1 data 1 Enables transmission and reception of control channel 1 data 6 to 4 All 0 R Reserved These bits are always read as 0 The write value should always be 0 3 to 0 CD1A 3 0 0000 R W Control Channel 1 Data Assigns 3 to 0 Specify the position of control chann...

Page 1283: ... baud rate generator BRG is used to generate the serial clock The division ratio is from 1 1 to 1 1024 Note that when using master clock directly as the serial clock without division by BRG division ratio 1 1 the MSIMM bit in SISCR should be set to 1 Figure 29 2 shows connections for supply of the serial clock SCKE SIOF_SCK SIOF_MCLK Pck Divider Pre scalar Baud rate generator 1 1 to 1 1024 Master ...

Page 1284: ...024 MHz 5 6448 MHz 6 144 MHz 256 bits 2 048 MHz 11 2896 MHz 12 288 MHz 29 4 2 Serial Timing SIOF_SYNC The SIOF_SYNC is a frame synchronous signal Depending on the transfer mode it has the following two functions Synchronous pulse 1 bit width pulse indicating the start of the frame L R 1 2 frame width pulse indicating the left channel stereo data L in high level and the right channel stereo data R ...

Page 1285: ...IOF_SCK SIOF_RXD SIOF_TXD SIOF_SYNC SIOF_SCK SIOF_RXD SIOF_TXD SIOF_SYNC a Synchronous pulse b L R 1 frame 1 frame Start bit data 1 bit delay Start bit of left channel data 1 2 frame length Start bit of right channel data 1 2 frame length No delay Figure 29 3 Serial Data Synchronization Timing ...

Page 1286: ...IOF_SCK REDG 0 REDG 1 SIOF_SYNC SIOF_TXD SIOF_RXD SIOF_SCK SIOF_SYNC SIOF_TXD SIOF_RXD a Falling edge sampling a Rising edge sampling Receive timing Transmit timing Receive timing Transmit timing Figure 29 4 SIOF Transmit Receive Timing 29 4 3 Transfer Data Format The SIOF performs the following transfer Transmit receive data Transfer of 8 bit data 16 bit data 16 bit stereo data Control data Trans...

Page 1287: ...1xxx x don t care 2 Frame Length The length of the frame to be transferred by the SIOF is specified by the bits FL 3 0 in SIMDR Table 29 7 shows the relationship between the bits FL 3 0 settings and frame length Table 29 7 Frame Length FL 3 0 Slot Length Number of Bits in a Frame Transfer Data 00XX 8 8 8 bit monaural data 0100 8 16 8 bit monaural data 0101 8 32 8 bit monaural data 0110 8 64 8 bit ...

Page 1288: ...ransmit data SITDAR Receive data SIRDAR Control data SICDAR Only 16 bit data is valid for control data In addition control data is always assigned to the same slot number both in transmission and reception 29 4 4 Register Allocation of Transfer Data 1 Transmit Receive Data Writing and reading of transmit receive data is performed for the following registers Transmit data writing SITDR 32 bit acces...

Page 1289: ...de in byte units for 8 bit data and in word units for 16 bit data Data in unshaded areas is not transmitted or received Monaural or stereo can be specified for transmit data by the TDLE bit and TDRE bit in SITDAR Monaural or stereo can be specified for receive data by the RDLE bit and RDRE bit in SIRDAR To achieve left and right same audio output while stereo is specified for transmit data specify...

Page 1290: ... by the following registers Transmit control data write SITCR 32 bit access Receive control data read SIRCR 32 bit access Figure 29 6 shows the control data and bit alignment in SITCR and SIRCR 31 24 23 16 15 8 7 0 31 24 23 16 15 8 7 0 a Control data One channel b Control data Two channels Control data channel 0 Control data channel 0 Control data channel 1 Figure 29 6 Control Data Bit Alignment T...

Page 1291: ...D1E 1 1 0 2 1 1 Note To use only one channel in control data use channel 0 29 4 5 Control Data Interface Control data performs control command output to the CODEC and status input from the CODEC The SIOF supports the following two control data interface methods Control by slot position Control by secondary FS Control data is valid only when data length is specified as 16 bits ...

Page 1292: ...Control channel 0 Control channel 1 1 frame Slot No 0 Slot No 1 Slot No 2 Slot No 3 Figure 29 7 Control Data Interface Slot Position 2 Control by Secondary FS Slave Mode 2 The CODEC normally outputs the SIOF_SYNC signal as synchronization pulse FS In this method the CODEC outputs the secondary FS specific to the control data transfer after 1 2 frame time has been passed not the normal FS output ti...

Page 1293: ...ew The transmit and receive FIFOs of the SIOF have the following features 16 stage 32 bit FIFOs for transmission and reception The FIFO pointer can be updated in one read or write cycle regardless of access size of the CPU and DMAC One stage 32 bit FIFO access cannot be divided into multiple accesses 2 Transfer Request The transfer request of the FIFO can be issued to the CPU or DMAC as the follow...

Page 1294: ... Valid data is 12 stages or more Smallest 111 16 Valid data is 16 stages Largest The number of stages of the FIFO is always sixteen even if the data area or empty area exceeds the FIFO size the number of FIFOs Accordingly an overflow error or underflow error occurs if data area or empty area exceeds sixteen FIFO stages The FIFO transmit or receive request is canceled when the above condition is no...

Page 1295: ...o disable transmission End transmission Transmit Output serial clock Set operation start for baud rate generator Set the start for frame synchronous signal output and enable transmission Output frame synchronous signal and issue transmit transfer request SIOF Settings SIOF Operation Note When interrupts due to transmit data underflow are enabled after setting the no 6 transmit data the TXE bit sho...

Page 1296: ...SICTR to 0 Set operating mode serial clock slot positions for receive data slot position for control data and FIFO request threshold value Set operation start for baud rate generator Output serial clock Flow Chart SIOF Settings SIOF Operation Set the start for frame synchronous signal output and enable reception Issue receive transfer request according to the receive FIFO threshold value Reception...

Page 1297: ...DR Transmit SITDR from SIOFTXD synchronously with SIOF_SYNC Transfer ended Clear the TXE bit in SICTR to 0 Set operating mode serial clock slot positions for transmit data slot position for control data control data and FIFO request threshold value Set transmit data Set to disable transmission Issue transmit transfer request to enable transmission when frame synchronous signal is input Transmit En...

Page 1298: ... bit in SICTR to 0 Set operating mode serial clock slot positions for receive data slot position for control data and FIFO request threshold value Flow Chart SIOF Settings SIOF Operation Issue receive transfer request according to the receive FIFO threshold value Reception End reception Read receive data Set to disable reception Read SIRDR Store SIOFRXD receive data in SIRDR synchronously with SIO...

Page 1299: ...ve reset RXRST bit in SICTR Table 29 13 shows the details of initialization upon transmit or receive reset Table 29 13 Transmit and Receive Reset Type Objects Initialized Transmit reset Stop transmitting form the SIOF_TXD high level is outputted Transmit FIFO write pointer TCRDY TFEMP and TDREQ bits in SISTR TXE bit in SICTR Receive reset Stop receiving form the SIOF_RXD Receive FIFO write pointer...

Page 1300: ...transmit control register is ready to be written 6 Control RCRDY Receive control data ready The receive control data register stores valid data 7 TFUDF Transmit FIFO underflow Serial data transmit timing has arrived while the transmit FIFO is empty 8 TFOVF Transmit FIFO overflow Write to the transmit FIFO is performed while the transmit FIFO is full 9 RFOVF Receive FIFO overflow Serial data is rec...

Page 1301: ... performs the following operations Transmit FIFO underflow TFUDF The immediately preceding transmit data is again transmitted Transmit FIFO overflow TFOVF The contents of the transmit FIFO are protected and the write operation causing the overflow is ignored Receive FIFO overflow RFOVF Data causing the overflow is discarded and lost Receive FIFO underflow RFUDF An undefined value is output on the ...

Page 1302: ...ynchronous pulse method falling edge sampling slot No 0 used for transmit and receive data an frame length 8 bits SIOF_SCK SIOF_RXD SIOF_TXD SIOF_SYNC L channel data Slot No 0 TRMD 1 0 00 or 10 TDLE 1 RDLE 1 CD0E 0 REDG 0 TDLA 3 0 0000 RDLA 3 0 0000 CD0A 3 0 0000 FL 3 0 0000 frame length 8 bits TDRE 0 RDRE 0 CD1E 0 TDRA 3 0 0000 RDRA 3 0 0000 CD1A 3 0 0000 Specifications 1 frame 1 bit delay Figure...

Page 1303: ...3 0 0000 CD1A 3 0 0000 Slot No 0 Slot No 1 Specifications 1 frame 1 bit delay Figure 29 14 Transmit and Receive Timing 8 Bit Monaural Data 2 3 16 bit Monaural Data Synchronous pulse method falling edge sampling slot No 0 used for transmit and receive data and frame length 64 bits SIOF_SCK SIOF_RXD SIOF_TXD SIOF_SYNC L channel data TRMD 1 0 00 or 10 TDLE 1 RDLE 1 CD0E 0 REDG 0 TDLA 3 0 0000 RDLA 3 ...

Page 1304: ...delay Figure 29 16 Transmit and Receive Timing 16 Bit Stereo Data 1 5 16 bit Stereo Data Case 2 L R method rising edge sampling slot No 0 used for left channel transmit data slot No 1 used for left channel receive data slot No 2 used for right channel transmit data slot No 3 used for right channel receive data and frame length 64 bits SIOF_SCK SIOF_RXD SIOF_TXD SIOF_SYNC TRMD 1 0 01 TDLE 1 RDLE 1 ...

Page 1305: ...No 4 Slot No 5 Slot No 6 Slot No 7 Specifications 1 frame 1 bit delay R channel data Figure 29 18 Transmit and Receive Timing 16 Bit Stereo Data 3 7 16 bit Stereo Data Case 4 Synchronous pulse method falling edge sampling slot No 0 used for left channel data slot No 2 used for right channel data slot No 1 used for control data for channel 0 slot No 3 used for control data for channel 1 and frame l...

Page 1306: ...ontrol data for channel 1 and frame length 128 bits In this mode valid data must be set to slot No 0 SIOF_SCK SIOF_RXD SIOF_TXD SIOF_SYNC TRMD 1 0 00 or 10 TDLE 1 RDLE 1 CD0E 1 REDG 0 TDLA 3 0 0000 RDLA 3 0 0000 CD0A 3 0 0010 FL 3 0 1110 frame length 128 bits TDRE 1 RDRE 1 CD1E 1 TDRA 3 0 0001 RDRA 3 0 0001 CD1A 3 0 0011 L channel data R channel data Control channel 0 Control channel 1 Slot No 0 S...

Page 1307: ... receive mode when T 0 Detection of error signal and automatic character retransmission in transmit mode when T 0 Selectable minimum character interval of 11 etus N 255 when T 1 etu Elementary Time Unit Selectable direct convention inverse convention Output clock can be fixed in high or low state Freely selectable bit rate by on chip baud rate generator Four types of interrupt source Transmit data...

Page 1308: ...ster Transmit shift register Transmit dara register Serial mode register Serial control 2 register Serial status register Bit rate register Serial clock ERI SCWAIT SCGRD Wait time register Guard extension register SCSMPL Sampling register TXI RXI TEI Transmit data empty Receive data full interrupt controller DMA controller SCSCR Serial control register SCRDR SCTDR SCRSR SCTSR Parity generation Par...

Page 1309: ...able 30 1 Table 30 1 Pin Configuration Name Abbreviation I O Function Transmit receive data SIM_D I O Transmit receive data input output Clock output SIM_CLK Output Clock output Smart card reset SIM_RST Output Smart card reset output Note In explaining transmit and receive operations the transmit data and receive data sides shall be referred to as TxD and RxD respectively ...

Page 1310: ...ift register SCTSR Transmit data register SCTDR R W H FFE9 0006 H 1FE9 0006 8 Serial status register SCSSR R W H FFE9 0008 H 1FE9 0008 8 Receive shift register SCRSR Receive data register SCRDR R H FFE9 000A H 1FE9 000A 8 Smart card mode register SCSCMR R W H FFE9 000C H 1FE9 000C 8 Serial control 2 register SCSC2R R W H FFE9 000E H 1FE9 000E 8 Wait time register SCWAIT R W H FFE9 0010 H 1FE9 0010...

Page 1311: ... H 00 Retained Retained Transmit shift register SCTSR Transmit data register SCTDR H FF H FF Retained Retained Serial status register SCSSR H 84 H 84 Retained Retained Receive shift register SCRSR Receive data register SCRDR H 00 H 00 Retained Retained Smart card mode register SCSCMR H 01 H 01 Retained Retained Serial control 2 register SCSC2R H 00 H 00 Retained Retained Wait time register SCWAIT ...

Page 1312: ...ode Selects whether even or odd parity is to be used when adding a parity bit and checking parity 0 Even parity 1 1 Odd parity 2 Notes 1 When set to even parity during transmission a parity bit is added such that the sum of 1 bits in the parity bit and transmit characters is even During reception a check is performed to ensure that the sum of 1 bits in the parity bit and the receive characters is ...

Page 1313: ...value R W 0 0 0 0 0 1 1 1 R R R R R R W R W R W BRR 2 0 Bit Bit Name Initial Value R W Description 7 to 3 All 0 R Reserved These bits are always read as 0 The write value should always be 0 2 1 0 BRR2 BRR1 BRR0 1 1 1 R W R W R W Set the transmit receive bit rate 2 to 0 The SCBRR setting can be determined from the following formula sck_frequency 2 BRR 1 Pck0 The units of Pck0 peripheral clock 0 fre...

Page 1314: ...mit data empty interrupt TXI requests 1 Enables transmit data empty interrupt TXI requests Note A TXI can be canceled either by clearing the TDRE flag or by clearing the TIE bit to 0 6 RIE 0 R W Receive Interrupt Enable When serial receive data is transferred from the receive shift register SCRSR to the receive data register SCRDR and the RDRF flag in SCSSR is set to 1 receive data full interrupt ...

Page 1315: ...les reception 1 1 Enables reception 2 Notes 1 Clearing the RE bit to 0 has no effect on the RDRF PER ERS ORER or WAIT_ER flag and the previous state is retained 2 If the start bit is detected in this state serial reception is initiated Before setting the RE bit to 1 SCSMR and SCSCMR must always be set to determine the receive format 3 WAIT_IE 0 R W Wait Enable Enables disables wait error interrupt...

Page 1316: ...smit Shift Register SCTSR SCTSR is a shift register that transmits serial data The smart card interface transfers transmit data from the transmit data register SCTDR to SCTSR and then sends the data in order from the LSB or MSB to the SIM_TXD pin to perform serial data transmission When data transmission of one byte is completed transmit data is automatically transferred from SCTDR to SCTSR and tr...

Page 1317: ...e transmit shift register SCTSR transmit data written to SCTDR is transferred to SCTSR and serial transmission is initiated During SCTSR serial data transmission if the next transmit data is written to SCTDR continuous serial transmission is possible 7 6 5 4 3 2 1 0 Bit Initial value R W 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W SCTD 7 0 Bit Bit Name Initial Value R W Description 7 to 0 SCTD...

Page 1318: ...iption 7 TDRE 1 R W Transmit Data Register Empty Indicates that data was transferred from the transmit data register SCTDR to the transmit shift register SCTSR and that the next serial transmit data can be written to SCTDR 0 Indicates that valid transmit data is written to SCTDR Clearing conditions When the TE bit in CCSCR is 1 and data is written to SCTDR When 0 is written to the TDRE bit 1 Indic...

Page 1319: ...data is stored in SCRDR Setting condition When serial reception is completed normally and received data is transferred from SCRSR to SCRDR Note In T 0 mode when a parity error is detected during reception the SCRDR contents and RDRF flag are unaffected and the previous state is retained On the other hand in T 1 mode when a parity error is detected during reception the received data is transferred ...

Page 1320: ...te is retained 2 In SCRDR the received data before the overrun error occurred is lost and the data that had been received at the time when the overrun error occurred is retained Further with the ORER bit set to 1 subsequent serial reception cannot be continued 4 ERS 0 R W Error Signal Status Indicates the status of error signals returned from the receive side during transmission In T 1 mode this f...

Page 1321: ...eption 2 Setting condition When the sum of 1 bits in the received data and parity bit does not match the even or odd parity specified by the O E bit in the serial mode register SCSMR Notes 1 When the RE bit in SCSCR is cleared to 0 the PER flag is unaffected and the previous state is retained 2 In T 0 mode the data received when a parity error occurs is not transferred to SCRDR and the RDRF flag i...

Page 1322: ...ot be written 0 Indicates that transmission is in progress Clearing condition When transmit data is transferred from SCTDR to SCTSR and serial transmission is initiated 1 Indicates that transmission is ended Setting conditions On reset When the ERS flag is 0 normal transmission after one byte of serial character and a parity bit are transmitted Note The TEND flag is set 1 etu before the end of the...

Page 1323: ...o successive received characters exceeds the SCWAIT value Character protection time etu Notes 1 Even if the RE bit in SCSCR is cleared to 0 the WAIT_ER flag is unaffected and the previous state is retained 2 In T 0 mode even if the setting condition for the WAIT_ER flag is satisfied when the RE bit is set to 1 the WAIT_ER flag may not be set to 1 In this case the RE bit has been set to 1 then the ...

Page 1324: ...RDR The CPU or DMAC cannot directly read from or write to SCRSR 30 3 8 Receive Data Register SCRDR SCRDR is an 8 bit read only register that stores received serial data When reception of one byte of serial data is completed the smart card interface transfers the received serial data from the receive shift register SCRSR to SCRDR for storage and completes the receive operation Thereafter SCRSR can ...

Page 1325: ...s 2 etus and the setting of the guard extension register is invalid 0 The character protection time is determined by the value of the guard extension register 1 The character protection time is 2 etus 5 PB 0 R W Protocol Selects the T 0 or T 1 protocol 0 The smart card interface operates according to the T 0 protocol 1 The smart card interface operates according to the T 1 protocol 4 0 R W Reserve...

Page 1326: ... not affect the parity bit 0 Transmits the SCTDR contents without change Stores received data in SCRDR without change 1 Inverts the SCTDR contents and transmits it Inverts received data and stores it in SCRDR 1 RST 0 R W Smart Card Reset Controls the output of the SIM_RST pin of the smart card interface 0 The SIM_RST pin of the smart card interface outputs low level 1 The SIM_RST pin of the smart ...

Page 1327: ...0 0 0 0 0 0 0 0 R W R R R R R R R EIO Bit Bit Name Initial Value R W Description 7 EIO 0 R W Error Interrupt Only When the EIO bit is 1 even if the RIE bit is set to 1 a receive data full interrupt RXI request is not sent to the CPU When the DMAC is used with this setting the CPU processes only ERI requests Receive data full interrupt RXI requests are determined by the RIE bit setting 6 to 0 All 0...

Page 1328: ...t Bit Name Initial Value R W Description 7 to 0 SCGRD 7 0 All 0 R W Guard Extension Indicate the time added for character protection after transmitting a character to the smart card The interval between the start of two successive characters is 12 etus no addition when the value of this register is H 00 is 13 etus when the value is H 01 and so on up to 266 etus for H FE If the value of this regist...

Page 1329: ... W Description 15 to 0 SCWAIT 15 0 All 0 R W Wait Time Register T 0 In this mode the operation wait time can be set in this register If the interval between the start of characters to be received and transmitted or received characters immediately before exceeds the 60 the value set in this register etu the WAIT_ER flag is set to 1 However if SCWAIT is set to H 0000 the WAIT_ER flag is set after 60...

Page 1330: ...it Initial value R W 0 0 0 0 0 0 0 1 0 1 1 1 0 0 1 1 R R R R R R W R W R W R W R W R W R W R W R W R W R W SCSMPL 10 0 Bit Bit Name Initial Value R W Description 15 to 11 All 0 R Reserved These bits are always read as 0 The write value should always be 0 10 to 0 SCSMPL 10 0 H 173 R W Setting for Number of Serial Clock Cycles per Etu The number of serial clock cycles per etu is SCSMPL value 1 The v...

Page 1331: ...and PB bits in SCSCMR is inserted between the end of each parity bit and the beginning of the next frame During reception in T 0 mode when a parity error is detected low level is output for a duration of 1 etu as an error signal 10 5 etus after the start bit During transmission in T 0 mode if an error signal is sampled after 2 etus or more have elapsed the same data is automatically transmitted On...

Page 1332: ... T 1 mode if a parity error is detected an error signal is not returned During transmission error signals are not sampled and data is not retransmitted Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Transmitter output When no parity error occurs Ds D1 D2 D3 D4 D5 D6 D7 Dp Transmitter output When a parity error occurs in T 0 mode Ds D0 DE Receiver output Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Transmitter output When a parit...

Page 1333: ...esting data retransmission After output of an error signal with the specified duration the receive side again sets the signal line to the high impedance state The signal line returns to high level by means of the pull up resistance If in T 1 mode however no error signal is output even if a parity error occurs 5 If the transmit side does not receive an error signal the next frame is transmitted On ...

Page 1334: ...ings refer to section 30 4 4 Clocks Serial control register SCSCR settings Each interrupt can be enabled and disabled using the TIE RIE TEIE and WAIT_IE bits By setting either the TE or RE bit to 1 transmission or reception is selected The CKE 1 and CKE 0 bits are used to select the clock output state For details refer to section 30 4 4 Clocks Smart card mode register SCSCMR settings When the IC c...

Page 1335: ...Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Ds D7 D6 D5 D4 D3 D2 D1 D0 Dp A Z Z A Z Z A A Z Z Z Z a Direct converntion SDIR SINV O E 0 b Inverse convention SDIR SINV O E 1 state A Z Z A A A A A Z Z Z A state Figure 30 3 Examples of Start Character Waveforms 30 4 4 Clocks Only the internal clock generated by the on chip baud rate generator can be used as the transmit receive clock in the smart card interface The...

Page 1336: ... is shown in the flowchart of figure 30 4 Step 1 to step 7 of figure 30 4 correspond to the following operation 1 Clear the TE and RE bits in the serial control register SCSCR to 0 2 Clear the error flags PER ORER ERS and WAIT_ER in the serial status register SCSSR to 0 3 Set the parity bit O E bit in the serial mode register SCSMR 4 Set the LCB PB SMIF SDIR and SINV bits in the smart card mode re...

Page 1337: ...lags to 0 Set the TIE RIE TE and RE bits in SCSCR Clear the TE and RE bits in SCSCR to 0 Set the party using the O E bit in SCSMR Initiallzation End Has a 1 bit interval elapsed Yes No Wait 1 2 3 4 5 6 7 Figure 30 4 Example of Initialization Flow 2 Serial Data Transmission Data transmission in smart card mode includes error signal sampling and retransmit processing An example of transmit processin...

Page 1338: ...atically cleared to 0 and the TDRE flag is automatically set to 1 5 When performing continuous data transmission return to step 2 6 When transmission is ended clear the TE bit to 0 Interrupt processing can be performed in the above series of processing When the TIE bit is set to 1 to enable interrupt requests and if transmission is started and the TDRE flag is set to 1 a transmit data empty interr...

Page 1339: ... 1 Clear TE bit in SCSCR to 0 Start transmission Yes No No Yes Error processing Yes No Yes No No Yes 6 5 4 3 2 1 Figure 30 5 Example of Transmit Processing 3 Serial Data Reception An example of data receive processing in smart card mode is shown in figure 30 6 Step 1 to step 6 of figure 30 6 correspond to the following operation 1 Follow the initialization procedure above to initialize the smart c...

Page 1340: ...t processing can be performed in the above series of processing When the RIE bit is set to 1 and the EIO bit is cleared to 0 and if the RDRF flag is set to 1 a receive data full interrupt RXI request is issued If the RIE bit is set to 1 an error occurs during reception and either the ORER PER or WAIT_ER flag is set to 1 a transmit receive error interrupt ERI request is issued For details refer to ...

Page 1341: ... Processing 4 Switching Modes When switching from receive mode to transmit mode after confirming that reception has been completed start initialization and then clear the RE bit to 0 and set the TE bit to 1 Completion of reception can be confirmed through the RDRF flag When switching from transmit mode to receive mode after confirming that transmission has been completed start initialization and t...

Page 1342: ...pt Sources of Smart Card Interface Operating State Flags Mask Bits Interrupt Sources TDRE TIE TXI Normal operation TEND TEIE TEI Transmit mode Error ERS RIE ERI Normal operation RDRF RIE EIO RXI ORER PER RIE ERI Receive mode Error WAIT_ER WAIT_IE ERI 6 Data Transfer Using DMAC The smart card interface enables reception and transmission using the DMAC In transmission when the TDRE flag in SCSSR is ...

Page 1343: ...l occurs When in T 0 mode and if a parity error occurs during reception a data retransmit request is issued At this time the RDRF flag is not set and a DMA transfer request is not issued so the number of bytes specified to the DMAC can be received When using the DMAC for receive data processing and performing error processing as a result of an interrupt request sent to the CPU the RIE bit should b...

Page 1344: ... using the serial clock for internal synchronization Receive data is captured internally at the rising edge of the 186th serial clock pulse This is shown in figure 30 7 Received data RXD Start bit Synchronization sampling timing Data sampling timing 372 clock pulses 186 clock pulses 0 0 185 185 371 0 371 D0 D1 Basic clock Figure 30 7 Receive Data Sampling Timing in Smart Card Mode Hence the receiv...

Page 1345: ...me if the RIE bit in SCSCR is set to enable an ERI request is issued The PER bit in SCSSR should be cleared to 0 before the sampling timing for the next parity bit 2 The RDRF bit in SCSSR is not set for frames in which a parity error occurs 3 If no error is detected as a result of checking the received parity bit the PER bit in SCSSR is not set 4 If no error is detected as a result of checking the...

Page 1346: ...t parity bit 2 In T 0 mode the TEND bit in SCSSR is not set for a frame when an error signal indicating an error is received 3 If no error signal is returned from the receive side the ERS bit in SCSSR is not set 4 If no error signal is returned from the receive side it is assumed that transmission of one frame including retransmission is completed and the TEND bit in SCSSR is set to 1 At this time...

Page 1347: ...put is fixed at the specified level 4 Make the transition to standby mode To return from standby mode to smart card interface mode 5 Cancel the standby state 6 Set the CKE1 bit in the serial control register SCSCR to the value of the output fixed state at the beginning of standby the current SIM_CLK pin state 7 Write 1 to the CKE0 bit in SCSCR to output a clock signal Clock signal generation begin...

Page 1348: ...connection is not needed Smrat card interface Note For details refer to ISO IEC7816 3 This LSI SIM_D SIM_CLK SIM_RST I O CLK RST Smart card Data line Clock line Reset line 20 kW Figure 30 11 Example of Pin Connections in Smart Card Interface Note The transmission reception in loop can perform self check when the RE and TE bits are set to 1 without connecting to the IC card 6 Transmit End Interrupt...

Page 1349: ...m of the timing to set the TEIE bit to 1 is shown in figure 30 12 D0 D1 D2 D3 D4 D5 D6 D7 DP Ds D0 D1 D2 D3 D4 D5 D6 D7 DP Ds D0 D1 D2 D3 D4 D5 D6 D7 DP Ds Unnecessary TEND set timing TEND TDRE DE DE TEIE TEIE Transmit frame Transmit frame Last frame TEIE set timing DE Figure 30 12 TEIE Set Timing ...

Page 1350: ...Section 30 SIM Card Module SIM Rev 1 00 Oct 01 2007 Page 1284 of 1956 REJ09B0256 0100 ...

Page 1351: ... in the future within the range of combinations of currently defined command types response types 31 1 Features Interface that complies with the MultiMediaCard System Specification Version 3 1 MMC mode supported Interface via the CLK output transfer clock output pin the CMD input output command output response input pin and the DAT input output data input output pin 16 7 Mbps bit rate max for the ...

Page 1352: ...ock diagram of the MMCIF MMCIF FIFO Peripheral bus Internal bus interface FSTAT TRAN ERR FRDY Interrupt control Card clock generator Data transmission reception control Command transmission control Response reception control MMC_CLK MMC_CMD MMC_DAT MMC_ODMOD MMC_VDDON MMC_CD Port interface Figure 31 1 MMCIF Block Diagram ...

Page 1353: ...MC_CLK CLK Output Clock output pin MMC_CMD CMD Input Output Command output response input pin MMC_DAT DAT Input Output Data input output pin MMC_ODMOD MMC_ODMOD Output Open drain mode control MMC_VDDON MMC_VDDON Output Card power supply control MMC_CD MMC_CD Input Card identification signal Note For easier understanding of transmission and reception the data transmission side and reception side ar...

Page 1354: ...2 8 Command register 3 CMDR3 R W H FFF9 0003 H 1FF9 0003 8 Command register 4 CMDR4 R W H FFF9 0004 H 1FF9 0004 8 Command register 5 CMDR5 R H FFF9 0005 H 1FF9 0005 8 Response register 0 RSPR0 R W H FFF9 0020 H 1FF9 0020 8 Response register 1 RSPR1 R W H FFF9 0021 H 1FF9 0021 8 Response register 2 RS PR2 R W H FFF9 0022 H 1FF9 0022 8 Response register 3 RSPR3 R W H FFF9 0023 H 1FF9 0023 8 Response...

Page 1355: ...0B 8 Interrupt control register 0 INTCR0 R W H FFF9 000C H 1FF9 000C 8 Interrupt control register 1 INTCR1 R W H FFF9 000D H 1FF9 000D 8 Interrupt status register 0 INTSTR0 R W H FFF9 000E H 1FF9 000E 8 Interrupt status register 1 INTSTR1 R W H FFF9 000F H 1FF9 000F 8 Transfer clock control register CLKON R W H FFF9 0010 H 1FF9 0010 8 VDD open drain control register VDCNT R W H FFF9 0012 H 1FF9 00...

Page 1356: ...ed Response register 0 RSPR0 H 00 H 00 Retained Retained Response register 1 RSPR1 H 00 H 00 Retained Retained Response register 2 RSPR2 H 00 H 00 Retained Retained Response register 3 RSPR3 H 00 H 00 Retained Retained Response register 4 RSPR4 H 00 H 00 Retained Retained Response register 5 RSPR5 H 00 H 00 Retained Retained Response register 6 RSPR6 H 00 H 00 Retained Retained Response register 7...

Page 1357: ... 00 H 00 Retained Retained Interrupt status register 0 INTSTR0 H 00 H 00 Retained Retained Interrupt status register 1 INTSTR1 H 00 H 00 Retained Retained Transfer clock control register CLKON H 00 H 00 Retained Retained VDD open drain control register VDCNT H 00 H 00 Retained Retained Data register DR H xxxx H xxxx Retained Retained FIFO pointer clear register FIFOCLR H 00 H 00 Retained Retained ...

Page 1358: ...R R W R W R W Bit Initial value R W TY6 TY5 TY4 TY2 TY 1 0 Bit Bit Name Initial Value R W Description 7 0 R Reserved This bit is always read as 0 The write value should always be 0 6 TY6 0 R W Specifies predefined multiblock transfer Bits TY1 and TY0 should be set to 01 or 10 When using a command to set this bit it is necessary to specify the transfer block size and the transfer block number in TB...

Page 1359: ...smission 11 Set this bit when transmitting Stop Tran Table 31 4 summarizes the correspondence between the commands described in the MultiMediaCard System Specification Version 3 1 and the settings of the CMDTYR and RSPTYR registers 31 3 2 Response Type Register RSPTYR RSPTYR specifies the command format in conjunction with CMDTYR The bits RTY 2 0 specify the number of response bytes and the bits R...

Page 1360: ...nd response bytes 000 A command requiring no command responses 001 Setting prohibited 010 Setting prohibited 011 Setting prohibited 100 A command requiring 6 byte command response Specified by R1 R1b R3 R4 and R5 responses in MMC mode 101 A command requiring a 17 byte command response Specified by the R2 response in MMC mode 110 Setting prohibited 111 Setting prohibited Note The purpose of a CRC c...

Page 1361: ...1 CMD3 SET_RELATIVE_ADDR R1 00 4 100 CMD4 SET_DSR 00 000 CMD7 SELECT DESELECT_CARD R1b 00 1 4 100 CMD9 SEND_CSD R2 00 101 CMD10 SEND_CID R2 00 101 CMD11 READ_DAT_UNTIL_STOP R1 01 4 100 CMD12 STOP_TRANSMISSION R1b 1 00 1 4 100 CMD13 SEND_STATUS R1 00 4 100 CMD15 GO_INACTIVE_STATE 00 000 CMD16 SET_BLOCKLEN R1 00 4 100 CMD17 READ_SINGLE_BLOCK R1 3 01 4 100 CMD18 READ_MULTIPLE_BLOCK R1 2 2 01 4 100 CM...

Page 1362: ...4 00 4 100 CMD40 GO_IRQ_STATE R5 00 4 100 CMD42 LOCK_UNLOCK R1b 10 1 4 100 CMD55 APP_CMD R1 00 4 100 CMD56 GEN_CMD R1b 5 1 4 100 Notes 1 These commands are not supported after MMCA Ver3 1 specification cards 2 Set the TY6 bit when the transfer block number is set in advance set the TY2 bit when the transfer block number is not set 3 Set this bit when using secure MMC multiple block transaction 4 S...

Page 1363: ...e multiblock transfer command corresponds to the number of bytes of each data block 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R R R R R W R W R W R W Bit Initial value R W C 3 0 Bit Bit Name Initial Value R W Description 7 to 4 All 0 R Reserved These bits are always read as 0 The write value should always be 0 3 to 0 CS 3 0 0000 R W Transfer Data Block Size 0000 1 byte 0001 2 bytes 0010 4 bytes 0011 8 bytes...

Page 1364: ... R W R W R W R W R W R W R W R W R W TBNCR Bit Bit Name Initial Value R W Description 15 to 0 TBNCR All 0 R W Transfer Block Number Counter Clearing condition When a specified block number is transferred or 0 is written to TBNCR 31 3 5 Command Registers 0 to 5 CMDR0 to CMDR5 The CMDR registers are six 8 bit registers A command is written to CMDR as shown in table 31 5 and the command is transmitte...

Page 1365: ...et to 1 5 to 0 INDEX All 0 R W Command index CMDR1 to CMDR4 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Bit Initial value R W CMDR 1 4 n Bit Bit Name Initial Value R W Description 7 to 0 CMDR 1 4 n All 0 R W Command arguments Note n 0 to 7 CMDR5 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R R R R R R R R Bit Initial value R W CRC End Bit Bit Name Initial Value R W Description 7 to 1 CRC Al...

Page 1366: ...sponse bytes and valid RSPR registers Table 31 6 Correspondence between Command Response Byte Number and RSPR MMC Mode Response RSPR registers 6 bytes R1 R1b R3 R4 R5 17 bytes R2 RSPR0 1st byte RSPR1 2nd byte RSPR2 3rd byte RSPR3 4th byte RSPR4 5th byte RSPR5 6th byte RSPR6 7th byte RSPR7 8th byte RSPR8 9th byte RSPR9 10th byte RSPR10 11th byte RSPR11 1st byte 12th byte RSPR12 2nd byte 13th byte R...

Page 1367: ...re cleared to H 00 by writing an arbitrary value RSPR0 to RSPR16 make up a continuous 17 byte shift registers in which a command response is stored RSPRD 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R R R R W R W R W R W R W Bit Initial value R W RSPR Bit Bit Name Initial Value R W Description 7 to 5 All 0 R Reserved These bits are always read as 0 The write value should always be 0 4 to 0 RSPR All 0 R W All o...

Page 1368: ...mmand response clearing the command response register write if necessary Analysis transfer of receive data of prior command if necessary Preparation of transmit data of the next command if necessary Setting of CMDTYR RSPTYR TBCR and TBNCR The CMDR0 to CMDR4 CMDTYR RSPTYR TBCR and TBNCR registers should not be changed until command transmission has ended during the time the CWRE flag in CSTR is set...

Page 1369: ...en setting the CMDOFF bit in OPCR issuing the CMD12 command or processing an error in MMC mode A new command sequence should be started only after the end of the command sequence on both the MMCIF and card sides is confirmed 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R R R R R R R R W Bit Initial value R W START Bit Bit Name Initial Value R W Description 7 to 1 All 0 R Reserved These bits are always read as ...

Page 1370: ...mand is transmitted This bit is then cleared by hardware Write enabled period From command transmission completion to command sequence end Write 0 Operation is not affected Write 1 Command sequence is forcibly aborted 6 0 R Reserved This bit is always read as 0 The write value should always be 0 5 RD_CONTI 0 R W Read Continue This bit is cleared by hardware when 1 is written and the MMCIF resumes ...

Page 1371: ...The write value should always be 0 In write data transmission the contents of the command response and data response should be analyzed and then transmission should be triggered In addition the data transmission should be temporarily halted by FIFO full empty and it should resume when the preparation has been completed In multiblock transfer the transfer should be temporarily halted at every block...

Page 1372: ...meout error handling the command sequence should be aborted by setting the CMDOFF bit to 1 and then clearing the CTERI flag 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 R R R R R R R R W Bit Initial value R W CTSEL0 Bit Bit Name Initial Value R W Description 7 to 1 All 0 R Reserved These bits are always read as 0 The write value should always be 0 0 CTSEL0 1 R W 0 128 transfer clock cycles from command transmi...

Page 1373: ...ting the prescaler output and enters the data timeout error states when the number of prescaler outputs reaches the number specified in DTOUTR When the DTERIE bit in INTCR1 is set to 1 the DTERI flag in INTSTR1 is set To perform data timeout error handling abort the command sequence by setting the CMDOFF bit to 1 and then clear the DTERI flag For a command with data busy status data timeout cannot...

Page 1374: ...o 1 this bit is cleared to 0 because the MMCIF command sequence is aborted 0 Idle state waiting for a command or data busy state 1 Command sequence execution in progress 6 FIFO_FULL 0 R FIFO Full This bit is set to 1 when the FIFO becomes full while data is being received and cleared to 0 when RD_CONTI is set to 1 or the command sequence is completed 0 The FIFO is empty 1 The FIFO is full 5 FIFO_E...

Page 1375: ...the response has ended or a command with write data has ended 0 Idle state waiting for a command or command sequence execution in progress 1 Card is in the data busy state after command sequence termination 2 DTBUSY_TU Undefined R Data Busy Pin Status Monitors the levels of the DAT pin in MMC mode By reading this bit whether the card is in the busy state can be monitored after the card in the busy...

Page 1376: ...ting 6 FFIE 0 R W FIFO Full Flag Enable 0 Disables FIFO full flag setting 1 Enables FIFO full flag setting 5 DRPIE 0 R W Data Response End Flag Enable 0 Disables data response end flag setting 1 Enables data response end flag setting 4 DTIE 0 R W Data Transfer End Flag Enable 0 Disables data transfer end flag setting 1 Enables data transfer end flag setting 3 CRPIE 0 R W Command Response End Flag ...

Page 1377: ... 0 R W ERR Interrupt Enable 0 Disables ERR interrupt 1 Enables ERR interrupt 6 INTRQ1E 0 R W TRAN Interrupt Enable 0 Disables TRAN interrupt 1 Enables TRAN interrupt 5 INTRQ0E 0 R W FSTAT Interrupt Enable 0 Disables FSTAT interrupt 1 Enables FSTAT interrupt 4 0 R Reserved This bit is always read as 0 The write value should always be 0 3 WRERIE 0 R W Write Error Flag Enable 0 Disables write error f...

Page 1378: ... 4 3 2 1 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Bit Initial value R W FEI FFI DRPI DTI CRPI CMDI DBSYI BTI Bit Bit Name Initial Value R W Description Interrupt output 7 FEI 0 R W FIFO Empty Flag Setting 1 condition When FIFO becomes empty while FEIE 1 and write data is being transmitted when the FIFO_EMPTY bit in CSTR is set Clearing 0 condition Write 0 after reading FEI 1 FSTAT 6 FFI 0...

Page 1379: ...e Receive End Flag Setting 1 condition When command response reception ends while CRPIE 1 Clearing 0 condition Write 0 after reading CRPI 1 TRAN 2 CMDI 0 R W Command Transmit End Flag Setting 1 condition When command transmission ends while CMDIE 1 Clearing 0 condition Write 0 after reading CMDI 1 TRAN 1 DBSYI 0 R W Data Busy End Flag Setting 1 condition When data busy state is canceled while DBSY...

Page 1380: ...sponse is detected while WREIE 1 Clearing 0 condition Write 0 after reading WREI 1 Note When the write error occurs abort the command sequence by setting the CMDOFF bit to 1 ERR 2 CRCERI 0 R W CRC Error Flag Setting 1 condition When a CRC error for command response or receive data or a CRC status error for transmit data response is detected while CRCERIE 1 For the command response other than R2 CR...

Page 1381: ... 0 after reading DTERI 1 Note When the data timeout error occurs abort the command sequence by setting the CMDOFF bit to 1 and then clear the DTERI flag ERR 0 CTERI 0 R W Command Timeout Error Flag Setting 1 condition When a command timeout error specified in TOCR occurs while CTERIE 1 Clearing condition Write 0 after reading CTERI 1 Note When the command timeout error occurs abort the command seq...

Page 1382: ...escription 7 CLKON 0 R W Clock On 0 Fixes the transfer clock output from the MMC_CLK pin to low level 1 Outputs the transfer clock from the MMC_CLK pin 6 to 4 All 0 R Reserved These bits are always read as 0 The write value should always be 0 3 to 0 CSEL 3 0 0000 R W Transfer Clock Frequency Select 0000 Setting prohibited 0001 Uses the 1 2 divided system clock as a transfer clock 0010 Uses the 1 4...

Page 1383: ... 0 0 0 R W R W R R R R R R Bit Initial value R W VDDON ODMOD Bit Bit Name Initial Value R W Description 7 VDDON 0 R W Available as a control signal for card power supply VDD 0 Low level signal is output to MMC_VDDON 1 High level signal is output to MMC_VDDON 6 ODMOD 0 R W Available to control open drain of CMD output in MMC mode 0 Low level signal is output to MMC_ODMOD 1 High level signal is outp...

Page 1384: ...W DR Bit Bit Name Initial Value R W Description 15 to 0 7 to 0 DR Undefined R W Register to read write FIFO data Word or byte access is possible However address 2n 1 cannot be accessed in bytes 31 3 17 FIFO Pointer Clear Register FIFOCLR The FIFO write read pointer is cleared by writing an arbitrary value to FIFOCLR 7 6 5 4 3 2 1 0 W W W W W W W W Bit Initial value R W FIFOCLR Bit Bit Name Initial...

Page 1385: ...MA request signal 1 Enables output of DMA request signal 6 AUTO 0 R W Auto Mode for pre define multiblock transfer using DMA transfer For details on auto mode operation see section 14 Direct Memory Access Controller DMAC 0 Disable auto mode 1 Enable auto mode 5 to 3 All 0 R Reserved These bits are always read as 0 The write value should always be 0 2 to 0 SET 2 0 000 R W Sets DMA request signal as...

Page 1386: ...YIE Bit Bit Name Initial Value R W Description 7 INTRQ3E 0 R W FRDY Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled 6 to 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 CDIE 0 R W Card Detection Flag Enable 0 Setting of card detection flag disabled 1 Setting of card detection flag enabled 0 FRDYIE 0 R W FIFO Ready Completion Flag Enable 0 Setting o...

Page 1387: ... CDI 0 R W Card Identification Flag Identifies insert pullout of card variation between high and low of card identification signal Setting 1 condition When insert pullout of card is identified while CDIE 1 Clearing 0 condition Write 0 after reading CDI 1 FRDY 1 FRDY_TU 1 R When the set condition of FRDYI is met Read value 0 Remaining data in FIFO meets the assert condition specified by DMACR 1 Rem...

Page 1388: ...e Initial Value R W Description 7 to 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 1 R Reserved This bit is always read as 1 The write value should always be 1 0 CDB 0 R Card Identification State Indication Indicates insert pullout of card 0 Card not inserted mmc_cd 1 1 Card inserted mmc_cd 0 Note mmc_cd 0 indicates the card is inserted The polarity of the...

Page 1389: ...nitial value R W GATE_ CDB Bit Bit Name Initial Value R W Description 7 to 3 All 0 R Reserved These bits are always read as 0 The write value should always be 0 2 GATE_CDB 0 R W Clock Control at Card Identification Stops the clock supply to FF that is not required at card identification 0 Peripheral clock 1 and internal divided clock operating 1 Peripheral clock 1 and internal divided clock halted...

Page 1390: ... 1 0 0 1 1 R R R R W R W R W R W R W CHAT Bit Initial value R W Bit Bit Name Initial Value R W Description 7 to 5 000 R The read value is 0 The write value should be 0 4 to 0 CHAT 10011 R W Frequency for Chattering Elimination Pulse Cycle 00000 to 01000 and 11000 to 11111 setting prohibited Chattering elimination pulse cycle Term sec 2char Pck1 frequency MHz Pck1 Peripheral clock 1 Chattering An u...

Page 1391: ...al Notation 2chat Pck1 33 MHz 01001 9 512 0 015 ms 01010 10 1024 0 031 ms 01011 11 2048 0 061 ms 01100 12 4096 0 123 ms 01101 13 8192 0 246 ms 01110 14 16384 0 492 ms 01111 15 32768 0 983 ms 10000 16 65536 1 966 ms 10001 17 131072 3 932 ms 10010 18 262144 7 864 ms 10011 19 524288 15 729 ms 10100 20 1048576 31 457 ms 10101 21 2097152 62 915 ms 10110 22 4194304 125 829 ms 10111 23 8388608 251 658 ms...

Page 1392: ...e card The data busy state is indicated by a 0 output from the card through the DAT pin Notes Do not connect or disconnect the card during command sequence execution or in the data busy state 31 4 1 Operations in MMC Mode MMC mode is an operating mode in which the transfer clock is output from the MMC_CLK pin command transmission response reception occurs via the MMC_CMD pin and data is transmitte...

Page 1393: ...e card immediately aborts the CID output One card that has completed its output enters the acknowledge state When the R2 response is necessary set the CTOCR register to H 01 A relative address RCA is given to the card in the acknowledge state through CMD3 A card that can acquire an RCA enters the standby state By repeating CMD2 and CMD3 an RCA is given to all cards in the ready state to put the ca...

Page 1394: ...mmands that do not require a command response Create settings to issue the command Set the START bit in CMDSTRT to 1 to start command transmission The end of the command sequence is detected by poling the BUSY flag in CSTR or through the command output end interrupt CMDI Input output pins Command output 48 bits Command transmission started Command transmission ended Command transmission period Com...

Page 1395: ...ude a number of commands that do not include data transfer Such commands execute the desired data transfer using command arguments and command responses For a command that is related to time consuming processing such as flash memory write erase the card indicates the data busy state via the DAT Figures 31 4 and 31 5 show examples of the command sequence for commands without data transfer Figure 31...

Page 1396: ...he DTBUSY_TU bit in CSTR If data busy is detected the end of data busy state is detected through the data busy end interrupt DBSYI Write the CMDOFF bit to 1 when a CRC error CRCERI or command timeout error CTERI occurs Input output pins Command output 48 bits Command transmission started Command response reception No busy state Command transmission period Command sequence execution period Response...

Page 1397: ...ssion started Command response reception Command transmission period Command sequence execution period Response reception completed Data busy period Busy state completed Busy state CLK CMD DAT CMDSTRT START INTSTR0 CMDI CSTR CWRE BUSY REQ CRPI DBSYI DTBUSY_TU Figure 31 5 Example of Command Sequence for Commands without Data Transfer with Data Busy State ...

Page 1398: ...t in CMDSTRT to 1 Yes No CRCERI interrupt detected Yes No CRPI interrupt detected Yes No R1b response Yes No DTBUSY detected Yes No Yes No DBSYI interrupt detected End of command sequence CTERI interrupt detected Set the CMDOFF to 1 Note In R2 command response case determine whether or not error exists through CRC check by software Hardware executes no CRC check Figure 31 6 Example of Operational ...

Page 1399: ...1 7 to 31 9 show examples of the command sequence for commands with read data Figures 31 10 to 31 12 show the operational flows for commands with read data Create settings to issue the command and clear FIFO Set the START bit in CMDSTRT to 1 to start command transmission Command transmission completion can be confirmed through the command transmit end interrupt CMDI The command response is receive...

Page 1400: ...nded write 1 to the CMDOFF bit before command response reception CRPI the command response may not be received correctly Therefore to receive the command response the command sequence must be continued set the RD_CONTI bit to 1 until the command response reception ends Input output pins Command Command response Read data Command transmission started Single block read command execution sequence CLK...

Page 1401: ...data reception suspended Read data Read data Block data reception resumed Reading data from FIFO Single block read command execution sequence Command transmission started CLK CMD DAT CMDSTRT START INTSTR0 CMDI CMDOFF CSTR CWRE BUSY REQ CRPI DTI FFI FIFO_FULL CMD17 READ_SINGLE_BLOCK OPCR RD_CONTI Command response Figure 31 8 Example of Command Sequence for Commands with Read Data Block Size FIFO Si...

Page 1402: ...iblock read command execution sequence Stop command execution sequence CLK CMD DAT CMDSTRT START INTSTR0 CMDI CMDOFF CSTR CWRE BUSY REQ CRPI DTI FFI FIFO_FULL CMD18 READ_MULTIPLE_BLOCK CMD12 STOP_TRANSMISSION OPCR RD_CONTI Command Command response Read data Read data Read data Command Command transmission started Command response Figure 31 9 Example of Command Sequence for Commands with Read Data ...

Page 1403: ...status normally ended Yes No End of command sequence CTERI interrupt detected Yes No FFI interrupt detected Set the CMDOFF to 1 Read data from FIFO Set the RD_CONTI to 1 Read data from FIFO No Yes DTERI interrupt detected No Yes CRCERI interrupt detected No Yes Legend Len Block length Byte Cap FIFO size Byte n FFI Number of FFI from read sequence starts DTERI interrupt detected Yes No DTI interrup...

Page 1404: ...ponse register Execute CMD18 CMDR to CMDSTRT Set the number of transfer block size to TBCR No Yes CRCERI interrupt detected Yes No CMD16 normally ended Yes No CRPI interrupt detected Yes No Response status normally ended Yes No CTERI interrupt detected 1 2 Figure 31 11 1 Example of Operational Flow for Commands with Read Data Open ended Multiblock Transfer ...

Page 1405: ...Yes CRCERI interrupt detected No Yes Legend Len Block length Byte Cap FIFO size Byte n FFI Number of FFI from read sequence starts n DTI Number of DTI from read sequence start DTERI interrupt detected Yes No Next block read Yes No DTI interrupt detected Yes No Cap Len 1 n DTI Cap n FFI Set the CMDOFF to 1 Execute CMD12 Set the CMDOFF to 1 Execute CMD12 Clear FIFO 1 2 Figure 31 11 2 Example of Oper...

Page 1406: ...STRT Set the number of transfer block size to TBCR No Yes CRCERI interrupt detected Yes No CMD16 normally ended Execute CMD23 Set the number of transfer block TBCR Yes No CMD23 normally ended Yes No CRPI interrupt detected Yes No Response status normally ended Yes No CTERI interrupt detected 1 2 Figure 31 12 1 Example of Operational Flow for Commands with Read Data Pre defined Multiblock Transfer ...

Page 1407: ...No Yes Legend Len Block length Byte Cap FIFO size Byte n FFI Number of FFI from read sequence starts n DTI Number of DTI from read sequence start DTERI interrupt detected Yes No BTI interrupt detected Yes No DTI interrupt detected Yes No Cap Len 1 n DTI Cap n FFI Yes No TBNCR value n DTI Set the CMDOFF to 1 Execute CMD12 Read data from FIFO Set the CMDOFF to 1 Clear FIFO 1 2 Figure 31 12 2 Example...

Page 1408: ...e for commands with write data Figures 31 16 to 31 18 show the operational flows for commands with write data Create settings to issue a command and clear FIFO Set the START bit in CMDSTRT to 1 to start command transmission The command response is received from the card If the card returns no command response the command response is detected through the command timeout error CTERI Set the write da...

Page 1409: ... error CRCERI or data timeout error DTERI occurs in the write data transmission Input output pins Command Command response Command transmission started Single block write command execution sequence Write data Status Busy CLK CMD DAT CMDSTRT START INTSTR0 CMDI CMDOFF CSTR CWRE BUSY DTBUSY_TU REQ CRPI DTI DBSYI FEI FIFO_EMPTY CMD24 WRITE_SINGLE_BLOCK OPCR DATAEN DRPI Figure 31 13 Example of Command ...

Page 1410: ...k transmission resumed Block data transmission suspended Writing data to FIFO Write data Write data CLK CMD DAT CMDSTRT START INTSTR0 CMDI CMDOFF CSTR CWRE BUSY DTBUSY_TU REQ CRPI DRPI DBSYI DTI FEI FIFO_EMPTY DTBUSY CMD24 WRITE_SINGLE_BLOCK OPCR DA TA EN Block data transmission resumed Single block write command execution sequence Figure 31 14 Example of Command Sequence for Commands with Write D...

Page 1411: ...NTSTR0 CMDI CMDOFF CSTR CWRE BUSY DTBUSY_TU REQ CRPI DRPI DBSYI DTI FEI FIFO_EMPTY DTBUSY CMD25 WRITE_MULTIPE_BLOCK CMD12 STOP_TRANSMISSION OPCR DATAEN Command Command response Command Command response Command transmission started Block data transmission started Block data reception ended Next block data transmission started Figure 31 15 Example of Command Sequence for Commands with Write Data Mul...

Page 1412: ...ly ended Yes No End of command sequence CTERI interrupt detected Set the CMDOFF to 1 Writing data to FIFO Set the DATAEN to 1 Yes DTBUSY detected Yes DBSYI interrupt detected No Yes CRCERI interrupt detected No Yes Legend Len Block length Byte Cap FIFO size Byte n FEI Number of FEI from write sequence starts DTERI interrupt detected Yes No DRPI interrupt detected Yes Cap n FEI Len No No Yes DTI in...

Page 1413: ...ponse register Execute CMD25 CMDR to CMDSTRT Set the number of transfer block size to TBCR No Yes CRCERI interrupt detected Yes No CMD16 normally ended Yes No CRPI interrupt detected Yes No Response status normally ended Yes No CTERI interrupt detected 1 2 Figure 31 17 1 Example of Operational Flow for Commands with Write Data Open ended Multiblock Transfer ...

Page 1414: ...k size or FIFO size or for FIFO size block size FIFO size Len Block length Byte Cap FIFO size Byte n FEI Number of FEI from write sequence starts n DRPI Number of DRPI from write sequence starts Legend DTERI interrupt detected Yes No DRPI interrupt detected Yes Cap n FEI Len 1 n DRPI Len No No Yes DTI interrupt detected No Yes FEI interrupt detected No Set the CMDOFF to 1 Set the CMDOFF to 1 Execu...

Page 1415: ...register Execute CMD25 CMDR to CMDSTRT Set the number of transfer block size to TBCR No Yes CRCERI interrupt detected Yes No CMD16 normally ended Yes No CRPI interrupt detected Yes No Response status normally ended Yes No CTERI interrupt detected Execute CMD 23 Yes No CMD 23 normally ended 1 2 Figure 31 18 1 Example of Operational Flow for Commands with Write Data Pre defined Multiblock Transfer ...

Page 1416: ... FIFO size Len Block length Byte Cap FIFO size Byte n FEI Number of FEI from write sequence starts n DRPI Number of DRPI from write sequence starts Legend DTERI interrupt detected Yes No DRPI interrupt detected Yes Cap n FEI Len 1 n DRPI Len No No Yes TBNCR n DRPI No Yes BTI interrupt detected No Yes DTI interrupt detected No Yes FEI interrupt detected No Set the CMDOFF to 1 Set the CMDOFF to 1 Se...

Page 1417: ...pre defined multiblock transfer end flag BTI An error in a command sequence during data reception is detected through the CRC error flag or data timeout flag When these flags are detected set the CMDOFF bit in OPCR to 1 issue CMD12 and suspend the command sequence The data remains in FIFO after the read sequence end Set the SET 2 0 bits in DMACR to 100 to read all data left in FIFO if necessary Co...

Page 1418: ...D16 normally ended No Yes CRPI interrupt detected No Yes Response status normally ended No Yes CTERI interrupt detected No Yes CRCERI interrupt detected Yes No Set the number of transfer block size to TBCR Set the number of transfer block to TBCR Execute CMD 18 CMDR to CMDSTRT Execute CMD 23 CMD 23 normally ended No Yes 1 2 Figure 31 19 1 Example of Operational Flow for Auto mode Pre defined Multi...

Page 1419: ...to 1 Clear the DMACR to H 00 Clear the DMACR to H 00 Clear FIFO Execute CMD12 Set the CMDOFF to 1 Clear the DMACR to H 00 Set the CMDOFF to 1 BTI interrupt detected No Yes DMA transfer ended No Yes CRCERI interrupt detected Yes No DTERI interrupt detected Yes No 1 2 Figure 31 19 2 Example of Operational Flow for Auto mode Pre defined Multiblock Read Transfer ...

Page 1420: ...command sequence is detected by poling the BUSY flag in CSTR or through the pre defined multiblock transfer end flag BTI An error in a command sequence during data transmission is detected through the CRC error flag CRCERI or data timeout error flag When these flags are detected set the CMDOFF bit in OPCR to 1 issue CMD12 and suspend the command sequence Confirm there is no data busy condition Det...

Page 1421: ... CMD16 normally ended No Yes CRPI interrupt detected No Yes Response status normally ended No Yes CTERI interrupt detected No Yes CRCERI interrupt detected Yes No Set the number of transfer block size to TBCR Execute CMD 25 CMDR to CMDSTRT 2 Set the number of block to TBNCR Execute CMD 23 CMD 23 normally ended No Yes 1 Figure 31 20 1 Example of Operational Flow for Auto mode Pre defined Multiblock...

Page 1422: ...d No Yes CRCERI or WRERI interrupt detected Yes No DTERI interrupt detected Yes No DTBUSY detected No Yes Clear the DMACR to H 00 DMA transfer ended No Yes 1 2 Set the CMDOFF to 1 Clear FIFO Clear the DMACR to H 00 Execute CMD12 or Stop Tran Set the CMDOFF to 1 Set the CMDOFF to 1 Figure 31 20 2 Example of Operational Flow for Auto mode Pre defined Multiblock Write Transfer ...

Page 1423: ...the enable bits in INTCR0 to INTCR2 Disabled interrupt sources do not set a flag Table 31 8 MMCIF Interrupt Sources Name Interrupt source Interrupt flag Write error WRERI CRC error CRCERI Data timeout error DTERI ERR Command timeout error CTERI FSTAT FIFO empty FEI FIFO full FFI TRAN Data response DRPI Data transfer end DTI Command response end CRPI Command output end CMDI Data busy end DBSYI Bloc...

Page 1424: ...ntification mode Data transfer Card identified No Yes Card identification clock is always operating CDIE setting Wait for card to be inserted to connector Card is inserted to connector Interrupt generated Data transfer between MMCIF and card Peripheral clock 1 and internal divided clock are halted to stop unnecessary FF operation Peripheral clock 1 and internal divided clock are operated to end ca...

Page 1425: ...o this LSI 32 1 Features As a PC card interface to be connected to physical area 6 an IC memory card interface and an I O card interface are supported Outputs control signals for the external buffer PCC_DRV Supports a preemptive operating system by switching attribute memory common memory and I O space by using addresses Provides a segment bit an address bit for the PC card for common memory enabl...

Page 1426: ...DY IREQ PCC_BVD1 STSCHG PCC_BVD2 SPKR PCC_CD1 PCC_CD2 PCC_VS1 PCC_VS2 PCC_REG PC card controller PCC Area 6 An IC memory card interface and an I O card interface are supported Area 6 internal interrrupt signal Area 6 PC card interface signal register 0 3 and register control Figure 32 1 PC Card Controller Block Diagram 32 1 1 PCMCIA Support This LSI supports an interface based on PCMCIA specificat...

Page 1427: ...OD of the general control register enables the continuous 32 Mbyte area mode In this mode the attribute memory space and I O memory space are 32 Mbytes and the common memory space is 64 Mbytes In the common memory space set 1 in bit 2 P0PA25 of the general control register to access an address of more than 32 Mbytes By this operation 1 is output to A25 pin enabling an address space of more than 32...

Page 1428: ...eneral control register to access an address of more than 16 Mbytes By this operation values are output to A25 and A24 pins enabling an address space of more than 16 Mbytes to be accessed initial value 0 for P0PA25 and P0PA24 When an address of 16 Mbytes or less is accessed no settings are required This bit does not affect access to attribute memory space or I O memory space Figure 32 3 shows the ...

Page 1429: ...16 Mbytes 16 Mbytes Attribute memory 16 Mbytes Pin PCCREG is always 0 Common memory Total 64 Mbytes Not used General control register bit settings P0MMOD 1 P0REG x H 18000000 H 1A000000 Area 6 P0PA25 P0PA24 x Don t care Common memory Pin PCCREG is always 1 P0PA25 x P0PA24 x P0PA25 0 P0PA24 0 P0PA25 0 P0PA24 1 P0PA25 1 P0PA24 0 P0PA25 1 P0PA24 1 P0PA25 x P0PA24 x Figure 32 3 Continuous 16 Mbyte Are...

Page 1430: ...O card interface is connected PCMCIA BVD1 pin PCC_BVD1 Input Buttery voltage detect 1 signal from PC card when IC memory interface is connected Card status change signal from PC card when I O card interface is connected PCMCIA BVD2 pin PCC_BVD2 Input Buttery voltage detect 2 signal from PC card when IC memory interface is connected Digital sound signal from PC card when I O card interface is conne...

Page 1431: ...4 H 1FE9 8004 8 Area 6 card status change interrupt enable register PCC0CSCIER R W H FFE9 8006 H 1FE9 8006 8 Note P4 addresses are used when area P4 in the virtual address space is used and area 7 addresses are used when accessing the register through area 7 in the physical address space using the TLB Table 32 4 Register State in Each Operating Mode Register Name Abbreviation Power On Reset Manual...

Page 1432: ...The value of RDY BSC pin of the PC card connected to area 6 is read when the IC memory card interface is connected The value of IREQ pin of the PC card connected to area 6 is read when the I O card interface is connected This bit cannot be written to Indicates that the value of RDY BSC pin is 0 when the PC card connected to area 6 is the IC memory card interface type Indicates that the value of IR...

Page 1433: ...nected to area 6 is the IC memory card interface type 5 P0VS2 Undefined R PCC0 Voltage Sense 2 The value of VS2 pin of the PC card connected to area 6 is read This bit cannot be written to 0 The value of VS2 pin of the PC card connected to area 6 is 0 1 The value of VS2 pin of the PC card connected to area 6 is 1 4 P0VS1 Undefined R PCC0 Voltage Sense 1 The value of VS1 pin of the PC card connecte...

Page 1434: ...rea 6 are read when the IC memory card interface is connected The values of SPKR and STSCHG pins of the PC card connected to area 6 are read when the I O card interface is connected These bits cannot be written to IC memory interface 11 The battery voltage of the PC card connected to area 6 is normal Battery Good 01 The battery must be changed although data is guaranteed for the PC card connected ...

Page 1435: ...e external buffer for the PC card connected to area 6 0 High level setting for control PCC_DRV pin of the external buffer for the PC card connected to area 6 1 Low level setting for control PCC_DRV pin of the external buffer for the PC card connected to area 6 6 P0PCCR 0 R W PCC0 Card Reset Controls resets for the PC card connected to area 6 0 Low level setting for reset PCC_RESET pin for the PC c...

Page 1436: ...is set to 1 bits 15 to 12 TYPE3 to TYPE0 in CS6BBCR of BSC should be set to 0101 3 P0MMOD 0 R W PCC0 Mode Controls PCC_REG and A24 pins for the PC card connected to area 6 Specifies either A24 of the address to be accessed or bit P0REG for outputting to PCC_REG pin When the common memory space is accessed specifies either A24 of the address to be accessed or bit P0PA24 for outputting to A24 pin By...

Page 1437: ...and the common memory space is accessed for the PC card connected to area 6 this bit is output to A24 pin When bit P0MMOD is 0 or the attribute memory space or I O space is accessed this bit is meaningless 0 When bit P0MMOD is 1 and the common memory space is accessed for the PC card connected to area 6 0 is output to A24 pin 1 When bit P0MMOD is 1 and the common memory space is accessed for the P...

Page 1438: ...P0CDC P0RC P0BW P0BD Bit Bit Name Initial Value R W Description 7 P0SCDI 0 R W PCC0 Software Card Detect Change Interrupt A PCC0 software card detect change interrupt can be generated by writing 1 to this bit When this bit is set to 1 the same interrupt as the PCC0 card detect change interrupt bit 3 set status occurs if bit 3 PCC0 card detect change enable in the area 6 card status change interrup...

Page 1439: ... if the IREQ pin is low 1 is read This bit always reads 0 on the IC memory card interface 0 No interrupt request on the IREQ pin of the PC card when the PC card is on the I O card interface 1 An interrupt request on the IREQ pin of the PC card has occurred when the PC card is on the I O card interface 4 P0SC 0 R W PCC0 Status Change Indicates a change in the value of the STSCHG pin of the PC card ...

Page 1440: ...ard are not changed 1 CD1 and CD2 pins in the PC card are changed 2 P0RC 0 R W PCC0 Ready Change Indicates a change in the value of the RDY BSY pin of the PC card when the PC card connected to area 6 is the IC memory card interface type When the RDY BSY pin is changed from 0 to 1 the P0RC bit is set to 1 When the RDY BSY pin is not changed the P0RC bit remains at 0 Write 0 to bit 2 in order to cle...

Page 1441: ...e in the battery warning state and the battery must be changed although the data is guaranteed when the PC card is on the IC memory card interface 0 P0BD 0 R W PCC0 Battery Dead Indicates whether the BVD2 and BVD1 pins of the PC card are in the state in which the battery must be changed since the data is not guaranteed when the PC card connected to area 6 is on the IC memory card interface When th...

Page 1442: ...d PCC0CSCIER is initialized by a power on reset but retains its value in a manual reset and in software standby mode 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W P0CRE IREQE 1 0 P0SCE P0CDE P0RE P0BWE P0BDE Bit Bit Name Initial Value R W Description 7 P0CRE 0 R W PCC0 Card Reset Enable When this bit is set to 1 and when the CD1 and CD2 pins detect that a PC...

Page 1443: ...r the PC card connected to area 6 Bit 5 in the status change register PCC0CSCR functions as a read only bit that indicates the inverse of the IREQ pin signal 01 The level mode IREQ interrupt request signal is accepted for the PC card connected to area 6 In level mode an interrupt occurs when level 0 of the signal input from the IREQ pin is detected 10 The pulse mode IREQ interrupt request signal i...

Page 1444: ... P0CDE 0 R W PCC0 Card Detect Change Enable Bit 3 enables or disables the interrupt request when the values of the CD1 and CD2 pins are changed 0 No interrupt occurs for the PC card connected to area 6 regardless of the values of the CD1 and CD2 pins 1 An interrupt occurs for the PC card connected to area 6 when the values of the CD1 and CD2 pins are changed 2 P0RE 0 R W PCC0 Ready Change Enable W...

Page 1445: ...lthough the data is guaranteed 1 An interrupt occurs when the BVD2 and BVD1 pins are in the state in which the battery must be changed although the data is guaranteed 0 P0BDE 0 R W PCC0 Battery Dead Enable When the PC card connected to area 6 is on the IC memory card interface bit 0 enables or disables the interrupt request when the BVD2 and BVD1 pins are in the state in which the battery must be ...

Page 1446: ...ence CE1B CE2B RD WE IORD IOWR PCC_RESET PCC_REG PCC_WAIT PCC_IOIS16 PCC_RDY PCC_BVD1 PCC_BVD2 A25 to A0 PCC0DRV D15 to D0 SH7763 A25 to A0 D15 to D0 D7 to D0 D15 to D8 RDWR PCC_CD1 CD2 PCC_VS1 VS2 CE1 CE2 OE WE PGM IORD IOWR RESET REG WAIT WP IOIS16 RDY BSY IREQ BVD1 STSCHG BVD2 SPKR CD1 CD2 VS1 VS2 G G G G DIR G DIR Area 6 PC card memory or I O Figure 32 4 SH7763 Interface ...

Page 1447: ...0 I Address A10 9 OE I Output enable OE I Output enable RD 10 A11 I Address A11 I Address A11 11 A9 I Address A9 I Address A9 12 A8 I Address A8 I Address A8 13 A13 I Address A13 I Address A13 14 A14 I Address A14 I Address A14 15 WE PGM I Write enable WE PGM I Write enable WE 16 RDY BSY O Ready busy IREQ O Interrupt request PCC_RDY 17 VCC Power supply VCC Power supply 18 VPP1 Programming power su...

Page 1448: ... I O port PCC_IOIS16 34 GND Ground GND Ground 35 GND Ground GND Ground 36 CD1 O Card detection CD1 O Card detection PCC_CD1 37 D11 I O Data D11 I O Data D11 38 D12 I O Data D12 I O Data D12 39 D13 I O Data D13 I O Data D13 40 D14 I O Data D14 I O Data D14 41 D15 I O Data D15 I O Data D15 42 CE2 I Card enable CE2 I Card enable CE2B 43 VS1 O Voltage sense VS1 O Voltage sense PCC_VS1 44 RFU Reserved ...

Page 1449: ...dress A25 I Address A25 57 VS2 O Voltage sense VS2 O Voltage sense PCC_VS2 58 RESET I Reset RESET I Reset PCC_RESET 59 WAIT O Wait request WAIT O Wait request PCC_WAIT 60 RFU Reserved INPACK O Input acknowledge 61 REG I Attribute memory space select REG I Attribute memory space select PCC_REG 62 BVD2 O Battery voltage detection SPKR O Digital sound signal PCC_BVD2 63 BVD1 O Battery voltage detecti...

Page 1450: ...1384 of 1956 REJ09B0256 0100 32 4 2 PC Card Interface Timing 1 Memory Card Interface Timing Tpcm1 Tpcm2 CLKOUT PCC_DRV CExx RDWR A25 to A0 WE read PCC_REG RD read 0 0 D15 to D0 write PCC_RESET D15 to D0 write Figure 32 5 PCMCIA Memory Card Interface Basic Timing ...

Page 1451: ...2007 Page 1385 of 1956 REJ09B0256 0100 Tpcm0 Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w CLKOUT PCC_DRV PCC_WAIT CExx RDWR A25 to A0 WE read PCC_REG RD read 0 0 D15 to D0 write PCC_RESET D15 to D0 write Figure 32 6 PCMCIA Memory Card Interface Wait Timing ...

Page 1452: ...Oct 01 2007 Page 1386 of 1956 REJ09B0256 0100 2 I O Card Interface Timing Tpcm1 Tpcm2 CLKOUT PCC_DRV CExx RDWR A25 to A0 IOWR read PCC_REG IORD read 0 0 D15 to D0 write PCC_RESET D15 to D0 write Figure 32 7 PCMCIA I O Card Interface Basic Timing ...

Page 1453: ...age 1387 of 1956 REJ09B0256 0100 Tpci0 Tpci0w Tpci1 Tpci1w Tpci1w Tpci2 Tpci2w CLKOUT PCC_DRV PCC_WAIT CExx RDWR A25 to A0 IOWR read PCC_REG IORD read 0 D15 to D0 write PCC_IOIS16 D15 to D0 write 0 PCC_RESET Figure 32 8 PCMCIA I O Card Interface Wait Timing ...

Page 1454: ...f 1956 REJ09B0256 0100 Tpci0 Tpci1 Tpci1w Tpci2 Tpci1 Tpci1w Tpci2 Tpci2w CLKOUT PCC_DRV PCC0WAIT CExx RDWR A25 to A1 A0 IOWR read PCC_REG IORD read 0 D15 to D0 read IOIS16 D15 to D0 write 0 PCC_RESET Figure 32 9 Dynamic Bus Sizing Timing for PCMCIA I O Card Interface ...

Page 1455: ...on Access Time 3 3 V Operation Attribute memory 300 ns 600 ns Common memory 250 ns 600 ns I O space IORD IOWR pulse width 165 ns 165 ns 2 Pin Function Control and Card Type Switching When setting pin function controller pin functions to dedicated PC card use other function the disabled state should first be set in the card status change interrupt enable register PCC0CSCIER Also the card status cha...

Page 1456: ... a card controller 1 Set bit 12 MAP in the common control register CMNCR of bus state controller to 1 2 Set bits 15 to 12 TYPE3 to TYPE0 in the bus control register for CS6B CS6BBCR of the bus state controller to B 0101 3 Set bit 4 P0USE in the area 6 general control register in the PC card controller to 1 4 Set the pin function controller to custom PC card pin functions other functions ...

Page 1457: ...CPU or the DMA transfer by the DMAC can be used 33 1 Features The HAC has the following features Supports Digital interface to a single AC 97 version 2 1 Audio Codec PIO transfer of status slots 1 and 2 in Rx frames PIO transfer of command slots 1 and 2 in Tx frames PIO transfer of data slots 3 and 4 in Rx frames PIO transfer of data slots 3 and 4 in Tx frames Selectable 16 bit or 20 bit DMA trans...

Page 1458: ...Shift register for slot 4 Shift register for slot 1 Shift register for slot 2 Shift register for slot 3 Shift register for slot 4 DMA control DMA control CSAR TX buffer CSDR TX buffer PCML TX buffer PCMR TX buffer CSAR RX buffer CSDR RX buffer PCML RX buffer PCMR RX buffer Data 19 0 Data 19 0 Data 19 0 Data 19 0 DMA request DMA request Slot3 slot4 request signal Figure 33 1 Block Diagram 33 2 Inpu...

Page 1459: ...rol register HACACR R W H FFEB 0060 H 1FEB 0060 32 Note P4 addresses are used when area P4 in the virtual address space is used and area 7 addresses are used when accessing the register through area 7 in the physical address space using the TLB Table 33 3 Register State in Each Operating Mode Register Name Abbrev Power on Reset Manual Reset Sleep Standby Control and status register HACCR H 0000 02...

Page 1460: ... R R R R R R R R R R R R R 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 R R R R W W R R R R W R R R R R CR CDRT WMRT ST Bit Bit Name Initial Value R W Description 31 to 16 All 0 R Reserved Always 0 for read and write 15 CR 0 R Codec Ready 0 The HAC connected codec is not ready 1 The HAC connected codec is ready 14 to 12 All 0 R Reserved Always read as 0 Write prohibited 11 CDRT 0 W HAC Cold Reset Use a cold re...

Page 1461: ...ST 0 W Start Transfer Write 1 Starts data transmission reception 0 Stops data transmission reception at the end of the current frame Do not take this action to terminate transmission reception in normal operation Read access Always read as 0 4 to 0 All 0 R Reserved Always 0 for read and write To place the off chip codec device into the power down mode write 1 to bit 12 of the register index 26 in ...

Page 1462: ...Bit Initial value R W Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R R R R R R R R R R R R RW CA SA 6 4 CA SA 3 0 SLREQ 3 12 Bit Bit Name Initial Value R W Description 31 to 20 All 0 R Reserved Always 0 for read and write 19 RW 0 R W Codec Read Write Command 0 Notifies the off chip codec device of a wr...

Page 1463: ...ister to be written Read Indicate the status address received via slot 1 corresponding to the codec register whose data has been returned in HACCSDR 11 to 2 SLREQ 3 12 All 0 R Slot Requests 3 to 12 Valid only in the Rx frame Indicate whether the codec is requesting slot data in the next Tx frame Automatically set by hardware and correspond to bits 11 to 2 of slot 1 in the Rx frame 0 Slot data is r...

Page 1464: ... 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R R R R CD SD 15 12 CD SD 11 0 Bit Bit Name Initial Value R W Description 31 to 20 All 0 R Reserved Always 0 for read and write 1...

Page 1465: ...R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W D 19 16 D 15 0 Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 20 All 0 R Reserved Always 0 for read and write 19 to 0 D 19 0 All 0 R W Data 19 to 0 Write the PCM playback left channel data to these bits The HAC then transmits the data to the codec on an ...

Page 1466: ...ft channel data to these bits The HAC then transmits the data to the codec on an on demand basis Read these bits to get the PCM record left channel data from the codec 15 to 0 RD 15 0 All 0 R W Right Data 15 to 0 Write the PCM playback right channel data to these bits The HAC then transmits the data to the codec on an on demand basis Read these bits to get the PCM record right channel data from th...

Page 1467: ...ith ADC DAC resolution of 20 bit or less 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W D 19 16 D 15 0 Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 ...

Page 1468: ...value R W Bit Bit Name Initial Value R W Description 31 30 All 0 R Reserved Always 0 for read and write 29 PLTFRQIE 0 R W PCML TX Request Interrupt Enable 0 Disables PCML TX request interrupts 1 Enables PCML TX request interrupts 28 PRTFRQIE 0 R W PCMR TX Request Interrupt Enable 0 Disables PCMR TX request interrupts 1 Enables PCMR TX request interrupts 27 to 10 All 0 R Reserved Always 0 for read ...

Page 1469: ... R W Bit Bit Name Initial Value R W Description 31 CMDAMT 1 R W 2 Command Address Empty 0 CSAR Tx buffer contains untransmitted data 1 CSAR Tx buffer is empty and ready to store data 1 30 CMDDMT 1 R W 2 Command Data Empty 0 CSDR Tx buffer contains untransmitted data 1 CSDR Tx buffer is empty and ready to store data 1 29 PLTFRQ 1 R W 2 PCML TX Request 0 PCML Tx buffer contains untransmitted data 1 ...

Page 1470: ...ot written to PCMR 7 to 0 All 0 R Reserved Always 0 for read and write Notes 1 CMDAMT and CMDDMT have no associated interrupts Poll these bits until they are read as 1 before writing a new command to HACCSAR HACCSDR When bit 19 RW of HACCSAR is 0 and TX12_ATOMIC is 1 take the following steps 1 Initialize CMDDMT and CMDAMT before first accessing a codec register after HAC initialization by any rese...

Page 1471: ...tatus Address Ready Interrupt Enable 0 Disables status address ready interrupts 1 Enables status address ready interrupts 21 STDRYIE 0 R W Status Data Ready Interrupt Enable 0 Disables status data ready interrupts 1 Enables status data ready interrupts 20 PLRFRQIE 0 R W PCML RX Request Interrupt Enable 0 Disables PCML RX request interrupts 1 Enables PCML RX request interrupts 19 PRRFRQIE 0 R W PCM...

Page 1472: ...Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 23 All 0 R Reserved Always 0 for read and write 22 STARY 0 R W Status Address Ready 0 HACCSAR status address is not ready 1 HACCSAR status address is ready 21 STDRY 0 R W Status Data Ready 0 HACCSDR status data is not ready 1 HACCSDR status data is ready 20 PLRFRQ 0 R W PCML RX Request 0 PCML RX data is no...

Page 1473: ... 0 to the bit initializes it but writing 1 has no effect 33 3 10 HAC Control Register HACACR HACACR is a 32 bit read write register used for controlling the HAC interface 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 R R W R W R R R W R R W R W R W R W R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R D...

Page 1474: ...tely Setting prohibited 1 Transmits TX data in HACCSAR and that in HACCSDR in the same frame if bit 19 in HACCSAR is 0 write HACCSAR must be written last 25 0 R Reserved Always 0 for read and write 24 RXDMAL_EN 0 R W RX DMA Left Enable 0 Disables 20 bit RX DMA for HACPCML 1 Enables 20 bit RX DMA is for HACPCML 23 TXDMAL_EN 0 R W TX DMA Left Enable 0 Disables 20 bit TX DMA for HACPCML 1 Enables 20 ...

Page 1475: ...3 4 AC97 Transmit Frame Structure Slot Name Description 0 SDATA_OUT TAG Codec IDs and Tags indicating valid data 1 Control CMD Addr write port Read write command and register address 2 Control DATA write port Register write data 3 PCM L DAC playback Left channel PCM output data 4 PCM R DAC playback Right channel PCM output data 5 Modem Line 1 DAC Modem 1 output data unsupported 6 PCM Center Center...

Page 1476: ...ted 12 Modem IO status Modem control IO input unsupported Notes There is no register for unsupported functions 33 5 Operation 33 5 1 Receiver The HAC receiver receives serial audio data input on the HAC_SD_IN pin synchronous to HAC_BITCLK From slot 0 the receiver extracts tag bits that indicate which other slots contain valid data It will update the receive data only when receiving valid slot data...

Page 1477: ...X16 bits in HACACR When the data size is 20 bits transfer of data slots 3 and 4 requires two local bus access cycles Since each of the receiver and transmitter has its DMA request the stereo mode generates a DMA request for slots 3 and 4 separately The mono mode generates a DMA request for just one slot When the data size is 16 bits data from slots 3 and 4 are packed into a single 32 bit quantity ...

Page 1478: ...t DMA transfer Receiver Transmitter HACCR H 0000 0020 Codec ready HACCR H 0000 8000 Set DMAC Note Refer to section 14 Direct Memory Access Controller DMAC Set read address H 26 Power down Ctrl Stat HACCSAR H 000A 6000 External codec internal status ADC DAC Analog REF ready HACCSDR H 0000 00F0 Set read volume and sampling rate TX RX enable set HACACR H 03E0 0000 20 bit DMATX slot 1 and slot 2 are a...

Page 1479: ...Cnt to 0 TSR CMDAMT 1 TSR CMDDMT 1 Wait for 1 µs LoopCnt Necessary setting ACR TX12_ATOMIC 1 No Yes 5 RetryCnt Error Return E1 Number required for the target system 21 E1 1000 Notes RetryCnt Input Addr Address of the codec register to be written to Data Data to be written to the codec register RetryCnt Software counter for error detection LoopCnt Software counter for wait insertion Figure 33 4 Sam...

Page 1480: ... Read_codec_aux Input RegN address of the codec register to be read When extrnal codec register are read in saquence data in the last register that was read may be read again in some codec devices In this case use the read procedure shown in this flowchart Send_read_request RegN Error Error Error Error Error Data 2 return Send_read_request RegN Get_codec_data RegN Get_codec_data RegN Data 1 acquis...

Page 1481: ...No Yes Yes No Yes Get_codec_data Clear LoopCnt2 to 0 Input RegN address of the codec register to be read WaitLoop_RSR Addr R RegN Assign HACCSDR read value to DataT DataT return E2 Number required for the target system 13 E2 LoopCnt2 Software counter for wait insertion Addr Variable to hold CSAR read value DataT Variable to hold CSDR read value Notes Wait for 5ms LoopCnt2 Assign HACCSAR read value...

Page 1482: ...s E3 LoopCnt 3 Error No No Yes WaitLoop_RSR Clear LoopCnt4 to 0 Return Notes E3 and E4 Number required for the target system 21 E3 21 E4 1000 LoopCnt3 Software counter for wait insertion LoopCnt4 Software counter for wait insertion Error RSR STARY 1 RSR STDRY 1 Write 0 to RSR STARY Write 0 to RSR STDRY Yes E4 LoopCnt 4 Wait for 1µs LoopCnt4 Figure 33 7 Sample Flowchart for Off Chip Codec Register ...

Page 1483: ...face HAC Rev 1 00 Oct 01 2007 Page 1417 of 1956 REJ09B0256 0100 33 5 6 Notes The HAC_SYNC signal is generated by the HAC to indicate the position of slot 0 within a frame 33 5 7 Reference AC 97 Component Specification Revision 2 1 ...

Page 1484: ...Section 33 Audio Codec Interface HAC Rev 1 00 Oct 01 2007 Page 1418 of 1956 REJ09B0256 0100 ...

Page 1485: ...ts as well as support for a multi channel mode 34 1 Features The SSI has the following features Number of channels Four channel Operating modes Non compressed mode The non compressed mode supports all serial audio streams divided into channels The SSI module is configured as any of a transmitter or receiver The serial bus format can be used Asynchronous transfer between the buffer and the shift re...

Page 1486: ...ch0 Data buffer Shift register Control circuit Register SSICR SSISR SSITDR SSIRDR Barrel shifter Bit counter Serial clock control Divider Divider LS SSI0_SDATA SSI0_WS SSI0_SCK SSI1_SDATA SSI1_WS SSI1_SCK MS PAD A A SSI ch2 Divider SSI2_SDATA SSI2_WS SSI2_SCK A SSI ch3 Divider SSI3_SDATA SSI3_WS SSI3_SCK SSI_CLK A Figure 34 1 Block Diagram of SSI Module ...

Page 1487: ..._CLK Input Divider input clock oversampling clock 256 384 512fs input SSI0_WS I O Word select SSI0_SDATA I O Serial data input output 0 SSI0_SCK I O Serial bit clock SSI1_WS I O Word select SSI1_SDATA I O Serial data input output 1 SSI1_SCK I O Serial bit clock SSI2_WS I O Word select SSI2_SDATA I O Serial data input output 2 SSI2_SCK I O Serial bit clock SSI3_WS I O Word select SSI3_SDATA I O Ser...

Page 1488: ...000 32 Status register 1 SSISR1 R W H FFE5 8004 H 1FE5 8004 32 Transmit data register 1 SSITDR1 R W H FFE5 8008 H 1FE5 8008 32 1 Receive data register 1 SSIRDR1 R H FFE5 800C H 1FE5 800C 32 Control register 2 SSICR2 R W H FFE6 0000 H 1FE6 0000 32 Status register 2 SSISR2 R W H FFE6 0004 H 1FE6 0004 32 Transmit data register 2 SSITDR2 R W H FFE6 0008 H 1FE6 0008 32 2 Receive data register 2 SSIRDR2...

Page 1489: ...register 1 SSISR1 H 0010 A003 H 0x10 A00x Retained Retained Transmit data register 1 SSITDR1 H 0000 0000 H 0000 0000 Retained Retained 1 Receive data register 1 SSIRDR1 H 0000 0000 H 0000 0000 Retained Retained Control register 2 SSICR2 H 0000 0000 H 0000 0000 Retained Retained Status register 2 SSISR2 H 0010 A003 H 0x10 A00x Retained Retained Transmit data register 2 SSITDR2 H 0000 0000 H 0000 00...

Page 1490: ... Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W R W R W R W R W R W 0 0 0 R R R R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R R W R W R W R W R W R W R R W R W R W Bit Bit Name Initial Value R W Description 31 to 29 0 R Reserved These bits are always read as 0 The write value should always be 0 28 DMEN 0 R W DMA Enable Enables or disables the DMA re...

Page 1491: ...ta interrupt disabled 1 Data interrupt enabled 23 22 CHNL 1 0 00 R W Channels These bits indicate the number of channels in each system word 00 1 channel per system word 01 2 channels per system word 10 3 channels per system word 11 4 channels per system word 21 to 19 DWL 2 0 000 R W Data Word Length These bits indicate the encoded number of bits in a data word 000 8 Bits 001 16 Bits 010 18 Bits 0...

Page 1492: ... Bits 011 32 Bits 100 48 Bits 101 64 Bits 110 128 Bits 111 256 Bits 15 SCKD 0 R W Serial Bit Clock Direction 0 Serial clock input slave mode 1 Serial clock output master mode Note The SCKD and SWSD bits can be set both 0s or 1s 0 0 or 1 1 Other settings are prohibited 14 SWSD 0 R W Serial WS Direction 0 Serial word select input slave mode 1 Serial word select output master mode Note The SCKD and S...

Page 1493: ... rising edge SSI_SCK falling edge SSI_SDATA output change timing in transmit mode TRMD 1 SSI_SCK falling edge SSI_SCK rising edge SSI_WS input sampling in slave mode SWSD 0 SSI_SCK rising edge SSI_SCK falling edge SSI_WS output change timing in master mode SWSD 1 SSI_SCK falling edge SSI_SCK rising edge 12 SWSP 0 R W Serial WS Polarity 0 SSI_WS is low for the first channel high for the second chan...

Page 1494: ...R is left aligned 1 Parallel data SSITDR SSIRDR is right aligned DWL 000 with a data word length of 8 bits the PDTA setting is ignored All data bits in SSIRDR or SSITDR are used on the audio serial bus Four data words are transmitted or received at each 32 bit access The first data word is derived from bits 7 to 0 the second from bits 15 to 8 the third from bits 23 to 16 and the last data word is ...

Page 1495: ...its are ignored or reserved DWL 010 011 100 101 with a data word length of 18 20 22 or 24 bits PDTA 1 right aligned The data bits used in SSIRDR or SSITDR are the following Bits the number of bits in the data word length specified by DWL minus 1 to 0 i e if DWL 011 then DWL 20 and bits 19 to 0 are used in either SSIRDR or SSITDR All other bits are ignored or reserved DWL 110 with a data word lengt...

Page 1496: ...ling clock frequency 2 010 Serial bit clock frequency oversampling clock frequency 4 011 Serial bit clock frequency oversampling clock frequency 8 100 Serial bit clock frequency oversampling clock frequency 16 101 Serial bit clock frequency oversampling clock frequency 6 110 Serial bit clock frequency oversampling clock frequency 12 111 Setting prohibited 3 MUEN 0 R W Mute Enable 0 The SSI module ...

Page 1497: ... R R R W R R R R W R R R R R R R 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 R R R R R R R R R R R R R R R R Bit Bit Name Initial Value R W Description 31 to 29 R Reserved These bits are always read as an undefined value The write value should always be 0 28 DMRQ 0 R DMA Request Status Flag This status flag allows the CPU to see the status of the DMA request of SSI module TRMD 0 Receive Mode If DMRQ 1 then SS...

Page 1498: ...it indicates that SSIRDR was read out before DMRQ and DIRQ bits would indicate the existence of new unread data In this instance the same received data may be stored twice by the host which can lead to destruction of multi channel data When TRMD 1 Transmit Mode If UIRQ 1 it indicates that the transmitted data was not written in SSITDR By this the same data may be transmitted one time too often whi...

Page 1499: ...struction of multi channel data Note When overflow error occurs the data in the data buffer will be overwritten by the next data sent from the SSI interface When TRMD 1 Transmit Mode If OIRQ 1 it indicates that SSITDR had data written in before the data in SSITDR was transferred to the shift register This may cause the loss of data which can lead to destruction of multi channel data 25 IIRQ 0 2 R ...

Page 1500: ...read data exists in SSIRDR 1 Unread data exists in SSIRDR When TRMD 1 Transmit Mode 0 The transmit buffer is full 1 The transmit buffer is empty and requires that data be written in SSITDR 23 to 4 H 10A00 R Reserved These bits are always read as H 10A00 The write value should always be 0 3 2 CHNO 1 0 00 R Channel Number The number indicates the current channel When TRMD 0 Receive Mode This bit ind...

Page 1501: ...lag Indicates that the serial bus activity has ceased This bit is cleared if EN 1 and the Serial Bus is currently active This bit can be set to 1 automatically under the following conditions SSI Serial bus master transmitter SWSD 1 and TRMD 1 This bit is set to 1 if no more data has been written to SSITDR and the current system word has been completed It can also be set to 1 by clearing the EN bit...

Page 1502: ...20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Initial value R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 34 3 4 Receive Data Register SSIRDR SSIRDR is a 32 bit register that stores the received data Data in SSIRDR is...

Page 1503: ...us formats in either mode The bus formats can be one of eight major modes as shown in table 34 4 Table 34 4 Bus Formats of SSI Module Bus Format TPMD SCKD SWSD EN MUEN DIEN IIEN OIEN UIEN DEL PDTA SDTA SPDP SWSP SCKP SWL 2 0 DWL 2 0 CHNL 1 0 Non Compressed Slave Receiver 0 0 0 Non Compressed Slave Transmitter 1 0 0 Non Compressed Master Receiver 0 1 1 Non Compressed Master Transmitter 1 1 1 Contro...

Page 1504: ...m to the format as specified in the SSI module then operation is not guaranteed 3 Master Receiver This mode allows the SSI module to receive serial data from another device The clock and word select signals are internally derived from the HAC_BIT_CLK input clock The format of these signals is as defined in the SSI module If the incoming data does not conform to the defined format then operation is...

Page 1505: ..._SCK SSI_WS SSI_SDATA SCKP 0 SWSP 0 DEL 0 CHNL 00 System word length data word length Figure 34 2 Philips Format with no Padding MSB LSB MSB LSB Next System word 1 System word 2 Data word 1 Data word 2 Padding Padding SSI_SCK SSI_WS SSI_SDATA SCKP 0 SWSP 0 DEL 0 CHNL 00 SPDP 0 SDTA 0 System word length data word length Figure 34 3 Philips Format with Padding Figure 34 4 shows the format used by So...

Page 1506: ...0 DEL 1 CHNL 00 SPDP 0 SDTA 1 System word length data word length Figure 34 5 Matsushita Format with Padding Bits First Followed by Serial Data 6 Multi Channel Formats Some devices extend the definition of the specification by Philips and allow more than 2 channels to be transferred within two system words The SSI module supports the transfer of 2 3 and 4 channels by the use of the CHNL SWL and DW...

Page 1507: ...24 16 14 12 10 8 0 100 48 40 32 30 28 26 24 16 101 64 56 48 46 44 42 40 32 110 128 120 112 110 108 106 104 96 00 1 111 256 248 240 238 236 234 232 224 000 8 001 16 0 010 24 8 011 32 16 0 100 48 32 16 12 8 4 0 101 64 48 32 28 24 20 16 0 110 128 112 96 92 88 84 80 64 01 2 111 256 240 224 220 216 212 208 192 000 8 001 16 010 24 0 011 32 8 100 48 24 0 101 64 40 16 10 4 110 128 104 80 74 68 62 56 32 10...

Page 1508: ...ta is left aligned with padding bits Figure 34 8 shows the data transfer in which data is right aligned with padding bits This selection is purely arbitrary MSB LSB Data word 1 MSB LSB MSB LSB MSB LSB Data word 2 Data word 3 Data word 4 System word 1 System word 2 MSB LSB Data word 1 MSB LSB MSB LSB MSB LSB Data word 2 Data word 3 Data word 4 System word 1 System word 2 LSB MSB SSI_SCK SSI_WS SSI_...

Page 1509: ...SB LSB MSB LSB MSB LSB MSB LSB Data word 2 Data word 3 Data word 4 Data word 5 Data word 6 Data word 7 Data word 8 Padding System word 1 Padding SSI_WS SSI_SDATA SSI_SCK SCKP 0 SWSP 0 DEL 1 CHNL 11 SPDP 0 SDTA 1 System word length data word length 4 Figure 34 8 Multichannel Format 4 Channels with Padding Bits First Followed by Serial Data with Padding ...

Page 1510: ..._WS SSI_SDATA Key for this and following diagrams 0 0 0 0 0 0 means a low level on the serial bus padding or mute 0 means a high level on the serial bus padding 1 Arrow head indicates sampling point of receiver Bit n in SSITDR TDn 1st channel 2nd channel TD28 TD31 TD31 TD30 TD29 TD28 TD31 TD30 TD29 TD28 SWL 6 bits not attainable in SSI module demonstration only DWL 4 bits not attainable in SSI mod...

Page 1511: ...TD28 TD31 TD31 TD30 TD29 TD28 TD31 TD30 TD29 TD28 As basic sample format configuration except SCKP 1 Figure 34 10 Inverted Clock 2 Inverted Word Select SSI_SCK SSI_WS SSI_SDATA 0 0 0 0 0 0 1st Channel 2nd Channel TD28 TD31 TD31 TD30 TD29 TD28 TD31 TD30 TD29 TD28 As basic sample format configuration except SWSP 1 Figure 34 11 Inverted Word Select 3 Inverted Padding Polarity SSI_SCK SSI_WS SSI_SDATA...

Page 1512: ...dding Bits First Followed by Serial Data without Delay As basic sample format configuration except SDTA 1 and DEL 1 0 0 0 TD28 0 0 TD29 0 TD31 TD30 TD29 TD28 TD31 TD30 TD29 TD28 SSI_SCK SSI_WS SSI_SDATA 1st Channel 2nd Channel Figure 34 14 Padding Bits First Followed by Serial Data without Delay 6 Serial Data First Followed by Padding Bits without Delay As basic sample format configuration except ...

Page 1513: ...ration except PDTA 1 0 0 0 0 0 0 TD3 TD0 TD3 TD2 TD1 TD0 TD3 TD2 TD1 TD0 SSI_SCK SSI_WS SSI_SDATA 1st Channel 2nd Channel Figure 34 16 Parallel Right Aligned with Delay 8 Mute Enabled As basic sample format configuration except MUEN 1 TD data ignored 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSI_SCK SSI_WS SSI_SDATA 1st Channel 2nd Channel Figure 34 17 Mute Enabled ...

Page 1514: ...ree modes of operation configuration enabled and disabled Figure 34 18 shows the transition diagram between these operation modes Module configration after reset Module enabled normal tx rx EN 1 IDST 0 Module disabled waiting until bus inactive EN 0 IDST 0 EN 0 IDST 1 Reset Figure 34 18 Transition Diagram between Operation Modes ...

Page 1515: ...one of two ways either DMA or an interrupt driven DMA driven is preferred to reduce the CPU load In DMA control mode an underflow or overflow of data or DMAC transfer end is notified by using an interrupt The alternative is using the interrupts that the SSI module generates to supply data as required This mode has a higher interrupt load as the SSI module is only double buffered and will require d...

Page 1516: ...EN 1 EN 0 DMEN 0 UIEN 0 OIEN 0 IIEN 1 Release reset specify configuration bits in SSICR Start Setup DMA controller to provide data as required for transmission Enable SSI module enable DMA enable error interrupts Wait for interrupt from DMAC or SSI SSI error interrupt Has DMAC Tx data been completed More data to be send Disable SSI module disable DMA disable error interrupt enable Idle interrupt W...

Page 1517: ...cify configuration bits in SSICR Start Enable SSI module enable DMA enable error interrupts Wait for interrupt from SSI Data interrupt More data to be send Disable SSI module disable DMA disable error interrupt enable Idle interrupt Wait for Idle interrupt from SSI module Reset SSI module if required End Yes No Use SSI status register bits to realign data after underflow overflow Load data of chan...

Page 1518: ...be controlled in one of two ways either DMA or an interrupt driven Figures 34 21 and 34 22 show the flow of operation When disabling the SSI module the SSI clock must be supplied continuously until the module enters in the idle state which is indicated by the IIRQ bit Note SCKD 0 Clock input through the SSI_SCK pin SCKD 1 Clock input through the SSI_CLK pin ...

Page 1519: ...EN 1 EN 0 DMEN 0 UIEN 0 OIEN 0 IIEN 1 Release reset specify configuration bits in SSICR Start Setup DMA controller to provide data as required for transmission Enable SSI module enable DMA enable error interrupts Wait for interrupt from DMAC or SSI SSI error interrupt Has DMAC Tx data been completed More data to be send Disable SSI module disable DMA disable error interrupt enable Idle interrupt W...

Page 1520: ...pecify configuration bits in SSICR Start Enable SSI module enable data interrupt enable error interrupts Wait for interrupt from SSI SSI Error interrupt More data to be received Disable SSI module disable data interrupt disable error IRQ enable idle IRQ Wait for idle interrupt from SSI module Reset SSI module if required End No No Use SSI status register bits to realign data after underflow overfl...

Page 1521: ...il it is ready to store the sample data that the SSI module is indicating that it will receive next to ensure consistency of the number of received data and so resynchronize with the audio data stream 34 4 6 Serial Clock Control This function is used to control and select which clock is used for the serial bus interface If the serial clock direction is set to input SCKD 0 the SSI module is in cloc...

Page 1522: ...rflow error status flag the OIRQ bit in SSISR disable the DMA transfer of the SSI to halt its operation by writing 0 to the EN bit and DMEN bit in SSICR then terminate the DMA setting And clear the overflow status flag by writing 0 to the OIRQ bit set the DMA again and transfer restart 34 5 2 Restrictions for Operation in Slave Mode To terminate data transfer while this LSI is used in slave mode c...

Page 1523: ...operates in Full speed mode Open HCI interfaces and registers are also embedded in this LSI For the development of software refer to the Open HCI specifications as well 35 1 Features Support the Open HCI interface Support the USB host interface Root Hub function although it supports only one port Operate in Full speed mode 12Mbps and low speed mode 1 5 Mbps Support Overcurrent detection and Power ...

Page 1524: ...module Application slave interface I F data 32 HCI I F slave OHCI register HCI I F master Divider data 12MHz Control Control Control List processor XVR USBP USBM USB_PWREN USB_OVRCRT XVR USB transceiver Root hub Host SIE Root hub setting OHCI Root hub register Application master interface FIFO input 4 bytes FIFO output 4 bytes USB_CLK 48MHz 48MHz Control 32 Figure 35 1 Block Diagram of USBH ...

Page 1525: ...e Function I O Function USBP D I O USB port D USBM D I O USB port D USB_PWREN USB port power source enable Output USB port power source enable management USB_OVRCRT USB port overcurrent detection I O USB port overcurrent detection This is used to detect an overcurrent at low level and normal operation at high level USB_CLK Clock pin Input USB clock input pin 48 MHz input Note USB_CLK should be slo...

Page 1526: ... register USBHIE R W H FFEC 8010 H 1FEC 8010 32 HcInterruptDisable register USBHID R W H FFEC 8014 H 1FEC 8014 32 HcHCCA register USBHHCCA R W H FFEC 8018 H 1FEC 8018 32 HcPeriodCurrentED register USBHPCED R W H FFEC 801C H 1FEC 801C 32 HcControlHeadED register USBHCHED R W H FFEC 8020 H 1FEC 8020 32 HcControlCurrentED register USBHCCED R W H FFEC 8024 H 1FEC 8024 32 HcBulkHeadED register USBHBHED...

Page 1527: ...H 00000000 H 00000000 Retained Retained HcInterruptDisable register USBHID H 00000000 H 00000000 Retained Retained HcHCCA register USBHHCCA H 00000000 H 00000000 Retained Retained HcPeriodCurrentED register USBHPCED H 00000000 H 00000000 Retained Retained HcControlHeadED register USBHCHED H 00000000 H 00000000 Retained Retained HcControlCurrentED register USBHCCED H 00000000 H 00000000 Retained Re...

Page 1528: ...r USBHR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 R R R R R R R R REV 7 0 Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7 to 0 REV 7 0 H 10 R Revision Indicate...

Page 1529: ...hould always be 0 10 RWE 0 R W RemoteWakeupConnectedEnable If a remote wakeup signal is supported this bit enables that operation Since remote wakeup signal is not supported this bit is ignored 9 RWC 0 R W RemoteWakeupConnected This bit indicates whether the Host Controller HC supports a remote wakeup signal 8 IR 0 R W InterruptRouting This bit specifies interrupt routing 0 Interrupts routed to no...

Page 1530: ...BHCCED before re enabling the list processing 0 Control list processing is not carried out 1 Control list processing is carried out 3 IE 0 R W IsochronousEnable When clear this bit disables the Isochronous List when the Periodic List is enabled so Interrupt EDs may be serviced While processing the Periodic List the Host Controller will check this bit when it finds an isochronous ED 2 PLE 0 R W Per...

Page 1531: ...C 1 0 All 0 R ScheduleOverrunCount These bits increment every time the SchedulingOverrun bit in HcInterruptStatus is set The count wraps from 11 to 00 15 to 3 All 0 R Reserved These bits are always read as 0 The write value should always be 0 2 BLF 0 R W BulkListFilled When set this bit indicates there is an active ED on the Bulk List The bit can be set by either software or the Host Controller Th...

Page 1532: ...0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R W R W R W R W R W R W R W RHSC FNO UE RD SF WDH SO Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 7 All 0 R Reserved These bits are always read as 0 The write value should always be 0 6 RHSC 0 R W RootHubStatusChange This bit is set when the content of HcRhStatus regi...

Page 1533: ...SF 0 R W StartofFrame This bit is set when the Frame manager signals a Start of Frame s event 1 WDH 0 R W WritebackDoneHead This bit is set after the Host Controller has written the value of HcDoneHead register to HccaDoneHead 0 SO 0 R W SchedulingOverrun This bit is set when the List Processor determines a Schedule Overrun has occurred ...

Page 1534: ...it Bit Name Initial Value R W Description 31 MIE 0 R W MasterInterruptEnable This bit is a global interrupt enable Writing 1 allows interrupts to be enabled via the specific enable bits listed below 30 OC 0 R W OwnershipChangeEnable 0 Ignored 1 Interrupt due to Ownership Change is enabled 29 to 7 All 0 R Reserved These bits are always read as 0 The write value should always be 0 6 RHCS 0 R W RootH...

Page 1535: ...ponding bit while writing 0 to a bit leaves the bit unchanged 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R W R W R W R W R W R W R W MIE OC RHSC FNO UE RD SF WDH SO Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W...

Page 1536: ...to Frame Number Overflow is disabled 4 UE 0 R W UnrecoverableErrorDisable This function is not supported Writing is ignored 3 RD 0 R W ResumeDetectedDisable 0 Ignored 1 Interrupt due to Resume Detected is disabled 2 SF 0 R W StartOfFrameDisable 0 Ignored 1 Interrupt due to Start of Frame is disabled 1 WDH 0 R W WritebackDoneHeadDisable 0 Ignored 1 Interrupt due to Writeback Done Head is disabled 0...

Page 1537: ... 0 R W HCCA Pointer to HCCA base address 7 to 0 All 0 R Reserved These bits are always read as 0 The write value should always be 0 35 3 8 HcPeriodCurrentED Register USBHPCED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R PCED 27 12 ...

Page 1538: ... ControlHeadED Pointer to the Control List Head ED 3 to 0 All 0 R Reserved These bits are always read as 0 The write value should always be 0 35 3 10 HcControlCurrentED Register USBHCCED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 1539: ... 0 R W BulkHeadED Pointer to the Bulk List Head ED 3 to 0 All 0 R Reserved These bits are always read as 0 The write value should always be 0 35 3 12 HcBulkCurrentED Register USBHBCED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 0 0 0 0 0 0 ...

Page 1540: ...5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R DH 27 12 DH 11 0 Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 4 DH All 0 R DoneHead Pointer to the current Done List Head ED 3 to 0 All 0 R Reserved These bits are always read as 0 The write value should always b...

Page 1541: ...13 0 Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 FIT 0 R W FrameIntervalToggle This bit is toggled by Host Control Driver HCD whenever it loads a new value into FrameInterval bit 30 to 16 FSMPS All 0 R W FSLargestDataPacket These bits specify a value which is loaded into the Largest Data Packet Counter at the beginning of each frame 15 14 00 R Reserved...

Page 1542: ...l Value R W Description 31 FRT 0 R FrameRemainingToggle This bit is loaded with FrameIntervalToggle when FrameRemaining is loaded 30 to 14 All 0 R Reserved These bits are always read as 0 The write value should always be 0 13 to 0 FR All0 R FrameRemaining These bits are the 14 bit down counter used to time a frame When the Host Controller is in the USB OPERATIONAL state the counter decrements each...

Page 1543: ... R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R FN 15 0 Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 16 All 0 R Reserved These bits are always read as 0 The write value should always be 0 15 to 0 FN All 0 R W FrameNumber These bits are the 16 bit up counter The count is incremented coincident with the loading of Frame...

Page 1544: ...R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R W R W R W R W R W R W R W R W R W R W R W R W R W R W PS 13 0 Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 14 All 0 R Reserved These bits are always read as 0 The write value should always be 0 13 to 0 PS All 0 R W PeriodicStart These bits set a value used by the List Processor to determin...

Page 1545: ...R R R R R R R R R R R R R R R R 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 R R R R R W R W R W R W R W R W R W R W R W R W R W R W LST 11 0 Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 12 All 0 R Reserved These bits are always read as 0 The write value should always be 0 11 to 0 LST H 628 R W LSThreshold These bits are a value used by the Frame manager to deter...

Page 1546: ...it Bit Name Initial Value R W Description 31 to 24 POTPGT H 02 R W PowerOnToPowerGoodTime USB Host Controller power switching is effective within 2 ms The bit value is represented as the number of 2 ms intervals Only bits 25 and 24 can be written to The remaining bits are read only as 0 It is not expected that these bits be written to anything other than 1h but limited adjustment is allowed These ...

Page 1547: ...ontroller is not a composite device 9 NPS 0 R W NoPowerSwitching USB Host Controller implements global power switching 0 Ports are power switched 1 Ports are always powered on This bit should be written to support the external system port power switching implementation 8 PSM 0 R W PowerSwitchingMode USB Host Controller implements a global power switching mode 0 Global Switching 1 Individual Switch...

Page 1548: ... R W R W R W R W R W R W R W R W R W R W R W R W PPCM 15 0 DR 15 0 Bit Initial value R W Bit Initial value R W Bit Bit Name Initial value R W Description 31 to 16 PPCM All 0 R W PortPowerControlMask USB Host Controller implements global power switching These bits are only valid if NoPowerSwitching is cleared and PowerSwitchingMode bit is set individual port switching When set the port only respond...

Page 1549: ...alue R W Description 15 to 0 DR All 0 R W DeviceRemovableUSB Host Controller ports default to removable devices 0 Device removable 1 Device not removable Port Bit relationship 0 Reserved 1 Port 1 2 Port 2 15 Port 15 Unimplemented ports are reserved These bits are always read as 0 The write value should always be 0 ...

Page 1550: ...e Writing 1 to this bit clears DeviceRemoteWakeupEnable bit Writing 0 has no effect 30 to 18 All 0 R Reserved These bits are always read as 0 The write value should always be 0 17 OCIC 0 R W OverCurrentIndicatorChange This bit is set when OverCurrentIndicator changes Writing 1 clears this bit Writing 0 has no effect 16 LPSC 0 R W read LocalPowerStatusChange Not supported by this LSI The read value...

Page 1551: ...be 0 1 OCI 0 R OverCurrentIndicator This bit reflects the state of the OVRCUR pin This bit is only valid if NoOverCurrentProtection and OverCurrentProtectionMode bits are cleared 0 No over current condition 1 Over current condition 0 LPS 0 R W read LocalPowerStatus Not Supported by this LSI The read value should be 0 write ClearGlobalPower Writing 1 issues a ClearGlobalPower command to the ports W...

Page 1552: ...o 21 All 0 R Reserved These bits are always read as 0 The write value should always be 0 20 PRSC 0 R W PortResetStatusChange This bit indicates that the port reset signal has completed 0 Port reset is not complete 1 Port reset is complete 19 OCIC 0 R W PortOverCurrentIndicatorChange This bit is set when OverCurrentIndicator changes Writing 1 clears this bit Writing 0 has no effect 18 PSSC 0 R W Po...

Page 1553: ...e should always be 0 9 LSDA Undefined R W read LowSpeedDeviceAttached This bit defines the speed and bus idle of the attached device It is only valid when CurrentConnectStatus is set 0 Full Speed device 1 Low Speed device write ClearPortPower Writing 1 clears PortPowerStatus bit Writing 0 has no effect 8 PPS 0 R W read PortPowerStatus This bit reflects the power state of the port regardless of pow...

Page 1554: ...e state of the OVRCUR pin dedicated to this port This bit is only valid if NoOverCurrentProtection bit is cleared and OverCurrentProtectionMode is set 0 No over current condition 1 Over current condition write ClearSuspendStatus Writing 1 initiates the selective resume sequence for the port Writing 0 has no effect 2 PSS 0 R W read PortSuspendStatus 0 Port is not suspended 1 Port is selectively sus...

Page 1555: ...nsceiver 35 3 23 ConfigurationControl Register USBHSC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 R R R R R R R R R R R R R R R R W PS Bit Initial value R W Bit Initial value R W Bit Bit Name Initial value R W Description 31 to 1 All 0 R Reserved These bits are ...

Page 1556: ...ected in USB Function as default value after power on sequence Check the status as follows Set the PortSwitch bit to 1 after matching the polarity between the PULLUPE bit in the USB function module and the PortPowerStatus bit in the USB host module There is no need to match the polarity if the PULLUPE bit is already ON after the USB function module is started ...

Page 1557: ...he ED block the TD block and the Request block The first three blocks operate in a lock step fashion with the List Control block triggering the ED block which in turn triggers the TD block These blocks are responsible for issuing their own bus master requests to the Request block which interfaces to the Host Controller Bus Master 2 Serial Interface Engine SIE The SIE is responsible for managing al...

Page 1558: ...oot Hub is suspended When the HC is in USB RESUME the hub generates the appropriate bus signaling USB RESET resets the Root Hub The following sections describe hub and bus related controls and status Port Control The Port is responsible for all activities associated with driving and monitoring bus states The HCD controls this behavior through the register command interface Clock Generation The USB...

Page 1559: ...accesses In access from the USBH to the external memory controlled by LBSC some access size combinations are not supported by the LBSC Therefore when a local bus area such as SRAM area is specifies as the external memory to be accessed by the USBH the memory access by the USBH may stop To avoid this specify a DDR SDRAM area as the external memory accessed by the USBH 35 6 2 Issuing USB Bus Reset W...

Page 1560: ...Section 35 USB Host Controller USBH Rev 1 00 Oct 01 2007 Page 1494 of 1956 REJ09B0256 0100 ...

Page 1561: ...dpoint the endpoint number used by the USB host and the EP FIFO number that is provided by this USB function controller the transfer method and direction are fixed EP FIFO Number Abbreviation Transfer Type Maximum Packet Size FIFO Buffer Capacity Byte DMA Transfer EP0s Setup 8 8 EP0i Control in 8 8 Endpoint 0 EP0o Control out 8 8 Endpoint 1 EP1 Bulk out 64 128 Possible Endpoint 2 EP2 Bulk in 64 12...

Page 1562: ... REJ09B0256 0100 Figure 36 1 shows the block diagram of USBF Peripheral bus Interrupt requests DMA transfer requests Status and control registers FIFO UDC Transceiver USB function controller USBP USBM Clock 48 MHz UDC USB device controller Legend Figure 36 1 Block Diagram of USBF ...

Page 1563: ...on and Functions Name Pin Name I O Function Overcurrent pin VBUS pin USB_OVRCRT VSBF_VBUS Input USB port over current detection USB cable connection monitor pin Clock pin USB_CLK Input USB clock input pin 48 MHz input Power enable pin USB_PWREN USBF_UPLUP Output USB port power enable control Pull up control output pin P pin USBP I O D M pin USBM I O D Note USB_CLK should be slower than Pck0 ...

Page 1564: ...register 2 IER2 H FFEC 0019 H 1FEC 0019 8 Interrupt enable register 3 IER3 H FFEC 001D H 1FEC 009D 8 Interrupt select register 0 ISR0 H FFEC 0021 H 1FEC 0021 8 Interrupt select register 1 ISR1 H FFEC 0025 H 1FEC 0025 8 Interrupt select register 2 ISR2 H FFEC 0029 H 1FEC 0029 8 Interrupt select register 3 ISR3 H FFEC 002D H 1FEC 002D 8 EP0i data register EPDR0i H FFEC 0031 H 1FEC 0031 8 EP0o data r...

Page 1565: ...iguration value register CVR H FFEC 00B9 H 1FEC 00B9 8 Control register 0 CTLR0 H FFEC 00BD H 1FEC 00BD 8 Time stamp register H TSRH H FFEC 00C1 H 1FEC 00C1 8 Time stamp register L TSRL H FFEC 00C5 H 1FEC 00C5 8 Endpoint information register EPIR H FFEC 00C9 H 1FEC 00C9 8 Interrupt flag register 4 IFR4 H FFEC 00D1 H 1FEC 00D1 8 Interrupt enable register 4 IER4 H FFEC 00D5 H 1FEC 00D5 8 Interrupt s...

Page 1566: ...ter 2 ISR2 H FFEC 0028 H 1FEC 0028 32 Interrupt select register 3 ISR3 H FFEC 002C H 1FEC 002C 32 EP0i data register EPDR0i H FFEC 0030 H 1FEC 0030 32 EP0o data register EPDR0o H FFEC 0034 H 1FEC 0034 32 EP0s data register EPDR0s H FFEC 0038 H 1FEC 0038 32 EP1 data register EPDR1 H FFEC 0040 H 1FEC 0040 32 EP2 data register EPDR2 H FFEC 0050 H 1FEC 0050 32 EP3 data register EPDR3 H FFEC 0060 H 1FE...

Page 1567: ...ister EPIR H FFEC 00C8 H 1FEC 00C8 32 Interrupt flag register 4 IFR4 H FFEC 00D0 H 1FEC 00D0 32 Interrupt enable register 4 IER4 H FFEC 00D4 H 1FEC 00D4 32 Interrupt select register 4 ISR4 H FFEC 00D8 H 1FEC 00D8 32 Control register 1 CTLR1 H FFEC 00DC H 1FEC 00DC 32 Timer register H TMRH H FFEC 00E0 H 1FEC 00E0 32 Timer register L TMRL H FFEC 00E4 H 1FEC 00E4 32 Set time out register H STOH H FFE...

Page 1568: ...egister 3 ISR3 H xxxx xx00 H xxxx xx00 Retained Retained EP0i data register EPDR0i H xxxx xxxx H xxxx xxxx Retained Retained EP0o data register EPDR0o H xxxx xxxx H xxxx xxxx Retained Retained EP0s data register EPDR0s H xxxx xxxx H xxxx xxxx Retained Retained EP1 data register EPDR1 H xxxx xxxx H xxxx xxxx Retained Retained EP2 data register EPDR2 H xxxx xxxx H xxxx xxxx Retained Retained EP3 dat...

Page 1569: ... H xxxx xx00 H xxxx xx00 Retained Retained Endpoint information register EPIR H xxxx xx00 H xxxx xxxx Retained Retained Interrupt flag register 4 IFR4 H xxxx xx00 H xxxx xx00 Retained Retained Interrupt enable register 4 IER4 H xxxx xx00 H xxxx xx00 Retained Retained Interrupt select register 4 ISR4 H xxxx xx00 H xxxx xx00 Retained Retained Control register 1 CTLR1 H xxxx xx00 H xxxx xx02 Retained...

Page 1570: ...e written to the other bits Do not use a bit field declaration of the C language to clear bits EP2 EMPTY and EP1 FULL are status bits that indicate the FIFO states of EP1 and EP2 respectively Therefore EP2 EMPTY and EP1 FULL cannot be cleared Initial value R W EP1 FULL SETUP TS EP0O TS EP0I TR EP0I TS EP2 TR EP2 EMPTY BRST 0 0 0 0 1 0 0 0 R W R W R W R W R R W R R W R R R R R R R R Bit 15 14 13 12...

Page 1571: ...are empty Note EP1 FULL is a status bit and cannot be cleared 5 EP2 TR 0 R W EP2 Bulk in Transfer Request Setting condition When an IN token is received from the host to EP2 and both of FIFO buffers are empty Clearing conditions When reset When 0 is written to by CPU 4 EP2 EMPTY 1 R EP2 Bulk in FIFO Empty Setting conditions When reset The FIFO buffer of EP2 has a dual buffer configuration and this...

Page 1572: ...plete Setting condition When data is normally received from the host to EP0o and an ACK handshake is returned from the function to the host Clearing conditions When reset When 0 is written to by CPU 1 EP0i TR 0 R W EP0i Transfer Request Setting condition When IN token is issued from the host to EP0i and the FIFO buffer is empty Clearing conditions When reset When 0 is written to by CPU 0 EP0i TS 0...

Page 1573: ...ces to be cleared and that 1 should be written to the other bits Do not use a bit field declaration of the C language to clear bits R W R W R W R R R R R R R R R R R R R R R R R R R R R R R R R R R R R Initial value R W EP3 TS VBUSF EP3 TR VBUS MN 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 8 10 9 7 6 5 4 3 0 2 1 Initial value R W Bit 31 30 29 28 27 24 26 25 23 22 21 20 19 16 18 17 Bit Bit Name Initial Val...

Page 1574: ...3 TS 0 R W EP3 Interrupt Transmit Complete Setting condition When data to be transmitted to the host is written to EP3 then data is normally transferred from the host to the function and an ACK handshake is returned Clearing conditions When reset When 0 is written to by CPU 0 VBUSF 0 R W USB Disconnection Detection The USBF_VBUS pin of this module is used for detecting connection disconnection Set...

Page 1575: ...he bits for the interrupt sources to be cleared and that 1 should be written to the other bits Do not use a bit field declaration of the C language to clear bits R W R W R W R W R W R R R R R R R R R R R R R R R R R R R R R R R R R R R Initial value R W SETC SETI SOF CFDN SURSF SURSS 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 8 10 9 7 6 5 4 3 0 2 1 Initial value R W Bit 31 30 29 28 27 24 26 25 23 22 21 20...

Page 1576: ... Complete Setting condition When the end point information written in EPIR is completed to be set loaded in this controller Note This controller operates normally as USB after the setting of the end point information is completed Clearing conditions When reset When 0 is written to by CPU 2 SOF 0 R W SOF Packet Setting condition When the valid SOF packet is detected Clearing conditions When reset W...

Page 1577: ...learing the flag is performed by writing 0 Writing 1 is not valid and nothing is changed To clear bits access the register so that 0 should be written only to the bits for the interrupt sources to be cleared and that 1 should be written to the other bits Do not use a bit field declaration of the C language to clear bits R W R W R W R W R R R R R R R R R R R R R R R R R R R R R R R R R R R R Initia...

Page 1578: ...evious frame Setting condition The FIFO buffer to be transmitted is empty when an IN token is issued from the host to EP5 Clearing conditions When reset When 0 is written to by CPU 2 EP5 TS 0 R W EP5 Isochronous in Normal Transmission Flag indicating the FIFO state of EP5 After the SOF packet is received the FIFO buffer is switched automatically The FIFO buffer which has transmitted data to the ho...

Page 1579: ...OF packet is received Setting condition When the transfer data from the host is abnormally received packet error by EP4 Clearing conditions When reset When 0 is written to by CPU 0 EP4 TS 0 R W EP4 Isochronous out Normal Reception Flag indicating the FIFO state of EP4 Indicates the state of the FIFO buffer that was readable after the data reception is completed and the next SOF packet is received ...

Page 1580: ...cleared and that 1 should be written to the other bits Do not use a bit field declaration of the C language to clear bits Initial value R W TMOUT 0 0 0 0 0 0 0 0 R W R R R R R R R R R R R R R R R Bit 15 14 13 12 11 8 10 9 7 6 5 4 3 0 2 1 Initial value R W R R R R R R R R R R R R R R R R Bit 31 30 29 28 27 24 26 25 23 22 21 20 19 16 18 17 Bit Bit Name Initial Value R W Description 31 to 8 Undefined...

Page 1581: ...R R R R R R R R R R Initial value R W EP0i TR IS EP0i TS IS EP0o TR IS SETUP TS IS EP2 EMPTY IS EP2 TR IS EP1 FULL IS BRST IS 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 8 10 9 7 6 5 4 3 0 2 1 Initial value R W Bit 31 30 29 28 27 24 26 25 23 22 21 20 19 16 18 17 Bit Bit Name Initial Value R W Description 31 to 8 Undefined R Reserved These bits are always read as undefined value Write value should always be...

Page 1582: ...of interrupt source of the IFR1 is USBFI1 R W R W R W R R R R R R R R R R R R R R R R R R R R R R R R R R R R R Initial value R W EP3 TS IS VBUSF IS EP3 TR IS 1 1 1 0 0 0 0 0 Bit 15 14 13 12 11 8 10 9 7 6 5 4 3 0 2 1 Initial value R W Bit 31 30 29 28 27 24 26 25 23 22 21 20 19 16 18 17 Bit Bit Name Initial Value R W Description 31 to 8 Undefined R Reserved These bits are always read as undefined v...

Page 1583: ... R W R W R W R W R R R R R R R R R R R R R R R R R R R R R R R R R R R Initial value R W SETC IS SETIE IS SOFE IS CFDN IS SURSE IS 1 1 1 1 1 0 0 0 Bit 15 14 13 12 11 8 10 9 7 6 5 4 3 0 2 1 Initial value R W Bit 31 30 29 28 27 24 26 25 23 22 21 20 19 16 18 17 Bit Bit Name Initial Value R W Description 31 to 8 Undefined R Reserved These bits are always read as undefined value Write value should alwa...

Page 1584: ...R3 is USBFI1 R W R W R W R W R R R R R R R R R R R R R R R R R R R R R R R R R R R R Initial value R W EP4 TF IS EP4 TS IS EP5 TS IS EP5 TR IS 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 8 10 9 7 6 5 4 3 0 2 1 Initial value R W Bit 31 30 29 28 27 24 26 25 23 22 21 20 19 16 18 17 Bit Bit Name Initial Value R W Description 31 to 8 Undefined R Reserved These bits are always read as undefined value Write value...

Page 1585: ...t request is issued to INTC In the initial value each of interrupt source of the IFR4 is USBFI1 R W R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R Initial value R W TMOUT IS 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 8 10 9 7 6 5 4 3 0 2 1 Initial value R W Bit 31 30 29 28 27 24 26 25 23 22 21 20 19 16 18 17 Bit Bit Name Initial Value R W Description 31 to 8 Undefined R Reserved These bits ...

Page 1586: ...0o TS IE SETUP TS IE EP2 EMPTY IE EP2 TR IE EP1 FULL IE BRST IE 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 8 10 9 7 6 5 4 3 0 2 1 Initial value R W Bit 31 30 29 28 27 24 26 25 23 22 21 20 19 16 18 17 Bit Bit Name Initial Value R W Description 31 to 8 Undefined R Reserved These bits are always read as undefined value Write value should always be 0 7 BRST IE 0 R W BRST Interrupt Enable 6 EP1 FULL IE 0 R W E...

Page 1587: ...R R R W R W R R R R R R R R R R R R R Initial value R W EP3 TS IE VBUSF IE EP3 TR IE 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 8 10 9 7 6 5 4 3 0 2 1 Initial value R W Bit 31 30 29 28 27 24 26 25 23 22 21 20 19 16 18 17 Bit Bit Name Initial Value R W Description 31 to 8 Undefined R Reserved These bits are always read as undefined value Write value should always be 0 7 to 3 All 0 R Reserved These bits are...

Page 1588: ...tial value R W SETCE IE SETIE IE SOFE IE CFDN IE SURSE IE 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 8 10 9 7 6 5 4 3 0 2 1 Initial value R W Bit 31 30 29 28 27 24 26 25 23 22 21 20 19 16 18 17 Bit Bit Name Initial Value R W Description 31 to 8 Undefined R Reserved These bits are always read as undefined value Write value should always be 0 7 to 5 All 0 R Reserved These bits are always read as 0 The write...

Page 1589: ... R R R R R Initial value R W EP4 TE IE EP4 TS IE EP5 TS IE EP5 TR IE 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 8 10 9 7 6 5 4 3 0 2 1 Initial value R W Bit 31 30 29 28 27 24 26 25 23 22 21 20 19 16 18 17 Bit Bit Name Initial Value R W Description 31 to 8 Undefined R Reserved These bits are always read as undefined value Write value should always be 0 7 to 4 All 0 R Reserved These bits are always read as ...

Page 1590: ...in the ISR4 is issued R W R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R Initial value R W TMOUT IE 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 8 10 9 7 6 5 4 3 0 2 1 Initial value R W Bit 31 30 29 28 27 24 26 25 23 22 21 20 19 16 18 17 Bit Bit Name Initial Value R W Description 31 to 8 Undefined R Reserved These bits are always read as undefined value Write value should always be 0 7 to 1 A...

Page 1591: ... the host after the data has been transmitted EP0iTS in interrupt flag register 0 is set This FIFO buffer can be initialized by means of EP0iCLR in the FCLR0 register R R R R R R R R R R R R R R R R R R R R R R R R W W W W W W W W Initial value R W D 7 0 Bit 15 14 13 12 11 8 10 9 7 6 5 4 3 0 2 1 Initial value R W Bit 31 30 29 28 27 24 26 25 23 22 21 20 19 16 18 17 Bit Bit Name Initial Value R W De...

Page 1592: ...data size register After the data has been read setting EP0oRDFN in the trigger register enables the next packet to be received This FIFO buffer can be initialized by means of BP0oCLR in the FCLR0 register R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R Initial value R W D 7 0 Bit 15 14 13 12 11 8 10 9 7 6 5 4 3 0 2 1 Initial value R W Bit 31 30 29 28 27 24 26 25 23 22 21 20 19 16 ...

Page 1593: ...the reception of data in the setup stage starts during read reception has priority and read data is invalid R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R Initial value R W D 7 0 Bit 15 14 13 12 11 8 10 9 7 6 5 4 3 0 2 1 Initial value R W Bit 31 30 29 28 27 24 26 25 23 22 21 20 19 16 18 17 Bit Bit Name Initial Value R W Description 31 to 8 Undefined R Reserved These bits are alway...

Page 1594: ...again by writing EP1RDFN in the trigger register to 1 after data is read The receive data of this FIFO buffer can be transferred by DMA This FIFO buffer can be initialized by means of EP1CLR in the FCLR0 register R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R Initial value R W D 7 0 Bit 15 14 13 12 11 8 10 9 7 6 5 4 3 0 2 1 Initial value R W Bit 31 30 29 28 27 24 26 25 23 22 21 20...

Page 1595: ... fixed and the dual FIFO buffer is switched over Transmit data for this FIFO buffer can be transferred by DMA This FIFO buffer can be initialized by means of EP2CLR in the FCLR0 register R R R R R R R R R R R R R R R R W W W W W W W W R R R R R R R R Initial value R W D 7 0 Bit 15 14 13 12 11 8 10 9 7 6 5 4 3 0 2 1 Initial value R W Bit 31 30 29 28 27 24 26 25 23 22 21 20 19 16 18 17 Bit Bit Name ...

Page 1596: ...eturned from the host after the data has been transmitted EP3TS in interrupt flag register 1 is set This FIFO buffer can be initialized by means of EP3CLR in the FCLR0 register R R R R R R R R R R R R R R R R W W W W W W W W R R R R R R R R Initial value R W D 7 0 Bit 15 14 13 12 11 8 10 9 7 6 5 4 3 0 2 1 Initial value R W Bit 31 30 29 28 27 24 26 25 23 22 21 20 19 16 18 17 Bit Bit Name Initial Va...

Page 1597: ...t be read until the next SOF packet is received When the next SOF packet is received the FIFO side is automatically switched over and the previous data will not be possible to be read This FIFO buffer can be initialized by means of EP4CLR in the FCLR1 register R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R Initial value R W D 7 0 Bit 15 14 13 12 11 8 10 9 7 6 5 4 3 0 2 1 Initial v...

Page 1598: ...er is switched over This FIFO buffer can be initialized by means of EP5CLR and EP5CCLR in the FCLR1 register EP5CLR initializes both FIFOs and EP5CCLR initializes one FIFO which is connected to the CPU R R R R R R R R R R R R R R R R R R R R R R R R W W W W W W W W Initial value R W D 7 0 Bit 15 14 13 12 11 8 10 9 7 6 5 4 3 0 2 1 Initial value R W Bit 31 30 29 28 27 24 26 25 23 22 21 20 19 16 18 1...

Page 1599: ... received from the host R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R Initial value R W 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 8 10 9 7 6 5 4 3 0 2 1 Initial value R W Bit 31 30 29 28 27 24 26 25 23 22 21 20 19 16 18 17 Bit Bit Name Initial Value R W Description 31 to 8 Undefined R Reserved These bits are always read as undefined value Write value should always be 0 7 to 0 All 0 R Nu...

Page 1600: ...n The size of the received data indicated by this register is the size of the currently selected side can be read by CPU R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R Initial value R W 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 8 10 9 7 6 5 4 3 0 2 1 Initial value R W Bit 31 30 29 28 27 24 26 25 23 22 21 20 19 16 18 17 Bit Bit Name Initial Value R W Description 31 to 8 Undefined R Reserv...

Page 1601: ...e received data indicated by this register is the size of the currently selected side can be read by CPU R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R Initial value R W 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 8 10 9 7 6 5 4 3 0 2 1 Initial value R W Bit 31 30 29 28 27 24 26 25 23 22 21 20 19 16 18 17 Bit Bit Name Initial Value R W Description 31 to 8 Undefined R Reserved These bits ar...

Page 1602: ...0 0 0 0 0 Bit 15 14 13 12 11 8 10 9 7 6 5 4 3 0 2 1 EP0i PKTE EP0o RDFN EP0s RDFN EP2 PKTE EP1 RDFN EP3 PKTE Initial value R W Bit 31 30 29 28 27 24 26 25 23 22 21 20 19 16 18 17 Bit Bit Name Initial Value R W Description 31 to 8 Undefined R Reserved These bits are always read as undefined value Write value should always be 0 7 0 W Reserved The write value should always be 0 6 EP3 PKTE 0 W EP3 Pac...

Page 1603: ...this bit is cleared to 0 when both sides are empty R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R Initial value R W 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 8 10 9 7 6 5 4 3 0 2 1 EP0i DE EP2 DE EP3 DE Initial value R W Bit 31 30 29 28 27 24 26 25 23 22 21 20 19 16 18 17 Bit Bit Name Initial Value R W Description 31 to 8 Undefined R Reserved These bits are always read as undefined value...

Page 1604: ...e corresponding interrupt flag is not cleared by this clear instruction Do not clear a FIFO buffer during transmission and reception W W W W W W W W R R R R R R R R Initial value R W EP0o CLR EP0i CLR EP2 CLR EP1 CLR EP3 CLR Bit 15 14 13 12 11 8 10 9 7 6 5 4 3 0 2 1 Initial value R W Bit 31 30 29 28 27 24 26 25 23 22 21 20 19 16 18 17 R R R R R R R R R R R R R R R R Bit Bit Name Initial Value R W ...

Page 1605: ...reception W W W W W W W W R R R R R R R R Initial value R W EP5 CLR EP4 CLR EP5 CCLR Bit 15 14 13 12 11 8 10 9 7 6 5 4 3 0 2 1 Initial value R W Bit 31 30 29 28 27 24 26 25 23 22 21 20 19 16 18 17 R R R R R R R R R R R R R R R R Bit Bit Name Initial Value R W Description 31 to 8 Undefined R Reserved These bits are always read as undefined value Write value should always be 0 7 to 5 Undefined W Res...

Page 1606: ... 12 11 8 10 9 7 6 5 4 3 0 2 1 Initial value R W Bit 31 30 29 28 27 24 26 25 23 22 21 20 19 16 18 17 R R R R R R R R R R R R R R R R Bit Bit Name Initial Value R W Description 31 to 8 Undefined R Reserved These bits are always read as undefined value Write value should always be 0 7 to 3 All 0 R Reserved These bits are always read as 0 The write value should always be 0 2 PULLUP E 0 R W Pull up Ena...

Page 1607: ... EP0 STL bit to 1 is ignored For detailed operation see section 36 8 Stall Operations R W R W R W R W R R R R R R R R R R R R Initial value R W EP1 STL EP0 STL EP2 STL EP3 STL 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 8 10 9 7 6 5 4 3 0 2 1 Initial value R W Bit 31 30 29 28 27 24 26 25 23 22 21 20 19 16 18 17 R R R R R R R R R R R R R R R R Bit Bit Name Initial Value R W Description 31 to 8 Undefined R R...

Page 1608: ...s Initial value R W EP5 STL EP4 STL 0 0 0 0 0 0 0 0 R W R W R R R R R R R R R R R R R R Bit 15 14 13 12 11 8 10 9 7 6 5 4 3 0 2 1 Initial value R W R R R R R R R R R R R R R R R R Bit 31 30 29 28 27 24 26 25 23 22 21 20 19 16 18 17 Bit Bit Name Initial Value R W Description 31 to 8 Undefined R Reserved These bits are always read as undefined value Write value should always be 0 7 to 2 All 0 R Rese...

Page 1609: ... W Description 31 to 8 Undefined R Reserved These bits are always read as undefined value 7 6 CNFV 1 0 00 R Configuration Value The configuration setting value is stored when the Set Configuration command has been received CNFV is updated when the SETC bit in the interrupt flag register is set to 1 5 4 INTV 1 0 00 R Interface Value The interface setting value is stored when the Set Interface comma...

Page 1610: ... TSR 7 0 bits in TSRL Although TSRH can be read directly TSRL is read via an 8 bit temporary register Therefore the registers should be accessed in the order of TSRH and TSRL in byte units TSRL cannot be read singly TSRH Initial value R W TSR 10 8 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Bit 15 14 13 12 11 8 10 9 7 6 5 4 3 0 2 1 Initial value R W R R R R R R R R R R R R R R R R Bit 31 30 29...

Page 1611: ...R R R R R R R R R R R R R R Bit 15 14 13 12 11 8 10 9 7 6 5 4 3 0 2 1 Initial value R W R R R R R R R R R R R R R R R R Bit 31 30 29 28 27 24 26 25 23 22 21 20 19 16 18 17 Bit Bit name Initial value R W Description 31 to 8 Undefined R Reserved These bits are always read as undefined value 7 to 0 TSR 7 0 All 0 R Lower Eight Bits of Time Stamp Data ...

Page 1612: ...ed value Write value should always be 0 7 to 5 All 0 R Reserved These bits are always read as 0 The write value should always be 0 4 RWUPS 0 R Remote Wakeup Status Status bit to indicate that the remote wakeup from the host is enabled disabled Indicates 0 when the remote wakeup is disabled with Device Remote Wakeup by the Set Feature Clear Feature request and indicates 1 when it is enabled 3 RSME ...

Page 1613: ...ed to the host and the stall setting bit EPSTLR EPXSTL of the returned endpoint is automatically cleared Control in a unit of endpoint is disabled as this bit is common for all endpoints When this bit is set to 0 be sure to clear the stall setting bit of each endpoint by using software This bit should be set to 1 before each stall bit in EPSTL is set to 1 0 0 R Reserved This bit is always read as ...

Page 1614: ...30 29 28 27 24 26 25 23 22 21 20 19 16 18 17 Bit Bit name Initial value R W Description 31 to 8 Undefined R Reserved These bits are always read as undefined value Write value should always be 0 7 to 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 TMRACLR 1 R W Timer Auto Clear Selects method to clear TMR timer register 0 Not cleared When clearing TMR write 0...

Page 1615: ...nly one EPIR register write data for registration number N N is from 0 to 9 is listed as EPIRN0 to EPIRN4 EPIR registration number write order for the purpose of explaining Write data in order from EPIR00 EPIRN0 Initial value R W D 1 0 D 3 2 D 7 4 W W W W W W W W R R R R R R R R Bit 15 14 13 12 11 8 10 9 7 6 5 4 3 0 2 1 Initial value R W R R R R R R R R R R R R R R R R Bit 31 30 29 28 27 24 26 25 ...

Page 1616: ... 20 19 16 18 17 Bit Bit Name Initial value R W Description 31 to 8 Undefined R Reserved These bits are always read as undefined value Write value should always be 0 7 6 D 7 6 Undefined W Alternate Number to which Endpoint Belongs Settable range 0 or 1 5 4 D 5 4 Undefined W Transfer Method of Endpoint Settable range 0 Control 1 Isochronous 2 Bulk 3 Interrupt 3 D3 Undefined W Transfer Direction of E...

Page 1617: ...defined value Write value should always be 0 7 to 1 D 7 1 Undefined W Maximum Packet Size of Endpoint Settable range 0 to 64 0 D0 Undefined W Reserved The write value should always be 0 EPIRN3 Initial value R W D 7 0 W W W W W W W W R R R R R R R R Bit 15 14 13 12 11 8 10 9 7 6 5 4 3 0 2 1 Initial value R W R R R R R R R R R R R R R R R R Bit 31 30 29 28 27 24 26 25 23 22 21 20 19 16 18 17 Bit Bit...

Page 1618: ...g values are limited as described below Since each endpoint FIFO is optimized by a dedicated hardware corresponding to each transfer method transfer direction and maximum packet size set the endpoint FIFO with a transfer method transfer direction and maximum packet size shown in the table below Example Endpoint FIFO number 1 cannot be set as other than bulk transfer OUT and maximum packet size 64 ...

Page 1619: ... 4 Restrictions of Settable Values Endpoint FIFO No Maximum Packet Size Transfer Method Transfer Direction 0 8 bytes Control 1 64 bytes Bulk OUT 2 64 bytes Bulk IN 3 8 bytes Interrupt IN 4 0 to 64 bytes Isochronous OUT 5 0 to 64 bytes Isochronous IN Example of Setting This is an example when endpoint 4 and 5 used for the isochronous transfer are allocated with Alternate value Table 36 5 Example of...

Page 1620: ...EPIR N 2 EPIR N 3 EPIR N 4 0 00 00 10 00 00 1 14 20 80 00 01 2 24 28 80 00 02 3 34 38 10 00 03 4 00 00 00 00 00 5 00 00 00 00 00 6 46 10 00 00 04 7 46 50 80 00 04 8 67 18 00 00 05 9 57 58 80 00 05 Config 1 Int 0 1 2 3 Alt 0 0 1 0 1 0 1 EP No 0 1 2 3 4 4 5 5 EP FIFO No 0 1 2 3 4 5 Attribute Control BulkOut BulkIn InterruptIn IsoOut IsoIn Figure 36 2 Example of Endpoint Configuration ...

Page 1621: ...and TMR 7 0 bits in TMRL Although TMRH can be read directly TMRL is read via an 8 bit temporary register Therefore the registers should be read in the order of TMRH and TMRL in byte units TMRL cannot be read singly TMRH R R R R R R R R R R R R R R R R R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Initial value R W TMR 15 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 8 10 9...

Page 1622: ... W R W R W Initial value R W TMR 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 8 10 9 7 6 5 4 3 0 2 1 Initial value R W Bit 31 30 29 28 27 24 26 25 23 22 21 20 19 16 18 17 Bit Bit Name Initial value R W Description 31 to 8 Undefined R Reserved These bits are always read as undefined value The write value should always be 0 7 to 0 TMR 7 0 0 R W Lower Eight Bits of Count Value ...

Page 1623: ...ough STOH can be read directly STOL is read via an 8 bit temporary register Therefore the registers should be read in the order of STOH and STOL in byte units STOL cannot be read singly STOH R R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Initial value R W STO 15 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 8 10 9 7 6 5 4 3 0 2 1 Initial value R W R R R R R R R R R R R R ...

Page 1624: ...W STO 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 8 10 9 7 6 5 4 3 0 2 1 Initial value R W R R R R R R R R R R R R R R R Bit 31 30 29 28 27 24 26 25 23 22 21 20 19 16 18 17 Bit Bit Name Initial Value R W Description 31 to 8 Undefined R Reserved The read value is undefined The write value should always be 0 7 to 0 STO 7 0 0 R W Lower Eight Bits of Specified Time Out Value ...

Page 1625: ...BRST 1 Bus reset interrupt Wait for setup command reception complete interrupt IFR0 CFDN 1 Endpoint information load complete interrupt USB module interrupt setting As soon as preparations are completed enable D pull up by USBF_UPLUP Clear VBUS flag IFR0 VBUSF Firmware preparations for start of USB communication Clear bus reset flag IFR0 BRST Clear FIFOs Wait for setup command reception complete i...

Page 1626: ...ire connection detection regardless of D pull up control detection should be carried out using IRQ or a general input port 36 4 2 Cable Disconnection USB function Cable connected USBF_VBUS pin 1 USB cable disconnection USBF_VBUS pin 0 UDC core reset End Application IFR0 VBUSF 1 VBUSMN 0 USB connection or disconnection detection interrupt Figure 36 4 Cable Disconnection Operation In applications th...

Page 1627: ...ne data stage direction 1 Write 1 to EP0s read complete bit TRG EP0s RDFN 1 To control in data stage To control out data stage Command to be processed by application Interrupt request Yes No Notes 1 In the setup stage the application analyzes command data from the host requiring processing by the application and determines the subsequent processing for example data stage direction etc 2 When the t...

Page 1628: ... host in the setup stage and determines the subsequent data stage direction If the result of command data analysis is that the data stage is in transfer one packet of data to be sent to the host is written to the FIFO If there is more data to be sent this data is written to the FIFO after the data written first has been sent to the host IFR0 EP0i TS 1 The end of the data stage is identified when t...

Page 1629: ... RDFN 1 written to TRG EP0o RDFN NAK NAK ACK No Yes No Yes Interrupt request Figure 36 7 Data Stage Control Out Operation The application first analyzes command data from the host in the setup stage and determines the subsequent data stage direction If the result of command data analysis is that the data stage is out transfer the application waits for data from the host and after data is received ...

Page 1630: ...control transfer Set EP0o reception complete flag IFR0 EP0o TS 1 Clear EP0o reception complete flag IFR0 EP0o TS 0 Write 1 to EP0o read complete bit TRG EP0o RDFN 1 End of control transfer ACK Interrupt request Figure 36 8 Status Stage Control In Operation The control in status stage starts with an OUT token from the host The application receives 0 byte data from the host and ends control transfer...

Page 1631: ...Figure 36 9 Status Stage Control Out Operation The control out status stage starts with an IN token from the host When an IN token is received at the start of the status stage there is not yet any data in the EP0i FIFO and so an EP0i transfer request interrupt is generated The application recognizes from this interrupt that the status stage has started Next in order to transmit 0 byte data to the ...

Page 1632: ...request Figure 36 10 EP1 Bulk Out Transfer Operation EP1 has two 64 byte FIFOs but the user can perform data reception and receive data reads without being aware of this dual FIFO configuration When one FIFO is full after reception is completed the IFR0 EP1 FULL bit is set After the first receive operation into one of the FIFOs when both FIFOs are empty the other FIFO is empty and so the next pack...

Page 1633: ...nterrupt request Figure 36 11 EP2 Bulk In Transfer Operation EP2 has two 64 byte FIFOs but the user can perform data transmission and transmit data writes without being aware of this dual FIFO configuration However one data write is performed for one FIFO For example even if both FIFOs are empty it is not possible to perform EP2 PKTE at one time after consecutively writing 128 bytes of data EP2 PK...

Page 1634: ...ta can be written to the other FIFO immediately When both FIFOs are full EP2 EMPTY is cleared to 0 If at least one FIFO is empty IFR0 EP2 EMPTY is set to 1 When ACK is returned from the host after data transmission is completed the FIFO used in the data transmission becomes empty If the other FIFO contains valid transmit data at this time transmission can be continued When transmission of all data...

Page 1635: ... 0 Write data to EP3 data register EPDR3 Write 1 to EP3 packet enable bit TRG EP3 PKTE 1 Valid data in EP3 FIFO Is there data for transmission to host Is there data for transmission to host No Yes No Yes No Yes NAK ACK Note This flowchart shows just one example of interrupt transfer processing Other possibilities include an operation flow in which if there is data to be transferred the EP3 DE bit ...

Page 1636: ...H TSRL A Read EP4 receive data size register EPSZ4 Read EP4 flag IFR3 EP4 TS EP4 TF Read data from EP4 data register EPDR4 Read EP4 receive data size register EPSZ4 Read EP4 flag IFR3 EP4 TS EP4 TF Read data from EP4 data register EPDR4 INTN SOF INTN SOF USB function Firmware To figure 36 14 To figure 36 14 SOF reception FIFO buffer switch over Out token reception No errorin receive data Data rece...

Page 1637: ...witch over No Out token reception No error in receive data Data reception from host Set EP4 abnormal reception flag to 1 IFR3 EP4 TF 1 Set EP4 normal reception flag to 1 IFR3 EP4 TS 1 Clear time out flag IFR4 TMOUT 0 Interrupt end Interrupt end Read time stamp register H L TSRH TSRL Clear SOF packet detection flag IFR2 SOF 0 INTN Time out INTN SOF USB function Firmware Time stamps do not match A F...

Page 1638: ...error in the data set the internal TS flag to 1 In firmware first the processing routine of the isochronous transfer is called by SOF interrupt to check the time stamp Then data is read from the FIFO buffer The flag information TS TF is read and decided if the data has an error The flag information at this time represents the status of the currently readable FIFO buffer SOF happens to be broken be...

Page 1639: ...nction Firmware Valid data in EP5 FIFO Data in FIFO B side has been transmitted No Data in FIFO A side has been transmitted Yes No FIFO B side 0 byte data transmission Read time stamp register H L TSRH TSRL No Time stamps match Yes No To figure 36 16 To figure 36 16 Clear SOF packet detection flag IFR2 SOF 0 Read time stamp register H L TSRH TSRL Time stamps match Set EP5 transmit flag IFR3 EP5 TR...

Page 1640: ...NTN Time out INTN FIFO USB function Firmware No valid data in EP5 FIFO 0 byte data transmission to host FIFO B side 0 byte data transmission Read time stamp register H L TSRH TSRL Time stamps do not match Write one packet of data to EP5 data register EPDR5 From figure 36 15 B In token reception Set EP5 transmit request flag IFR3 EP5 TR 1 No valid data in EP5 FIFO 0 byte data transmission to host 0...

Page 1641: ...transfer is called by SOF interrupt to check the time stamp Then one packet data is written to FIFO This written data is transmitted to the host in the next frame SOF happens to be broken because of external cause during transmission from the host In this case an operation flow is different from that in figure 36 15 As an example figure 36 16 shows the operation flow of a broken frame and a subseq...

Page 1642: ...ion Get interface Get status Set address Set configuration Set feature Set interface Get descriptor Class Vendor command Synch frame Set descriptor If decoding is not necessary on the application side command decoding and data stage and status stage processing are performed automatically No processing is necessary by the user An interrupt is not generated in this case If decoding is necessary on t...

Page 1643: ...nt from the host for the endpoint for which the EPSTL bit was set the USB function controller references the internal status bit and if this is not set references the corresponding bit in EPSTL 1 2 in figure 36 17 If the corresponding bit in USBEPSTL is set the USB function controller sets the internal status bit and returns a stall handshake to the host 1 3 in figure 36 17 In this time if the CTL...

Page 1644: ...STL not changed 1 EPnSTL cleared to 0 by application 2 IN OUT token received from host 3 Internal status bit already set to 1 4 EPnSTL not referenced 5 Internal status bit not changed To 1 2 Internal status bit 0 EPnSTL 0 1 Internal status bit 0 EPnSTL 1 Internal status bit 0 1 EPnSTL 1 Internal status bit 1 EPnSTL 1 0 Internal status bit 1 EPnSTL 0 Internal status bit 1 0 EPnSTL 0 Internal status...

Page 1645: ...ains set until cleared by a Clear Feature command from the host without regard to the corresponding bit in EPSTL After a bit is cleared by the Clear Feature command the corresponding bit in EPSTL is referenced 3 1 in figure 36 18 The USB function controller continues to return a stall handshake while the internal status bit is set since the internal status bit is set even if a transaction is execu...

Page 1646: ...e of USB specification violation etc USB function module stalls endpoint automatically 1 Transmission of STALL handshake 1 Internal status bit cleared to 0 2 EPnSTL not changed 1 EPnSTL cleared to 0 by application 2 IN OUT token received from host 3 Internal status bit already set to 1 4 EPnSTL not referenced 5 Internal status bit not changed Normal status restored Internal status bit 0 1 EPnSTL 0...

Page 1647: ...REN pin According to the status of the USBF_VBUS pin the USB function controller recognizes whether the cable is connected disconnected Also pin D must be pulled up in order to notify the USB host hub that the connection is established The sample circuit in figure 36 19 uses the USBF_UPLUP pin for pull up control This LSI USB function USB connector IC allowing voltage application when system power...

Page 1648: ...e host or transmitting to the host must not be cleared 36 10 3 Overreading Overwriting of Data Register The following points should be noted when the data register of the USBF is read from or written to Receive Data Register The receive data register must not read data which is more than valid receive data bytes That is data which is more than bytes indicated in the receive data size register must...

Page 1649: ...TR Interrupt The bulk in transfer has a transfer request interrupt TR interrupt The following points should be noted when using a TR interrupt When the IN token is sent from the USB host and there is no data in the corresponding EP FIFO the TR interrupt flag is set However the TR interrupt is generated continuously at the timing as shown in figure 36 20 In this case note that erroneous operation s...

Page 1650: ...0 CPU TR flag clearing IN token IN token IN token NAK determination NAK determination TR flag setting TR flag setting TR flag is set again NAK NAK ACK Data transmission Transmit data writing TRG PKTE Host USB TR interrupt routine TR interrupt routine Figure 36 20 Set Timing of TR Interrupt Flag ...

Page 1651: ...color modes Supports 1 2 4 6 bpp grayscale modes Supports LCD panel sizes from 16 1 to 1024 1024 2 24 bit color palette memory 16 of the 24 bits are valid R 5 G 6 B 5 STN DSTN panels are prone to flicker and shadowing The controller applies 65536 color control by 24 bit space modulation FRC with 8 bit RGB values for reduced flicker Dedicated display memory is unnecessary using part of the DDR_SDRA...

Page 1652: ...h can be Displayed in this LCDC Figure 37 1 shows a block diagram of LCDC Clock generator LCDC LCD_CLK Bck Pck0 DDRIF DDR I O LCD_CL1 LCD_CL2 LCD_FLM LCD_D15 to 0 LCD_DON LCD_VCPWC LCD_VEPWC LCD_M_DISP DOTCLK LCDM_CL1 LCDM_CL2 LCDM_FLM LCDM_D15 to 0 LCDM_DON LCDM_VCPWC LCDM_VEPWC LCDM_M_DISP DDR SDRAM VRAM Normal output pin group Mirror output output group Power control Line buffer Register Periph...

Page 1653: ..._D15 to 0 LCDM_D15 to 0 Output Data for LCD panel LCD_DON LCDM_DON Output Display on signal DON LCD_CL1 LCDM_CL1 Output Shift clock 1 STN DSTN horizontal sync signal HSYNC TFT LCD_CL2 LCDM_CL2 Output Shift clock 2 STN DSTN dot clock DOTCLK TFT LCD_M_DISP LCDM_M_DISP Output LCD current alternating signal DISP signal LCD_FLM LCDM_FLM Output First line marker vertical sync signal VSYNC TFT LCD_VCPWC ...

Page 1654: ...E8 040C 32 LCDC fetch data line address offset register for display panel LDLAOR R W H FFE8 0410 H 1FE8 0410 16 LCDC palette control register LDPALCR R W H FFE8 0412 H 1FE8 0412 16 LCDC horizontal character number register LDHCNR R W H FFE8 0414 H 1FE8 0414 16 LCDC horizontal synchronization signal register LDHSYNR R W H FFE8 0416 H 1FE8 0416 16 LCDC vertical displayed line number register LDVDLNR...

Page 1655: ...d Retained Retained LCDC input clock register LDICKR H 1101 H 1101 Retained Retained LCDC module type register LDMTR H 0109 H 0109 Retained Retained LCDC data format register LDDFR H 000C H 000C Retained Retained LCDC scan mode register LDSMR H 0000 H 0000 Retained Retained LCDC data fetch start address register for upper display panel LDSARU H 0C000000 H 0C000000 Retained Retained LCDC data fetch...

Page 1656: ...errupt control register LDINTR H 0000 H 0000 Retained Retained LCDC power management mode register LDPMMR H 0010 H 0010 Retained Retained LCDC power supply sequence period register LDPSPR H F60F H F60F Retained Retained LCDC control register LDCNTR H 0000 H 0000 Retained Retained LCDC user specified interrupt control register LDUINTR H 0000 H 0000 Retained Retained LCDC user specified interrupt li...

Page 1657: ...to the LCDC is 66 MHz or less regardless of the LCD_CL2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 R R R W R W R R R R R R R W R W R W R W R W R W ICKSEL 1 0 DCDR 5 0 Bit Initial value R W Bit Bit Name Initial Value R W Description 15 14 All 0 R Reserved These bits are always read as 0 The write value should always be 0 13 12 ICKSEL 1 0 00 R W Input Clock Select Set the ...

Page 1658: ...00 66 000 000001 1 1 50 000 60 000 66 000 000010 1 2 25 000 30 000 33 000 000011 1 3 16 667 20 000 22 000 000100 1 4 12 500 15 000 16 500 000110 1 6 8 333 10 000 11 000 001000 1 8 6 250 7 500 8 250 001100 1 12 4 167 5 000 5 500 010000 1 16 3 125 3 750 4 125 011000 1 24 2 083 2 500 2 750 100000 1 32 1 563 1 875 2 063 Note Any setting other than above is handled as a clock division ratio of 1 1 init...

Page 1659: ...OL DPOL MCNT CL1CNT CL2CNT MIFTYP 5 0 Bit Bit Name Initial Value R W Description 15 FLMPOL 0 R W FLM Vertical Sync Signal Polarity Select Selects the polarity of the LCD_FLM vertical sync signal first line marker for the LCD module 0 LCD_FLM pulse is high active 1 LCD_FLM pulse is low active 14 CL1POL 0 R W CL1 Horizontal Sync Signal Polarity Select Selects the polarity of the LCD_CL1 horizontal s...

Page 1660: ...t to output the LCD s current alternating signal of the LCD module 0 M AC line modulation signal is output 1 M signal is not output 9 CL1CNT 0 R W CL1 Horizontal Sync Signal Control Sets whether or not to enable CL1 output during the vertical retrace period 0 CL1 is output during vertical retrace period 1 CL1 is not output during vertical retrace period 8 CL2CNT 1 R W CL2 Dot Clock of LCD Module C...

Page 1661: ...or data specifications for an STN or DSTN panel see the specifications of the LCD panel used The output data bus width should be set according to the mechanical interface specifications of the LCD panel If an STN or DSTN panel is selected display control is performed using a 24 bit space modulation FRC consisting of the 8 bit R G and B included in the LCDC regardless of the color and gradation set...

Page 1662: ... PABD DSPCOLOR 6 0 Bit Bit Name Initial Value R W Description 15 to 9 All 0 R Reserved These bits are always read as 0 The write value should always be 0 8 PABD 0 R W Byte Data Pixel Alignment Sets the pixel data alignment type in one byte of data The contents of aligned data per pixel are the same regardless of this bit s setting For example data H 05 should be expressed as B 0101 which is the no...

Page 1663: ...ually selected by the display data and displayed The number of colors that can be selected in rotation mode is restricted by the display resolution For details see table 37 5 0000000 Monochrome 2 grayscales 1 bpp via palette 0000001 Monochrome 4 grayscales 2 bpp via palette 0000010 Monochrome 16 grayscales 4 bpp via palette 0000100 Monochrome 64 grayscales 6 bpp via palette 0001010 Color 16 colors...

Page 1664: ...write value should always be 0 13 ROT 0 R W Rotation Module Select Selects whether or not to rotate the display by hardware Note that the following restrictions are applied to rotation An STN or TFT panel must be used A DSTN panel is not allowed The maximum horizontal internal scan direction of the LCD panel width of the LCD panel is 320 Set a binary exponential that exceeds the display size in LD...

Page 1665: ...umber of column address bits and bus width of connected SDRAM For details see table 37 5 7 to 0 All 0 R Reserved These bits are always read as 0 The write value should always be 0 37 3 5 LCDC Start Address Register for Upper Display Data Fetch LDSARU LDSARU sets the start address from which data is fetched by the LCDC for display of the LCDC panel When a DSTN panel is used this register specifies ...

Page 1666: ...ot used Write 0 to the lower nine bits When using the hardware rotation function set the LDSARU value so that the upper left address of the image is aligned with the 512 byte boundary 2 When the hardware rotation function is used ROT 1 set the upper left address of the image which can be calculated from the display image size in this register The equation below shows how to calculate the LDSARU va...

Page 1667: ...R W R W R W R W R R R R Bit Initial value R W Bit Initial value R W SAL 25 16 SAL 15 4 Bit Bit Name Initial Value R W Description 31 to 28 All 0 R Reserved These bits are always read as 0 The write value should always be 0 27 26 All 1 R Reserved These bits are always read as 1 The write value should always be 1 25 to 4 SAL 25 4 All 0 R W Start Address for Lower Panel Display Data Fetch The start a...

Page 1668: ...t Initial value R W LAO 15 0 Bit Bit Name Initial Value R W Description 15 to 0 LAO 15 0 H 0280 R W Line Address Offset The minimum alignment unit of LDLAOR is 16 bytes Because the LCDC handles these values as 16 byte data the values written to the lower four bits of the register are always treated as 0 The lower four bits of the register are always read as 0 The initial values resolution 640 will...

Page 1669: ...0 R R R R R R R R R R R R R R R R W Bit Initial value R W PALS PALEN Bit Bit Name Initial Value R W Description 15 to 5 All 0 R Reserved These bits always read as 0 The write value should always be 0 4 PALS 0 R Palette State Indicates the access right state of the palette 0 Normal display mode LCDC uses the palette 1 Color palette setting mode The host CPU uses the palette 3 to 1 All 0 R Reserved ...

Page 1670: ... and B For details on the color palette specifications see section 37 4 3 Color Palette Specification 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R R R R R R R R R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W Bit Initial value R W PALDnn 23 16 PALDnn 15 0 Bit Bit Name Initial Value R W ...

Page 1671: ... H 4F 7 to 0 HTCN 7 0 01010010 R W Horizontal Total Character Number Set the number of total horizontal characters unit character 8 dots Specify to the value of the number of total characters 1 However the minimum horizontal retrace period is three characters 24 dots Example For a LCD module with a width of 640 pixels HTCN 640 8 1 3 82 H 52 In this case the number of total horizontal dots is 664 d...

Page 1672: ...nals CL1 and Hsync unit character 8 dots Specify to the value of the number of horizontal sync signal width 1 Example For a horizontal sync signal width of 8 dots HSYNW 8 dots 8 dots character 1 0 H 0 11 to 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7 to 0 HSYNP 7 0 01010000 R W Horizontal Sync Signal Output Position Set the output position of the horizon...

Page 1673: ...per and lower panels e g 480 for a 640 x 480 panel 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 1 1 R R R R R R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W VDLN 10 0 Bit Bit Name Initial Value R W Description 15 to 11 All 0 R Reserved These bits are always read as 0 The write value should always be 0 10 to 0 VDLN 10 0 00111011111 R W Vertical Display Line N...

Page 1674: ...W R W Bit Initial value R W VTLN 10 0 Bit Bit Name Initial Value R W Description 15 to 11 All 0 R Reserved These bits are always read as 0 The write value should always be 0 10 to 0 VTLN 10 0 00111011111 R W Vertical Total Line Number Set the total number of vertical display lines unit line Specify to the value of the number of total line 1 The minimum for the total number of vertical lines is 2 l...

Page 1675: ... of the vertical sync signal width 1 Example For a vertical sync signal width of 1 line VSYNW 1 1 0 H 0 11 0 R Reserved This bit is always read as 0 The write value should always be 0 10 to 0 VSYNP 10 0 00111011111 R W Vertical Sync Signal Output Position Set the output position of the vertical sync signals FLM and Vsync unit line Specify to the value of the number of vertical sync signal output p...

Page 1676: ... R R W R W R W R W R W Bit Initial value R W ACLN 4 0 Bit Bit Name Initial Value R W Description 15 to 5 All 0 R Reserved These bits are always read as 0 The write value should always be 0 4 to 0 ACLN 4 0 01100 R W AC Line Number Set the number of lines where the LCD current alternating signal of the LCD module is toggled unit line Specify to the value of the number of toggle line 1 Example For to...

Page 1677: ...ription 15 MINTEN 0 R W Memory Access Interrupt Enable Enables or disables an interrupt generation at the start point of each vertical retrace line period for VRAM access by LCDC 0 Disables an interrupt generation at the start point of each vertical retrace line period for VRAM access 1 Enables an interrupt generation at the start point of each vertical retrace line period for VRAM access 14 FINTE...

Page 1678: ...tine this bit should be cleared by writing 0 0 LCDC did not generate a memory access interrupt or has been informed that the generated memory access interrupt has completed 1 LCDC has generated a memory access end interrupt and not yet been informed that the generated memory access interrupt has completed 10 FINTS 0 R W Flame End Interrupt State Indicates the flame end interrupt handling state Thi...

Page 1679: ...ed 1 LCDC has generated a Vsync start interrupt and has not yet been informed that the generated Vsync start interrupt has completed 8 VEINTS 0 R W Vsync End Interrupt State Indicates the LCDC s Vsync end interrupt handling state This bit is set to 1 at the time a Vsync end interrupt is generated During the Vsync end interrupt handling routine this bit should be cleared by writing 0 0 LCDC did not...

Page 1680: ...e period from LCD_VEPWC assertion to LCD_DON assertion in the power on sequence of the LCD module in frame units Specify to the value of the period 1 This period is the c period in figures 37 4 to 37 7 Power Supply Control Sequence and States of the LCD Module For details on setting this register see table 37 6 Available Power Supply Control Sequence Periods at Typical Frame Rates The setting meth...

Page 1681: ...VEPWC pin 0 Disabled LCD_VEPWC pin is masked and fixed low 1 Enabled LCD_VEPWC pin output is asserted and negated according to the power on or power off sequence 4 DONE 1 R W LCD_DON Pin Enable Sets whether or not to enable a power supply control sequence using the LCD_DON pin 0 Disabled LCD_DON pin is masked and fixed low 1 Enabled LCD_DON pin output is asserted and negated according to the power...

Page 1682: ...DC Power On Sequence Period Set the period from LCD_VCPWC assertion to starting output of the display data LCD_D and timing signals LCD_FLM LCD_CL1 LCD_CL2 and LCD_M_DISP in the power on sequence of the LCD module in frame units Specify to the value of the period 1 This period is the a period in figures 37 4 to 37 7 Power Supply Control Sequence and States of the LCD Module 11 to 8 ONB 3 0 0110 R ...

Page 1683: ... in frame units Specify to the value of the period 1 This period is the e period in figures 37 4 to 37 7 Power Supply Control Sequence and States of the LCD Module 3 to 0 OFFF 3 0 1111 R W LCDC Power Off Sequence Period Set the period from stopping output of the display data LCD_D and timing signals LCD_FLM LCD_CL1 LCD_CL2 and LCD_M_DISP to LCD_VCPWC negation to in the power off sequence of the LC...

Page 1684: ...B 00 Do not make any action to the DON bit until the sequence ends 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R W R R R R W DON2 Bit Initial value R W DON Bit Bit Name Initial Value R W Description 15 to 5 All 0 R Reserved These bits are always read as 0 The write value should always be 0 4 DON2 0 R W Display On 2 Specifies the start of the LCDC dis...

Page 1685: ...generated and indicates its processing state This interrupt is generated at the time when image data which is set by the line number register LDUINTLNR in LCDC is read from VRAM This LCDC issues the interrupts LCDCI user specified interrupt by this register memory access interrupt by the LCDC interrupt control register LDINTR and OR of Vsync interrupt output This register and LCDC interrupt contro...

Page 1686: ...ser specified interrupt and has not yet been notified that the generated user specified interrupt has completed Note Interrupt processing flow 1 Interrupt signal is input 2 LDINTR is read 3 If MINTS FINTS VSINTS or VEINTS is 1 a generated interrupt is memory access interrupt flame end interrupt Vsync rising edge interrupt or Vsync falling edge interrupt Processing for each interrupt is performed 4...

Page 1687: ...INTLN 10 0 00001001111 R W User Specified Interrupt Generation Line Number Specifies the line in which the user specified interrupt is generated line units Set the number of lines in which interrupts are generated 1 Example Generate the user specified interrupt in the 80th line UINTLN 160 2 1 79 H 04F Notes 1 When using the LCD module with STN TFT display the setting value of this register should ...

Page 1688: ...esses VRAM one clock after the LCDC accessed VRAM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R W R W R W R W R W R W R W R W Bit Initial value R W LIRN 7 0 Bit Bit Name Initial Value R W Description 15 to 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7 to 0 LIRN 7 0 All 0 R W VRAM Read Bus Cycle Interval Specifies t...

Page 1689: ...memory read operation and a 2 4 Kbyte line buffer so although a complete breakdown of the display is unlikely there may be some problems with the display depending on the combination A recommended size at the frame rate of 60 Hz is 320 240 dots in 16 bpp or 640 480 dots in 8 bpp As a rough standard the bus occupation ratio shown below should not exceed 40 Bus occupation ratio Overhead coefficient ...

Page 1690: ...e Back Porch Back Porch Hsync Signal Vsync Signal Active Video Top Left Border Addressable Video Bottom Right Border Total H Blank Hsync Time Back Porch Front Porch Total V Blank Vsync Time Back Porch Front Porch HTCN H Total Time HDCN H Addressable Video HSYNP H Addressable Video Right Border Front Porch HSYNW Hsync Time VTLN V Total Time CDLN V Addressable Video VSYNP V Addressable Video Bottom ...

Page 1691: ...th are shown table 37 5 A monochromatic LCD module is necessary for the display of images in the above monochromatic formats A color LCD module is necessary for the display of images in the above color formats Table 37 5 Limits on the Resolution of Rotated Displays Burst Length and Connected Memory 32 bit SDRAM Image for Display in Memory X Resolution Y Resolution LCD Module X Resolution Y Resolut...

Page 1692: ...bursts 234 320 320 234 9 bits Not more than 8 bursts Monochrome 6 bpp 10 bits Not more than 16 bursts 9 bits 4 bursts Color 16 bpp 10 bits Not more than 8 bursts 80 160 160 80 Monochrome 9 bits 2 bpp 10 bits 9 bits 4 bpp packed 10 bits 9 bits Not more than 16 bursts 4 bpp unpacked 10 bits 9 bits Not more than 16 bursts 6 bpp 10 bits Color 9 bits 4 bpp packed 10 bits 9 bits Not more than 16 bursts ...

Page 1693: ... of Column Address Bits of SDRAM Burst Length of LCDC LDSMR 64 128 128 64 Monochrome 1 bpp 9 bits 10 bits 2 bpp 9 bits 10 bits 9 bits 4 bpp packed 10 bits 9 bits 4 bpp unpacked 10 bits 6 bpp 9 bits 10 bits Color 4 bpp 9 bits packed 10 bits 4 bpp 9 bits unpacked 10 bits 8 bpp 9 bits 10 bits Note Specify the data of the number of line specified as burst length can be stored in address of SDRAM same ...

Page 1694: ...set to 1 0 7 15 23 31 Color Monochrome B0 B1 B2 B3 B4 B5 B6 B7 G0 G1 G2 G3 G4 G5 G6 G7 R0 R1 R2 R3 R4 R5 R6 R7 M0 M1 M2 M3 M4 M5 M6 M7 Figure 37 3 Color Palette Data Format PALDnn color and gradation data should be set as above For a color display PALDnn 23 16 PALDnn 15 8 and PALDnn 7 0 respectively hold the R G and B data Although the bits PALDnn 18 16 PALDnn 9 8 and PALDnn 2 0 exist no memory is...

Page 1695: ...ed Format Address 00 01 02 03 LAO 00 LAO 01 LAO 02 LAO 03 Bit Byte0 Byte1 MSB LSB P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 7 6 5 4 3 2 1 0 Display Memory 3 Packed 4bpp Pixel Alignment in Byte is Big Endian Windows CE Recommended Format Address 00 01 02 03 LAO 00 LAO 01 LAO 02 LAO 03 Bit Byte0 Byte1 Byte2 MSB LSB P00 P01 P02 P03 P10 P11 P12 P13 P04 P05 P14 P15 7 6 5 4 3 2 1 0...

Page 1696: ...ay Memory Top Left Pixel P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 Display Pn Pn 1 0 Put 2 bit data LAO Line Address Offset Unused bits should be 0 Top Left Pixel P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 Display Pn Pn 3 0 Put 4 bit data LAO Line Address Offset Unused bits should be 0 4 Packed 1bpp Pixel Alignment in Byte is Little Endian Address 00 01 0...

Page 1697: ...ft Pixel P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 Display Pn Pn 3 0 Put 4 bit data LAO Line Address Offset Unused bits should be 0 Top Left Pixel P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 Display Pn Pn 4 0 Put 5 bit data LAO Line Address Offset Unused bits should be 0 9 Unpacked 6bpp Windows CE Recommended Format Address 00 01 02 03 LAO 00 LAO 01 LAO 02...

Page 1698: ...LAO 06 Bit Word0 Word2 Word4 MSB LSB P00R P01R P10R P11R P02R P12R P00G P01G P10G P11G P02G P12G P00B P01B P10B P11B P02B P12B 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Display Memory Top Left Pixel P00P01 P02 P03 P04 P05 P06 P07 P10P11 P12 P13 P14 P15 P16 P17 Display Pn Pn 7 0 Put 8 bit data LAO Line Address Offset Unused bits should be 0 Top Left Pixel P00P01 P02 P03 P04 P05 P06 P07 P10P11 P12 P13 P...

Page 1699: ...ble to issue an interrupt at the beginning of each vertical retrace line period to be exact at the beginning of the line after the last line of the display This function is set up by using the LDINTR 37 4 6 Power Supply Control Sequence An LCD module normally requires a specific sequence for processing to do with the cutoff of the input power supply Settings in LDPMMR LDPSPR and LDCNTR in conjunct...

Page 1700: ...out LCD_DON pin Register control sequence Figure 37 4 Power Supply Control Sequence and States of the LCD Module 00b 00b 11b a 0 frame b 0 frame c 1 frame d 1 frame f 0 frame e 0 frame VCPE OFF VEPE OFF DONE ON Start power supply Start power cutoff Arbitrary Undefined Undefined LCD module active LCD module stopped LCD module stopped Internal signal Internal signal 2 Power Supply Control for LCD Pa...

Page 1701: ...le stopped e 1 frame f 1 frame a 1 frame 00b 11b 00b 11b Figure 37 6 Power Supply Control Sequence and States of the LCD Module 00b 00b 11b a 0 frame b 0 frame c 0 frame d 0 frame e 0 frame f 0 frame VCPE OFF 4 Power Supply Control for LCD panels other than TFT VEPE OFF DONE OFF Internal signal Internal signal Internal signal Start power supply Start power cutoff Arbitrary Undefined Undefined in D...

Page 1702: ...00 ms 11 1 60 200 00 ms H C 12 1 120 108 33 ms 12 1 60 216 67 ms H D 13 1 120 116 67 ms 13 1 60 233 33 ms H E 14 1 120 125 00 ms 14 1 60 250 00 ms ONA ONB ONC OFFD OFFE and OFFF are used to set the power supply control sequence periods in units of frames from 0 to 15 1 is subtracted from each register H 0 to H E settings select from 1 to15 frames The setting H F selects 0 frames Actual sequence pe...

Page 1703: ...er setting DON 0 Register access is enabled Fixed resolution the format of the data for display is determined by the number of colors and timing signals are not output to the LCD module Table 37 8 LCD Module Power Supply States STN DSTN module State Power Supply for Logic Display Data Timing Signal Power Supply for High Voltage Systems DON Signal Control Pin LCD_VCPWC LCD_CL2 LCD_CL1 LCD_FLM LCD_M...

Page 1704: ...e normal operation is not guaranteed In the worst case the connected LCD module may be damaged 37 4 7 Operation for Hardware Rotation Operation in hardware rotation mode is described below Hardware rotation mode can be thought of as using a landscape format LCD panel instead of a portrait format LCD panel by placing the landscape format LCD panel as if it were a portrait format panel Whether the p...

Page 1705: ...int 1 Normal mode Figure 37 8 Operation for Hardware Rotation Normal Mode For example the registers have been set up for the display of image data in landscape format 320 240 which starts from LDSARU 0x0c001000 on a 320 240 LCD panel The graphics driver software is complete Some changes are required to apply hardware rotation and use the panel as a 240 320 display If LDLAOR is 512 the graphics dri...

Page 1706: ... possible regardless of the drawing processing carried out by the graphics driver software However the sizes in the image data and address offset values which are managed by the graphics driver software must be altered Picture image LDSARU start point LDSARU LDLAOR HDCN 8 2 1 end point Scanning starts from LDSARU Scanning is done from large address to small address of Y coordination LCD panel Star...

Page 1707: ...s DOTCLK 1 STN monochrome 4 bit data bus module LCD_CL2 LCD_D0 LCD_D1 LCD_D2 LCD_D3 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 LCD_D4 to 15 Low Figure 37 10 Clock and LCD Data Signal Example DOTCLK 2 STN monochrome 8 bit data bus module LCD_CL2 LCD_D0 LCD_D1 LCD_D2 LCD_D3 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 LCD_D8 to 15 Low LCD_D4 LCD_D5 LCD_D6 LCD_D7 B12 B13 B14 B15 Figure 37 11 Cloc...

Page 1708: ...11 B14 R15 G15 B15 R12 G12 B12 R13 G13 B13 R14 G14 Figure 37 12 Clock and LCD Data Signal Example STN Color 4 Bit Data Bus Module DOTCLK 4 STN color 8 bit data bus module LCD_CL2 LCD_D0 LCD_D1 LCD_D2 LCD_D3 R0 G0 B0 R1 G1 R2 G2 LCD_D8 to 15 Low LCD_D4 LCD_D5 LCD_D6 LCD_D7 B1 B2 R3 G3 R4 G4 B3 R5 B4 G5 B5 R6 G6 R7 G7 B6 B7 R8 G8 B8 R9 G9 R10 G10 B9 B10 R11 G11 R12 G12 B11 R13 B12 G13 B13 R14 G14 R1...

Page 1709: ...D0 LCD_D1 LCD_D2 LCD_D3 R0 G0 B0 R1 G1 R2 G2 LCD_D12 to 15 Low LCD_D4 LCD_D5 LCD_D6 LCD_D7 B1 B2 R3 G3 R4 G4 B3 R5 B4 G5 B5 R6 G6 R7 G7 B6 B7 R8 G8 B8 R9 G9 R10 G10 B9 B10 R11 G11 R12 G12 B11 R13 B12 G13 B13 R14 G14 R15 G15 B14 B15 LCD_D8 LCD_D9 LCD_D10 LCD_D11 Figure 37 14 Clock and LCD Data Signal Example STN Color 12 Bit Data Bus Module ...

Page 1710: ...D1 LCD_D2 LCD_D3 R0 G0 B0 R1 G1 R2 G2 LCD_D4 LCD_D5 LCD_D6 LCD_D7 B1 B2 R3 G3 R4 G4 B3 R5 B4 G5 B5 R6 G6 R7 G7 B6 B7 R8 G8 B8 R9 G9 R10 G10 B9 B10 R11 G11 R12 G12 B11 R13 B12 G13 B13 R14 G14 R15 G15 B14 B15 LCD_D8 LCD_D9 LCD_D10 LCD_D11 LCD_D12 LCD_D13 LCD_D14 LCD_D15 Figure 37 15 Clock and LCD Data Signal Example STN Color 16 Bit Data Bus Module ...

Page 1711: ...100 DOTCLK 7 DSTN monochrome 8 bit data bus module LCD_CL2 LCD_D0 LCD_D1 LCD_D2 LCD_D3 UB0 UB1 UB2 UB3 LB0 LB1 LB2 LB3 UB4 UB5 UB6 UB7 LCD_DATA8 to 15 Low LCD_D4 LCD_D5 LCD_D6 LCD_D7 LB4 LB5 LB6 LB7 Figure 37 16 Clock and LCD Data Signal Example DSTN Monochrome 8 Bit Data Bus Module ...

Page 1712: ...chrome 16 bit data bus module LCD_CL2 LCD_D0 LCD_D1 LCD_D2 LCD_D3 LCD_D4 LCD_D5 LCD_D6 LCD_D7 UB0 UB1 UB2 UB4 UB5 UB3 UB7 UB6 LB0 LB1 LB2 LB3 LB5 LB6 LB4 LB7 LCD_D8 LCD_D9 LCD_D10 LCD_D11 LCD_D12 LCD_D13 LCD_D14 LCD_D15 Figure 37 17 Clock and LCD Data Signal Example DSTN Monochrome 16 Bit Data Bus Module ...

Page 1713: ..._D0 LCD_D1 LCD_D2 LCD_D3 UR0 UG0 UB0 UR1 UG1 UR2 UG2 LCD_D8 to 15 Low LCD_D4 LCD_D5 LCD_D6 LCD_D7 UB1 UB2 UR3 UG3 UR4 UG4 UB3 UR5 UB4 UG5 UB5 UR6 UG6 UR7 UG7 UB6 UB7 LR0 LG0 LB0 LR1 LG1 LR2 LG2 LB1 LB2 LR3 LG3 LR4 LG4 LB3 LR5 LB4 LG5 LB5 LR6 LG6 LR7 LG7 LB6 LB7 Figure 37 18 Clock and LCD Data Signal Example DSTN Color 8 Bit Data Bus Module ...

Page 1714: ...D10 LCD_D11 UR0 UG0 UB0 UR1 UR2 UG2 UB2 UR3 UR4 UG4 UB4 UR5 UR6 UG6 UB6 UR7 LCD_D12 to 15 Low LCD_D4 LCD_D5 LCD_D6 LCD_D7 UG1 UB1 LR0 LG0 UG3 UB3 LR2 LG2 UG5 UB5 LR4 LG4 UG7 UB7 LR6 LG6 LCD_D0 LCD_D1 LCD_D2 LCD_D3 LB0 LR1 LG1 LB1 LB2 LR3 LG3 LB3 LB4 LR5 LG5 LB5 LB6 LR7 LG7 LB7 Figure 37 19 Clock and LCD Data Signal Example DSTN Color 12 Bit Data Bus Module ...

Page 1715: ...D3 UR0 UG0 UB0 UR1 UG1 UR2 UG2 LCD_D4 LCD_D5 LCD_D6 LCD_D7 UB1 UB2 UR3 UG3 UR4 UG4 UB3 UR5 UB4 UG5 UB5 UR6 UG6 UR7 UG7 UB6 UB7 LCD_D8 LCD_D9 LCD_D10 LCD_D11 LCD_D12 LCD_D13 LCD_D14 LCD_D15 LR0 LG0 LB0 LR1 LG1 LR2 LG2 LB1 LB2 LR3 LG3 LR4 LG4 LB3 LR5 LB4 LG5 LB5 LR6 LG6 LR7 LG7 LB6 LB7 Figure 37 20 Clock and LCD Data Signal Example DSTN Color 16 Bit Data Bus Module ...

Page 1716: ... LCD_D6 B05 LCD_D7 LCD_D8 LCD_D9 LCD_D10 LCD_D11 LCD_D12 LCD_D13 LCD_D14 LCD_D15 G00 G01 G02 G03 G04 G05 R01 R02 R03 R04 R05 B11 B12 B13 B14 B15 G10 G11 G12 G13 G14 G15 R11 R12 R13 R14 R15 B21 B22 B23 B24 B25 G20 G21 G22 G23 G24 G25 R21 R22 R23 R24 R25 B31 B32 B33 B34 B35 G30 G31 G32 G33 G34 G35 R31 R32 R33 R34 R35 Figure 37 21 Clock and LCD Data Signal Example TFT Color 16 Bit Data Bus Module ...

Page 1717: ... LCD_CL1 Valid Valid Valid Valid Valid LCD_D One horizontal time LCD_FLM 1st line data 2nd line data One frame time 480 CL1 1st line data LCD_CL2 2nd line data Next frame time 480 CL1 No vertical retrace One vertical retrace LCD_CL1 LCD_D Valid Valid One horizontal time LCD_FLM 1st line data 2nd line data One frame time 481 CL1 1st line data LCD_CL2 2nd line data Next frame time 480 CL1 Vertical r...

Page 1718: ...frame time 480 CL1 1st line data LCD_CL2 2nd line data 480th line data Next frame time 480 CL1 No vertical retrace Horizontal wave B639 3 B639 4 B639 5 B639 6 B639 7 G639 2 G639 3 G639 4 G639 5 G639 6 G639 7 R639 3 R639 4 R639 5 R639 6 R639 7 LCD_D8 LCD_D9 LCD_D10 LCD_D11 LCD_D12 LCD_D13 LCD_D14 LCD_D15 B0 3 B0 4 B0 5 B0 6 B0 7 G0 2 G0 3 G0 4 G0 5 G0 6 G0 7 R0 3 R0 4 R0 5 R0 6 R0 7 8DCLK 8DCLK 8DC...

Page 1719: ...t for the display time for a single frame to elapse This halting procedure is required before selecting self refreshing for the display data storage VRAM DDR SDRAM in area 3 or making a transition to standby mode or module standby mode 37 6 2 Notes on Using NMI Interrupt If the NMIFL bit in the NMIFCR register is set to 1 by an NMI interrupt while the LCDC is used the LCDC cannot access the VRAM t...

Page 1720: ...Section 37 LCD Controller LCDC Rev 1 00 Oct 01 2007 Page 1654 of 1956 REJ09B0256 0100 ...

Page 1721: ...elow 10 bit resolution Four input channels High speed conversion Conversion time maximum 8 5 µs per channel Pck0 33 MHz operation Three conversion modes Single mode A D conversion on one channel Multi mode A D conversion on one to four channels Scan mode Continuous A D conversion on one to four channels Four 16 bit data registers Sample and hold function A D interrupt requested at the end of conve...

Page 1722: ...ntrol circuit Peripheral Clock Pck0 Successive approxi mation register Comparator Sample and hold circuit ADI interrupt signal AVss AN0 AN1 AN2 AN3 ADCSR Pck0 4 Pck0 8 Pck0 16 Pck0 32 AVcc A D converter ADCR ADCSR ADDRA ADDRB ADDRC ADDRD A D control register A D control status register A D data register A A D data register B A D data register C A D data register D Legend ADDRC Internal data bus Fi...

Page 1723: ...in the A D converter AVcc also functions as the A D converter reference voltage pin Table 38 1 Pin Configuration Pin Name Abbreviation I O Function Analog power supply pin AVcc Input Analog power supply Analog ground pin AVss Input Analog ground and reference voltage for A D conversion Analog input pin 0 AN0 Input Analog input pin 1 AN1 Input Analog input pin 2 AN2 Input Analog input pin 3 AN3 Inp...

Page 1724: ...ress space using the TLB Table 38 3 Register State in Each Operating Mode Register Name Abbreviation Power On Reset Manual Reset Sleep Standby A D data register A ADDRA H 0000 H 0000 Retained Retained A D data register B ADDRB H 0000 H 0000 Retained Retained A D data register C ADDRC H 0000 H 0000 Retained Retained A D data register D ADDRD H 0000 H 0000 Retained Retained A D control status regist...

Page 1725: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Bit Initial value R W AD 9 0 Bit Bit Name Initial Value R W Description 15 to 6 AD 9 0 0 R Bit data 10 bits 5 to 0 All 0 R Reserved These bits are always read as 0 The write value should always be 0 Table 38 4 Analog Input Channels and A D Data Registers Analog Input Channel A D Data Register AN0 ADDRA AN1 ADDRB AN2 ADDRC AN3 ADDRD ...

Page 1726: ...ngle mode A D conversion ends Multi mode A D conversion has cycled through the selected channels A D conversion cycles through the selected channels Scan mode A D conversion has cycled through the selected channels A D conversion is continuously repeated for the selected channels Note When clearing the ADST bit to 0 to stop A D conversion in scan mode or in multi mode ADF 0 after clearing the ADST...

Page 1727: ... is cleared to 0 by software A D conversion does not stop 0 cannot be written to this bit during A D conversion Multi mode A D conversion starts This bit is cleared to 0 automatically when conversion on the specified channels has been performed for one cycle When the ADST bit is cleared to 0 by software A D conversion stops when the currently executed channel ends Scan mode A D conversion starts A...

Page 1728: ...etting prohibited 10 Multi mode 11 Scan mode 3 0 R Reserved These bits are always read as 0 The write value should always be 0 2 to 0 CH 2 0 000 R W Channel Select These bits and the MDS bit select the analog input channels Clear the ADST bit to 0 before changing the channel selection Single mode Multi mode or scan mode 000 AN0 AN0 001 AN1 AN0 AN1 010 AN2 AN0 to AN2 011 AN3 AN0 to AN3 100 Reserved...

Page 1729: ...input channel during A D conversion first clear the ADST bit to 0 to halt A D conversion in order to avoid malfunction After the change has been made setting the ADST bit to 1 resumes A D conversion Typical operations when channel 1 AN1 is selected in single mode are described below Figure 38 2 shows a timing diagram for this example 1 Select single mode as the operating mode MDS 1 0 00 AN1 as the...

Page 1730: ...ore are converted once each A D conversion starts with the first channel AN0 when the ADST bit bit 13 of the A D control status register ADCSR is set to 1 by software When multiple channels are selected A D conversion for the second channel AN1 starts immediately after A D conversion for the first channel ends A D conversion on the specified channels is performed for one cycle The conversion resul...

Page 1731: ...version proceeds in the same way up to the third channel AN2 4 When A D conversion of all selected channels AN0 to AN2 is completed the ADF bit is set to 1 the ADST bit is cleared to 0 and A D conversion stops If the ADIE bit is set to 1 at this time an ADI interrupt is generated after A D conversion ends Idle ADST Channel 0 AN0 A D conversion 1 Idle ADF A D conversion 2 Idle Channel 1 AN1 Channel...

Page 1732: ...T bit to 1 selects the first channel and A D conversion is resumed Typical operations when three channels AN0 to AN2 are selected in scan mode are described below Figure 38 4 shows a timing diagram for this example 1 Select scan mode as the operating mode MDS 1 0 11 and AN0 to AN2 as the input channels CH 2 0 010 Then start A D conversion ADST 1 2 A D conversion of the first channel AN0 starts Whe...

Page 1733: ...A D conversion result 3 ADDRA ADDRB ADDRC ADDRD A D conversion 3 Idle Idle A D conversion result 2 Idle A D conversion 4 A D conversion 5 Idle Idle A D conversion result 4 Set Clear Consecutive A D conversion execution Clear Note Vertical arrows indicate instruction execution by software ADI Interrupt occurs A D conversion result 5 Figure 38 4 Example of A D Converter Operation Scan Mode Three Cha...

Page 1734: ... 136 139 268 275 532 547 1060 1091 A D conversion time for the second and subsequent conversions multi mode or scan mode 128 256 512 1024 Notes Values in the table are the numbers of states one state is one peripheral clock IO Bus Pck0 cycle Period starting from when the ADST bit is set to 1 and until data is stored in the register 38 5 Interrupts The A D converter generates an A D conversion end ...

Page 1735: ...stics when the digital output value changes from the minimum zero voltage 0000000000 000 in figure 38 5 to 0000000001 001 in figure 38 5 2 Full scale error figure 38 5 2 Deviation between actual A D conversion characteristics and ideal A D conversion characteristics when the digital output value changes from 1111111110 110 in figure 38 5 to the maximum 1111111111 111 in figure 38 5 3 Quantization ...

Page 1736: ...0 010 011 0 1 8 2 8 3 8 4 8 5 8 6 8 7 8 FS Analog input voltage Analog input voltage FS Full scale voltage 3 Quantization error Ideal A D conversion characteristic Ideal A D conversion characteristic FS 4 Nonlinearity error Digital output 2 Full scale error 1 Offset error Figure 38 5 Definitions of A D Conversion Accuracy ...

Page 1737: ...3 V and AVss Vss AVcc Analog power supply AVss Analog ground Vss Internal digital power supply 38 7 2 Processing of Analog Input Pins To prevent damage from abnormal voltage such as voltage surges at the analog input pins AN0 to AN3 connect a protection circuit like the one shown in figure 38 6 The circuit shown also includes a CR filter to suppress noise This circuit is shown as an example the ci...

Page 1738: ...ns be sure to see table 38 6 when setting the Pck0 clock and clock division ratio Table 38 6 Relationship between Clock Division Ratio and Usable Pck0 Clock Frequency Clock Division Ratio Pck0 Clock Pck0 4 18 MHz or lower Pck0 8 34 MHz or lower Pck0 16 67 MHz or lower Pck0 32 67 MHz or lower 38 7 4 A D Conversion Stop In multi mode or scan mode A D conversion does not stop as soon as the setting t...

Page 1739: ...F Output voltage 0 V to AVcc analog power supply Figure 28 1 shows the block diagram for the DAC Analog I O buffer DADR0 AVcc AVss DA0 DA1 DAO1 DAO0 DADR1 DACR 8 bit D A converter D A converter circuit Peripheral clock Pck0 Control circuit Peripheral data bus Legend DACR DADR0 DADR1 AVcc AVss DAO0 DAO1 D A control register D A data register 0 D A data register 1 Analog power supply Analog ground A...

Page 1740: ...Register Configuration Register Name Abbreviation R W Area P4 Address Area 7 Address Access Size D A data register 0 DADR0 R W H FFEA 8000 H 1FEA 8000 8 D A data register 1 DADR1 R W H FFEA 8002 H 1FEA 8002 8 D A control register DACR R W H FFEA 8004 H 1FEA 8004 8 Note P4 addresses are used when area P4 in the virtual address space is used and area 7 addresses are used when accessing the register ...

Page 1741: ...er DACR are set to 1 the contents of the D A data register are converted and output to analog output pins DA0 DA1 The D A data register is initialized to H 00 at reset Note that the D A data register is not initialized upon entering the software standby module standby or hardware standby mode 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit Initial value Bit Bit Name Initial...

Page 1742: ...it Initial value Bit Bit Name Initial Value R W Description 7 DAOE1 0 R W Controls D A conversion for channel 1 and analog output 0 D A conversion for channel 1 and analog output DA1 are disabled 1 D A conversion for channel 1 and analog output DA1 are enabled 6 DAOE0 0 R W Controls D A conversion for channel 0 and analog output 0 D A conversion for channel 0 and analog output DA0 are disabled 1 D...

Page 1743: ...1 Write conversion data to DADR0 2 When the DAOE0 bit in DACR is set to 1 D A conversion starts The results are output after the conversion has ended The output value will be DADR0 contents 256 AVcc The conversion results are output continuously until DADR0 is modified or the DAOE0 bit is cleared to 0 3 When D A data register 0 DMDR0 is modified the conversion starts again The results are output a...

Page 1744: ...ction 39 D A Converter DAC Rev 1 00 Oct 01 2007 Page 1678 of 1956 REJ09B0256 0100 39 5 Usage Notes The input voltages AVcc and AVss of the analog power supply should be as follows AVcc 3 3 0 3 V AVss Vss ...

Page 1745: ...ther a General Purpose I O GPIO pin or a peripheral module pin The GPIO has the following features Each port pin is a multiplexed pin for which the port control register can set the pin function and MOS pull up control individually Each port has a data register that stores data for its pins GPIO interrupts are supported Table 40 1 lists the multiplexed pins controlled by the GPIO registers Each po...

Page 1746: ...rt AD12 TRI PCIC PTA4 Input output Port AD13 TRI PCIC SCIF1_RTS Input output SCIF1 PTA3 Input output Port AD15 TRI PCIC SCIF1_CTS Input output SCIF1 PTA2 Input output Port LOCK STRI PCIC SCIF1_TXD Output SCIF1 PTA1 Input output Port DEVSEL STRI PCIC SCIF1_RXD Input SCIF1 A PTA0 Input output Port PAR TRI PCIC SCIF1_SCK Input output SCIF1 PTB7 Input output Port AD6 TRI PCIC LCDM_D2 Output LCDCM PINT...

Page 1747: ...ERR O D PCIC LCDM_D9 Output LCDCM PINT9 Input INT B PTB0 Input output Port PERR STRI PCIC LCDM_D10 Output LCDCM PINT8 Input INT PTC7 Input output Port AD3 TRI PCIC MMC_CLK Output MMC PTC6 Input output Port AD5 TRI PCIC LCDM_CL1 Output LCDCM PTC5 Input output Port AD0 TRI PCIC MMC_CD Input MMC LCDM_FLM Output LCDCM PTC4 Input output Port AD7 TRI PCIC MMC_CMD Input output MMC LCDM_CL2 Output LCDCM P...

Page 1748: ...SI1 LCDM_DON Output LCDCM PTD3 Input output Port PCIFRAME STRI PCIC PCC_BVD2 Input PCC SIOF0_SCK Input output SIOF0 HAC_RES Output HAC LCDM_D12 Output LCDCM PTD2 Input output Port TRDY STRI PCIC PCC_RDY Input PCC SIOF0_RXD Input SIOF0 HAC_SYNC Output HAC LCDM_D11 Output LCDCM PTD1 Input output Port CBE2 TRI PCIC PCC_VS2 Input PCC SIOF0_TXD Output SIOF0 HAC_SD_OU T Output HAC LCDM_D15 Output LCDCM ...

Page 1749: ...CBE3 TRI PCIC ET1_TX CLK Input MII1 PTF2 Input output Port AD31 TRI PCIC SIM_RST Output SIM ET1_MDIO Input output MII1 TEND3 Output DMAC3 PTF1 Input output Port REQ0 REQOUT TRI PCIC SIM_CLK Output SIM ET1_MDC Output MII1 DACK3 Output DMAC3 F PTF0 Input output Port GNT0 GNTIN TRI PCIC SIM_D Input output SIM ET1_ETXD3 Output MII1 DREQ3 Input DMAC3 PTG7 Input output Port AD28 TRI PCIC ET1_TX EN Outpu...

Page 1750: ...I1M PTH5 Input output Port AD23 TRI PCIC TPU_TO1 Output TPU ET1_ERXD1 Input MII1 RMII1M_TXD0 Output RMII1M PTH4 Input output Port AD19 TRI PCIC TPU_TO0 Output TPU ET1_ERXD3 Input MII1 RMII1M_RXD0 Input RMII1M PTH3 Input output Port AD21 TRI PCIC TPU_TI2B Input TPU ET1_ERXD2 Input MII1 RMII1M_RXD1 Input RMII1M PTH2 Input output Port AD24 TRI PCIC TPU_TI2A Input TPU ET1_ERXD0 Input MII1 RMII1M_TXD1 ...

Page 1751: ...rt ST0M_STARTI Input STIF0M IIC0_SCL Input output IIC0 SIOF1_RXD Input SIOF1 USB_ OVERCRT USBF_VBUS Input USBH F PTI1 Input output Port STATUS1 Output ST1_REQ Input output STIF1 RMII0_MDIO Input output RMII0 I PTI0 Input output Port STATUS0 Output ST1_CLK ST1_STRB Input output STIF1 RMII0_MDC Output RMII0 PTJ7 Input output Port INTB Input PCIC ST0M_D5I Input STIF0M IRQOUT Output INT RMII1_TXD0 Out...

Page 1752: ...ST1_D6 Input output STIF1 GET0_ERXD6 Input GMII0 SIOF2_SCK Input output SIOF2 LCD_VEPWC Output LCDC PTK5 Input output Port ST1_D5 Input output STIF1 GET0_ERXD5 Input GMII0 SIOF2_RXD Input SIOF2 LCD_D7 Output LCDC PTK4 Input output Port ST1_D4 Input output STIF1 GET0_ERXD4 Input GMII0 SIOF2_TXD Output SIOF2 LCD_D6 Output LCDC PTK3 Input output Port ST1_D3 Input output STIF1 GET0_ETXD7 Output GMII0 ...

Page 1753: ... Input output LBSC 2 EXCPU IRQ6 IRL6 Input INT ET0_ETXD3 Output MII0 TEND0 Output DMAC0 LCD_D10 Output LCDC PTL1 Input output Port D17 EX_AD17 Input output LBSC 2 EXCPU IRQ5 IRL5 Input INT ET0_MDC Output MII0 DACK0 Output DMAC0 LCD_D9 Output LCDC L PTL0 Input output Port D16 EX_AD16 Input output LBSC 2 EXCPU IRQ4 IRL4 Input INT ET0_COL Input MII0 DREQ0 Input DMAC0 LCD_D8 Output LCDC PTM7 Input out...

Page 1754: ...MII0_RX_ ER Input RMII0 PINT1 Input INT M PTM0 Input output Port D24 EX_AD24 Input output LBSC 2 EXCPU ST0_D0 Input output STIF0 ET0_TX ER Output MII0 RMII0M0_ MDIO Input output RMII0M0 PINT0 Input INT PTN5 Input output Port NMI Input INT PTN4 Input output Port SCIF0_RTS Input output SCIF0 MD2 1 Input CPG PTN3 Input output Port SCIF0_CTS Input output SCIF0 MD4 1 Input LBSC PTN2 Input output Port S...

Page 1755: ...O Input output RMII0M1 SSI2_SCK Input output SSI2 PTO2 Input output Port AUDATA1 Output AUD RMII0M1_ MDC Output RMII0M1 PTO1 Input output Port AUDATA0 Output AUD RMII1_MDIO Input output RMII1 SSI2_SDATA Input output SSI2 O PTO0 Input output Port AUDSYNC Output AUD RMII1_MDC Output RMII1 SSI2_WS Input output SSI2 Legend TRI Tri state STRI Sustained tri state O D Open drain Note 1 Hatched areas in t...

Page 1756: ...EF 000E H 1FEF 000E 16 Port I control register PICR R W H FFEF 0010 H 1FEF 0010 16 Port J control register PJCR R W H FFEF 0012 H 1FEF 0012 16 Port K control register PKCR R W H FFEF 0014 H 1FEF 0014 16 Port L control register PLCR R W H FFEF 0016 H 1FEF 0016 16 Port M control register PMCR R W H FFEF 0018 H 1FEF 0018 16 Port N control register PNCR R W H FFEF 001A H 1FEF 001A 16 Port O control re...

Page 1757: ...0056 8 Port M pull up control register PMPUPR R W H FFEF 0058 H 1FEF 0058 8 Port N pull up control register PNPUPR R W H FFEF 005A H 1FEF 005A 8 Port O pull up control register POPUPR R W H FFEF 005C H 1FEF 005C 8 Input pin pull up control register PPUPR R W H FFEF 0060 H 1FEF 0060 8 Pin select register 0 PSEL0 R W H FFEF 0070 H 1FEF 0070 16 Pin select register 1 PSEL1 R W H FFEF 0072 H 1FEF 0072 ...

Page 1758: ...ontrol register PLCR H 0000 Retained Retained Retained Port M control register PMCR H 0000 Retained Retained Retained Port N control register PNCR H 02AA Retained Retained Retained Port O control register POCR H 0FFF Retained Retained Retained Port A data register PADR H 00 Retained Retained Retained Port B data register PBDR H 00 Retained Retained Retained Port C data register PCDR H 00 Retained ...

Page 1759: ...d Retained Retained Pin select register 0 PSEL0 H 0008 Retained Retained Retained Pin select register 1 PSEL1 H 4888 Retained Retained Retained Pin select register 2 PSEL2 H 0000 Retained Retained Retained Pin select register 3 PSEL3 H 4444 Retained Retained Retained Pin select register 4 PSEL4 H 0000 Retained Retained Retained 40 2 1 Port A Control Register PACR PACR is a 16 bit readable writable...

Page 1760: ... 10 Port input MOS pull up Off 11 Setting prohibited 7 6 PA3MD 1 0 00 R W PTA3 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Setting prohibited 5 4 PA2MD 1 0 00 R W PTA2 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Setting prohibited 3 2 PA1MD 1 0 00 R W PTA1 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Setting prohibited...

Page 1761: ... 1 0 Bit Bit Name Initial value R W Description 15 14 PB7MD 1 0 00 R W PTB7 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Setting prohibited 13 12 PB6MD 1 0 00 R W PTB6 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Setting prohibited 11 10 PB5MD 1 0 00 R W PTB5 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Setting prohibite...

Page 1762: ...ode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Setting prohibited 40 2 3 Port C Control Register PCCR PCCR is a 16 bit readable writable register that selects the pin function 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W PC7MD 1 0 PC6MD 1 0 PC5MD 1 0 PC4MD 1 0 PC3MD...

Page 1763: ...t 10 Port input MOS pull up Off 11 Setting prohibited 9 8 PC4MD 1 0 00 R W PTC4 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Setting prohibited 7 6 PC3MD 1 0 00 R W PTC3 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Setting prohibited 5 4 PC2MD 1 0 00 R W PTC2 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Setting prohibite...

Page 1764: ... 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W PD7MD 1 0 PD6MD 1 0 PD5MD 1 0 PD4MD 1 0 PD3MD 1 0 PD2MD 1 0 PD1MD 1 0 PD0MD 1 0 Bit Bit Name Initial value R W Description 15 14 PD7MD 1 0 00 R W PTD7 Mode 00 Other function 01 Port output 10 Setting prohibited 11 Setting prohibited 13 12 PD6MD 1 0 00 R W PTD6 Mode 00 Other ...

Page 1765: ...3MD 1 0 00 R W PTD3 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Setting prohibited 5 4 PD2MD 1 0 00 R W PTD2 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Setting prohibited 3 2 PD1MD 1 0 00 R W PTD1 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Setting prohibited 1 0 PD0MD 1 0 00 R W PTD0 Mode 00 Other function 01 Port o...

Page 1766: ... 0 Bit Bit Name Initial value R W Description 15 12 All 0 R Reserved These bits are always read as 0 and the write value should always be 0 11 10 PE5MD 1 0 00 R W PTE5 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Setting prohibited 9 8 PE4MD 1 0 00 R W PTE4 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Setting prohibited 7 6 PE3MD 1 0 0 00 R W PTE...

Page 1767: ... prohibited 40 2 6 Port F Control Register PFCR PFCR is a 16 bit readable writable register that selects the pin function 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R W R W R W R W R W R W R W R W Bit Initial value R W PF3MD 1 0 PF2MD 1 0 PF1MD 1 0 PF0MD 1 0 Bit Bit Name Initial value R W Description 15 to 8 All 0 R Reserved These bits are always read as ...

Page 1768: ...2MD 1 0 00 R W PTF2 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Setting prohibited 3 2 PF1MD 1 0 00 R W PTF1 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Setting prohibited 1 0 PF0MD 1 0 00 R W PTF0 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Setting prohibited ...

Page 1769: ... 0 PG5MD 1 0 PG4MD 1 0 PG3MD 1 0 PG2MD 1 0 PG1MD 1 0 PG0MD 1 0 Bit Bit Name Initial value R W Description 15 14 PG7MD 1 0 00 R W PTG7 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Setting prohibited 13 12 PG6MD 1 0 00 R W PTG6 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Setting prohibited 11 10 PG5MD 1 0 00 R W PTG5 Mode 00 Other function 01 Port...

Page 1770: ...10 Port input MOS pull up Off 11 Setting prohibited 5 4 PG2MD 1 0 00 R W PTG2 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Setting prohibited 3 2 PG1MD 1 0 00 R W PTG1 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Setting prohibited 1 0 PG0MD 1 0 00 R W PTG0 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Setting prohibited ...

Page 1771: ... 1 0 PH5MD 1 0 PH4MD 1 0 PH3MD 1 0 PH2MD 1 0 PH1MD 1 0 PH0MD 1 0 Bit Bit Name Initial value R W Description 15 14 PH7MD 1 0 00 R W PH7 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Setting prohibited 13 12 PH6MD 1 0 00 R W PH6 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Setting prohibited 11 10 PH5MD 1 0 00 R W PH5 Mode 00 Other function 01 Port ...

Page 1772: ...10 Port input MOS pull up Off 11 Setting prohibited 5 4 PH2MD 1 0 00 R W PTH2 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Setting prohibited 3 2 PH1MD 1 0 00 R W PTH1 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Setting prohibited 1 0 PH0MD 1 0 00 R W PTH0 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Setting prohibited ...

Page 1773: ...ue R W PI7MD 1 0 PI6MD 1 0 PI5MD 1 0 PI4MD 1 0 PI3MD 1 0 PI2MD 1 0 PI1MD 1 0 PI0MD 1 0 Bit Bit Name Initial value R W Description 15 14 PI7MD 1 0 00 R W PTI7 Mode 00 Other function 01 Setting prohibited 10 Port input 11 Setting prohibited 13 12 PI6MD 1 0 00 R W PTI6 Mode 00 Other function 01 Setting prohibited 10 Port input 11 Setting prohibited 11 10 PI5MD 1 0 10 R W PTI5 Mode 00 Other function 0...

Page 1774: ...ohibited 10 Port input 11 Setting prohibited 5 4 PI2MD 1 0 10 R W PTI2 Mode 00 Other function 01 Setting prohibited 10 Port input 11 Setting prohibited 3 2 PI1MD 1 0 00 R W PTI1 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Port input MOS pull up On 1 0 PI0MD 1 0 00 R W PTI0 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Port input MOS pull up On ...

Page 1775: ... 1 0 PJ5MD 1 0 PJ4MD 1 0 PJ3MD 1 0 PJ2MD 1 0 PJ1MD 1 0 PJ0MD 1 0 Bit Bit Name Initial value R W Description 15 14 PJ7MD 1 0 11 R W PTJ7 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Port input MOS pull up On 13 12 PJ6MD 1 0 11 R W PTJ6 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Port input MOS pull up On 11 10 PJ5MD 1 0 11 R W PTJ5 Mode 00 Other ...

Page 1776: ...MOS pull up Off 11 Port input MOS pull up On 5 4 PJ2MD 1 0 11 R W PTJ2 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Port input MOS pull up On 3 2 PJ1MD 1 0 11 R W PTJ1 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Port input MOS pull up On 1 0 PJ0MD 1 0 11 R W PTJ0 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Port input M...

Page 1777: ... 1 0 PK5MD 1 0 PK4MD 1 0 PK3MD 1 0 PK2MD 1 0 PK1MD 1 0 PK0MD 1 0 Bit Bit Name Initial value R W Description 15 14 PK7MD 1 0 11 R W PTK7 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Port input MOS pull up On 13 12 PK6MD 1 0 11 R W PTK6 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Port input MOS pull up On 11 10 PK5MD 1 0 11 R W PTK5 Mode 00 Other ...

Page 1778: ...MOS pull up Off 11 Port input MOS pull up On 5 4 PK2MD 1 0 11 R W PTK2 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Port input MOS pull up On 3 2 PK1MD 1 0 11 R W PTK1 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Port input MOS pull up On 1 0 PK0MD 1 0 11 R W PTK0 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Port input M...

Page 1779: ... 1 0 PL5MD 1 0 PL4MD 1 0 PL3MD 1 0 PL2MD 1 0 PL1MD 1 0 PL0MD 1 0 Bit Bit Name Initial value R W Description 15 14 PL7MD 1 0 00 R W PTL7 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Port input MOS pull up On 13 12 PL6MD 1 0 00 R W PTL6 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Port input MOS pull up On 11 10 PL5MD 1 0 00 R W PTL5 Mode 00 Other ...

Page 1780: ...MOS pull up Off 11 Port input MOS pull up On 5 4 PL2MD 1 0 00 R W PTL2 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Port input MOS pull up On 3 2 PL1MD 1 0 00 R W PTL1 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Port input MOS pull up On 1 0 PL0MD 1 0 00 R W PTL0 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Port input M...

Page 1781: ... 1 0 PM5MD 1 0 PM4MD 1 0 PM3MD 1 0 PM2MD 1 0 PM1MD 1 0 PM0MD 1 0 Bit Bit Name Initial value R W Description 15 14 PM7MD 1 0 00 R W PTM7 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Port input MOS pull up On 13 12 PM6MD 1 0 00 R W PTM6 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Port input MOS pull up On 11 10 PM5MD 1 0 00 R W PTM5 Mode 00 Other ...

Page 1782: ...MOS pull up Off 11 Port input MOS pull up On 5 4 PM2MD 1 0 00 R W PTM2 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Port input MOS pull up On 3 2 PM1MD 1 0 00 R W PTM1 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Port input MOS pull up On 1 0 PM0MD 1 0 00 R W PTM0 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Port input M...

Page 1783: ...ial value R W PN5MD 1 0 PN4MD 1 0 PN3MD 1 0 PN2MD 1 0 PN1MD 1 0 PN0MD 1 0 Bit Bit Name Initial value R W Description 15 12 All 0 R Reserved These bits are always read as 0 and the write value should always be 0 11 10 PN5MD 1 0 00 R W PTN5 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Port input MOS pull up On 9 8 PN4MD 1 0 10 R W PTN4 Mode 00 Other function 01 Port output ...

Page 1784: ...2MD 1 0 10 R W PTN2 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Setting prohibited 3 2 PN1MD 1 0 10 R W PTN1 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Setting prohibited 1 0 PN0MD 1 0 10 R W PTN0 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Setting prohibited ...

Page 1785: ...0 PO6MD 1 0 PO5MD 1 0 PO4MD 1 0 PO3MD 1 0 PO2MD 1 0 PO1MD 1 0 PO0MD 1 0 Bit Bit Name Initial value R W Description 15 14 PO7MD 1 0 00 R W PTO7 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Setting prohibited 13 12 PO6MD 1 0 00 R W PTO6 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Setting prohibited 11 10 PO5MD 1 0 11 R W PTO5 Mode 00 Other functio...

Page 1786: ...MOS pull up Off 11 Port input MOS pull up On 5 4 PO2MD 1 0 11 R W PTO2 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Port input MOS pull up On 3 2 PO1MD 1 0 11 R W PTO1 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Port input MOS pull up On 1 0 PO0MD 1 0 11 R W PTO0 Mode 00 Other function 01 Port output 10 Port input MOS pull up Off 11 Port input M...

Page 1787: ...itial value R W Description 7 0 R Reserved This bit is always read as 0 The write value should always be 0 6 PA6DT 0 R W 5 PA5DT 0 R W 4 PA4DT 0 R W 3 PA3DT 0 R W 2 PA2DT 0 R W 1 PA1DT 0 R W 0 PA0DT 0 R W Each of these bits stores output data for the corresponding pin that is used as a general output port If the port is read the value of the corresponding bit in this register will be read for a pi...

Page 1788: ...DT PB2DT PB1DT PB0DT Bit Bit Name Initial value R W Description 7 PB7DT 0 R W 6 PB6DT 0 R W 5 PB5DT 0 R W 4 PB4DT 0 R W 3 PB3DT 0 R W 2 PB2DT 0 R W 1 PB1DT 0 R W 0 PB0DT 0 R W Each of these bits stores output data for the corresponding pin that is used as a general output port If the port is read the value of the corresponding bit in this register will be read for a pin configured as a general out...

Page 1789: ...DT PC2DT PC1DT PC0DT Bit Bit Name Initial value R W Description 7 PC7DT 0 R W 6 PC6DT 0 R W 5 PC5DT 0 R W 4 PC4DT 0 R W 3 PC3DT 0 R W 2 PC2DT 0 R W 1 PC1DT 0 R W 0 PC0DT 0 R W Each of these bits stores output data for the corresponding pin that is used as a general output port If the port is read the value of the corresponding bit in this register will be read for a pin configured as a general out...

Page 1790: ...DT PD2DT PD1DT PD0DT Bit Bit Name Initial value R W Description 7 PD7DT 0 R W 6 PD6DT 0 R W 5 PD5DT 0 R W 4 PD4DT 0 R W 3 PD3DT 0 R W 2 PD2DT 0 R W 1 PD1DT 0 R W 0 PD0DT 0 R W Each of these bits stores output data for the corresponding pin that is used as a general output port If the port is read the value of the corresponding bit in this register will be read for a pin configured as a general out...

Page 1791: ...al value R W Description 7 6 All0 R Reserved These bits are always read as 0 and the write value should always be 0 5 PE5DT 0 R W 4 PE4DT 0 R W 3 PE3DT 0 R W 2 PE2DT 0 R W 1 PE1DT 0 R W 0 PE0DT 0 R W Each of these bits stores output data for the corresponding pin that is used as a general output port If the port is read the value of the corresponding bit in this register will be read for a pin con...

Page 1792: ...nitial value R W Description 7 to 4 All0 R Reserved These bits are always read as 0 and the write value should always be 0 3 PF3DT 0 R W 2 PF2DT 0 R W 1 PF1DT 0 R W 0 PF0DT 0 R W Each of these bits stores output data for the corresponding pin that is used as a general output port If the port is read the value of the corresponding bit in this register will be read for a pin configured as a general ...

Page 1793: ...DT PG2DT PG1DT PG0DT Bit Bit Name Initial value R W Description 7 PG7DT 0 R W 6 PG6DT 0 R W 5 PG5DT 0 R W 4 PG4DT 0 R W 3 PG3DT 0 R W 2 PG2DT 0 R W 1 PG1DT 0 R W 0 PG0DT 0 R W Each of these bits stores output data for the corresponding pin that is used as a general output port If the port is read the value of the corresponding bit in this register will be read for a pin configured as a general out...

Page 1794: ...DT PH2DT PH1DT PH0DT Bit Bit Name Initial value R W Description 7 PH7DT 0 R W 6 PH6DT 0 R W 5 PH5DT 0 R W 4 PH4DT 0 R W 3 PH3DT 0 R W 2 PH2DT 0 R W 1 PH1DT 0 R W 0 PH0DT 0 R W Each of these bits stores output data for the corresponding pin that is used as a general output port If the port is read the value of the corresponding bit in this register will be read for a pin configured as a general out...

Page 1795: ...DT PI2DT PI1DT PI0DT Bit Bit Name Initial value R W Description 7 PI7DT 0 R 6 PI6DT 0 R 5 PI5DT Pin state R W 4 PI4DT Pin state R W 3 PI3DT Pin state R 2 PI2DT Pin state R 1 PI1DT 0 R W 0 PI0DT 0 R W Each of these bits stores output data for the corresponding pin that is used as a general output port If the port is read the value of the corresponding bit in this register will be read for a pin con...

Page 1796: ...DT PJ2DT PJ1DT PJ0DT Bit Bit Name Initial value R W Description 7 PJ7DT Pin state R W 6 PJ6DT Pin state R W 5 PJ5DT Pin state R W 4 PJ4DT Pin state R W 3 PJ3DT Pin state R W 2 PJ2DT Pin state R W 1 PJ1DT Pin state R W 0 PJ0DT Pin state R W Each of these bits stores output data for the corresponding pin that is used as a general output port If the port is read the value of the corresponding bit in ...

Page 1797: ...DT PK2DT PK1DT PK0DT Bit Bit Name Initial value R W Description 7 PK7DT Pin state R W 6 PK6DT Pin state R W 5 PK5DT Pin state R W 4 PK4DT Pin state R W 3 PK3DT Pin state R W 2 PK2DT Pin state R W 1 PK1DT Pin state R W 0 PK0DT Pin state R W Each of these bits stores output data for the corresponding pin that is used as a general output port If the port is read the value of the corresponding bit in ...

Page 1798: ...DT PL2DT PL1DT PL0DT Bit Bit Name Initial value R W Description 7 PL7DT 0 R W 6 PL6DT 0 R W 5 PL5DT 0 R W 4 PL4DT 0 R W 3 PL3DT 0 R W 2 PL2DT 0 R W 1 PL1DT 0 R W 0 PL0DT 0 R W Each of these bits stores output data for the corresponding pin that is used as a general output port If the port is read the value of the corresponding bit in this register will be read for a pin configured as a general out...

Page 1799: ...DT PM2DT PM1DT PM0DT Bit Bit Name Initial value R W Description 7 PM7DT 0 R W 6 PM6DT 0 R W 5 PM5DT 0 R W 4 PM4DT 0 R W 3 PM3DT 0 R W 2 PM2DT 0 R W 1 PM1DT 0 R W 0 PM0DT 0 R W Each of these bits stores output data for the corresponding pin that is used as a general output port If the port is read the value of the corresponding bit in this register will be read for a pin configured as a general out...

Page 1800: ...al value R W Description 7 6 All0 R Reserved These bits are always read as 0 and the write value should always be 0 5 PN5DT 0 R W 4 PN4DT Pin state R W 3 PN3DT Pin state R W 2 PN2DT Pin state R W 1 PN1DT Pin state R W 0 PN0DT Pin state R W Each of these bits stores output data for the corresponding pin that is used as a general output port If the port is read the value of the corresponding bit in ...

Page 1801: ...DT PO2DT PO1DT PO0DT Bit Bit Name Initial value R W Description 7 PO7DT 0 R W 6 PO6DT 0 R W 5 PO5DT Pin state R W 4 PO4DT Pin state R W 3 PO3DT Pin state R W 2 PO2DT Pin state R W 1 PO1DT Pin state R W 0 PO0DT Pin state R W Each of these bits stores output data for the corresponding pin that is used as a general output port If the port is read the value of the corresponding bit in this register wi...

Page 1802: ... individual pins The settings in this register are invalid for the pins specified to function as port pins by PICR 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 R R R R R R R W R W Bit Initial value R W PI1PUPR PI0PUPR Bit Bit Name Initial value R W Description 7 to 2 All 1 R Reserved These bits are always read as 1 and the write value should always be 1 1 PI1PUPR 1 R W Controls pull up of the PTI1 pin 0 PTI1 p...

Page 1803: ...PJ5PUPR PJ4PUPR PJ3PUPR PJ2PUPR PJ1PUPR PJ0PUPR Bit Bit Name Initial value R W Description 7 PJ7PUPR 1 R W Controls pull up of the PTJ7 pin 0 PTJ7 pin pull up off 1 PTJ7 pin pull up on 6 PJ6PUPR 1 R W Controls pull up of the PTJ6 pin 0 PTJ6 pin pull up off 1 PTJ6 pin pull up on 5 PJ5PUPR 1 R W Controls pull up of the PTJ5 pin 0 PTJ5 pin pull up off 1 PTJ5 pin pull up on 4 PJ4PUPR 1 R W Controls pu...

Page 1804: ...alid for the pins specified to function as port pins by PKCR 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W Bit Initial value R W PK7PUPRPK6PUPR PK5PUPR PK4PUPR PK3PUPR PK2PUPR PK1PUPR PK0PUPR Bit Bit Name Initial value R W Description 7 PK7PUPR 1 R W Controls pull up of the PTK7 pin 0 PTK7 pin pull up off 1 PTK7 pin pull up on 6 PK6PUPR 1 R W Controls pull up of the PTK6 pin 0 PT...

Page 1805: ...this register corresponds to PTL7 to PTL0 and when the pins of Port L are used by other function pull up control is performed for the individual pins The settings in this register are invalid for the pins specified to function as port pins by PLCR 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W Bit Initial value R W PL7PUPR PL6PUPR PL5PUPR PL4PUPR PL3PUPR PL2PUPR PL1PUPR PL0PUPR Bi...

Page 1806: ...the PTL1 pin 0 PTL1 pin pull up off 1 PTL1 pin pull up on 0 PL0PUPR 1 R W Controls pull up of the PTL0 pin 0 PTL0 pin pull up off 1 PTL0 pin pull up on 40 2 35 Port M Pull Up Control Register PMPUPR PMPUPR is an 8 bit readable writable register Each bit of this register corresponds to PTM7 to PTM0 and when the pins of Port M are used by other function pull up control is performed for the individua...

Page 1807: ...rols pull up of the PTM5 pin 0 PTM5 pin pull up off 1 PTM5 pin pull up on 4 PM4PUPR 1 R W Controls pull up of the PTM4 pin 0 PTM4 pin pull up off 1 PTM4 pin pull up on 3 PM3PUPR 1 R W Controls pull up of the PTM3 pin 0 PTM3 pin pull up off 1 PTM3 pin pull up on 2 PM2PUPR 1 R W Controls pull up of the PTM2 pin 0 PTM2 pin pull up off 1 PTM2 pin pull up on 1 PM1PUPR 1 R W Controls pull up of the PTM1...

Page 1808: ...or the individual pins The settings in this register are invalid for the pins specified to function as port pins by PNCR 7 6 5 4 3 2 1 0 Bit Initial value R W 1 1 1 1 1 1 1 1 R R R W R R R R R PN5PUPR Bit Bit Name Initial value R W Description 7 6 All 1 R Reserved These bits are always read as 1 and the write value should always be 1 5 PN5PUPR 1 R W Controls pull up of the PTN5 pin 0 PTN5 pin pull...

Page 1809: ...PO4PUPRPO3PUPRPO2PUPRPO1PUPRPO0PUPR Bit Bit Name Initial value R W Description 7 6 All 1 R Reserved These bits are always read as 1 and the write value should always be 1 5 PO5PUPR 1 R W Controls pull up of the PTO5 pin 0 PTO5 pin pull up off 1 PTO5 pin pull up on 4 PO4PUPR 1 R W Controls pull up of the PTO4 pin 0 PTO4 pin pull up off 1 PTO4 pin pull up on 3 PO3PUPR 1 R W Controls pull up of the P...

Page 1810: ... 1 1 1 1 1 R R R R R R R W R W IOIS16UPBREQPUP RDYPUP Bit Bit Name Initial value R W Description 7 to 3 All 1 R Reserved These bits are always read as 1 and the write value should always be 1 2 IOIS16UP 1 R W Controls pull up of the IOIS16 pin 0 IOIS16 pin pull up off 1 IOIS16 pin pull up on 1 BREQPUP 1 R W Controls pull up of the BREQ pin 0 BREQ pin pull up off 1 BREQ pin pull up on 0 RDYPUP 1 R ...

Page 1811: ... 0 0 0 0 1 0 0 0 R R R R R R R R R R R R W R W R W R W R W Bit Initial value R W PTSEL0 4 0 Bit Bit Name Initial value R W Description 15 to 5 All 0 R Reserved These bits are always read as 0 and the write value should always be 0 4 to 0 PTSEL0 4 0 01000 R W These bits select the functions of Port A PTA Port B PTB and Port C PTC Bit setting Selected function PTSEL0 4 0 PTA PTB PTC 01xxx PCIC PCIC ...

Page 1812: ...0 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 R R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W PTSEL1 3 0 PTSEL1 7 4 PTSEL1 11 8 PTSEL1 14 12 Bit Bit Name Initial value R W Description 15 0 R Reserved This bit is always read as 0 and the write value should always be 0 14 to 12 PTSEL1 14 12 100 R W These bits select the function of Port H PTH Bit setting S...

Page 1813: ... When clearing interrupt mask of the interrupt controller INTC with the PCIC function selected make sure to select the PCIC function with this register in advance 7 to 4 PTSEL1 7 4 1000 R W These bits select the functions of Port E PTE Bit setting Selected function PTSEL1 7 4 PTE 1xxx PCIC 0000 GMII1 0010 DMAC2 SCIF2 0011 DMAC2 SSI0 0100 PCC SCIF2 0101 PCC SSI0 Other than above Setting prohibited ...

Page 1814: ...lect the functions of Port D PTD Bit setting Selected function PTSEL1 3 0 PTD 1xxx PCIC 0000 GMII1 SIOF0 0001 LCDCM 0010 PCC 0100 HAC SSI1 0101 HAC GMII1 Other than above Setting prohibited Legend x Don t care Note When clearing interrupt mask of the interrupt controller INTC with the PCIC function selected make sure to select the PCIC function with this register in advance ...

Page 1815: ...gister to select other function 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W PTSEL2 14 12 PTSEL2 11 8 PTSEL2 7 6 PTSEL2 5 4 PTSEL2 3 2 PTSEL2 1 0 Bit Bit Name Initial value R W Description 15 0 R Reserved This bit is always read as 0 and the write value should always be 0 14 to 12 PTSEL2 14...

Page 1816: ...M Other than above Setting prohibited Note When clearing interrupt mask of the interrupt controller INTC with the PCIC function selected make sure to select the PCIC function with this register in advance 7 6 PTSEL2 7 6 All 0 R W These bits select the functions of Port J PTJ0 Bit setting Selected function PTSEL2 7 6 PTJ0 00 REF50CK 01 GMII0 10 STIF0M Other than above Setting prohibited 5 4 PTSEL2 ...

Page 1817: ... 3 2 PTSEL2 3 2 All 0 R W These bits select the functions of Port I PTI3 PTI2 Bit setting Selected function PTSEL2 3 2 PTI3 PTI2 00 USB 01 STIF0M 10 SIOF1 11 IIC0 1 0 PTSEL2 1 0 All 0 R W These bits select the functions of Port I PTI1 PTI0 Bit setting Selected function PTSEL2 1 0 PTI1 PTI0 00 SYS 01 STIF1 1x RMII0 Legend x Don t care ...

Page 1818: ...TSEL3 6 4 PTSEL3 2 0 Bit Bit Name Initial value R W Description 15 0 R Reserved This bit is always read as 0 and the write value should always be 0 14 to 12 PTSEL3 14 12 100 R W These bits select the functions of Port L PTL7 to PTL4 and Port M PTM7 to PTM1 Bit setting Selected function PTSEL3 14 12 PTL7 to PTL4 PTM7 to PTM1 1xx LBSC 1 EXCPU LBSC 1 EXCPU 000 LCDC RMII0 001 MII0 MII0 010 DMAC1 PCIC ...

Page 1819: ... 0 R Reserved This bit is always read as 0 and the write value should always be 0 6 to 4 PTSEL3 6 4 100 R W These bits select the function of Port L PTL3 Bit setting Selected function PTSEL3 6 4 PTL3 1xx LBSC 1 EXCPU 000 LCDC 001 PCIC 2 010 IRQ7 011 MII0 Legend x Don t care Notes 1 When 32 bit is selected as the data bus width in the LBSC select this pin function 2 When clearing interrupt mask of ...

Page 1820: ...alue R W Description 2 to 0 PTSEL3 2 0 100 R W These bits select the functions of Port L PTL2 to PTL0 Bit setting Selected function PTSEL3 2 0 PTL2 to PTL0 1xx LBSC EXCPU 000 LCDC 001 DMAC0 010 INT 011 MII0 Legend x Don t care Note When 32 bit is selected as the data bus width in the LBSC select this pin function ...

Page 1821: ...W R R W R W R W R W R W R W R W Bit Initial value R W PTSEL4F PTSEL4E PTSEL4D PTSEL4B PTSEL4 10 9 PTSEL4 5 4 PTSEL4 3 2 PTSEL4 1 0 PTSEL48 PTSEL46 Bit Bit Name Initial value R W Description 15 PTSEL4F 0 R W Selects the function of the IOIS16 TCLK pin 0 IOIS16 function is selected 1 TCLK function is selected When the IOIS16 function is selected this bit should be set to the initial value Do not sel...

Page 1822: ...sed as ET0_ MDIO only PTL3 can be used when using GMII0 and MII0 01 Input from PTI1 is used as RMII0_ MDIO 10 Input from PTM0 is used as RMII0_ MDIO 11 Input from PTO3 is used as RMII0_ MDIO 8 PTSEL48 0 R W Selects the pin for MDIO1 0 Input from PTF2 is used as ET1_ MDIO only PTF2 can be used when using GMII1 and MII1 1 Input from PTO1 is used as ET1_ MDIO 7 0 R Reserved This bit is always read as...

Page 1823: ...EL4 5 4 PTI7 PTI6 00 INT 01 IIC1 11 STIF0M Other than above Setting prohibited 3 2 PTSEL4 3 2 00 R W These bits select the function of Port O PTO3 to PTO0 Bit setting Selected function PTSEL4 3 2 PTO3 to PTO0 00 AUD 01 SSI2 1x RMII0M1 RMII1M Legend x Don t care 1 0 PTSEL4 1 0 00 R W These bits select the function of Port O PTO7 to PTO4 Bit setting Selected function PTSEL4 1 0 PTO7 to PTO4 00 AUD I...

Page 1824: ...l up to the corresponding two bits in the port control register PACR to PPCR This allows the value of that pin to be read from the corresponding bit in the port data register PADR to PPDR Note that settings in the pull up control register PAPUPR to PPPUPR and pin select register PSEL0 to PSEL4 are invalid for the pins configured for the port output function 40 3 3 Peripheral Module Function To set...

Page 1825: ...reak Sequential break involves two cases such that the channel 0 break condition is satisfied in a certain bus cycle and then the channel 1 break condition is satisfied in a different bus cycle and vice versa Address When 40 bits containing ASID and 32 bit address are compared with the specified value all the ASID bits can be compared or masked 32 bit address can be masked bit by bit allowing the ...

Page 1826: ...BR0 CRR0 CAR0 CAMR0 CBR1 CRR1 CAR1 CAMR1 CDR1 CDMR1 CETR1 CCMFR CBCR SAB SDB Legend ASID comparator ASID comparator ASID Match condition setting register 0 Match operation setting register 0 Match address setting register 0 Match address mask setting register 0 Match condition setting register 1 Match operation setting register 1 Match address setting register 1 Match address mask setting register...

Page 1827: ... 1 CBR1 R W H FF200020 H 1F200020 32 Match operation setting register 1 CRR1 R W H FF200024 H 1F200024 32 Match address setting register 1 CAR1 R W H FF200028 H 1F200028 32 Match address mask setting register 1 CAMR1 R W H FF20002C H 1F20002C 32 Match data setting register 1 CDR1 R W H FF200030 H 1F200030 32 Match data mask setting register 1 CDMR1 R W H FF200034 H 1F200034 32 Execution count brea...

Page 1828: ...r 1 CAMR1 Undefined Retained Retained Retained Match data setting register 1 CDR1 Undefined Retained Retained Retained Match data mask setting register 1 CDMR1 Undefined Retained Retained Retained Execution count break register 1 CETR1 Undefined Retained Retained Retained Channel match flag register CCMFR H 00000000 Retained Retained Retained Break control register CBCR H 00000000 Retained Retaine...

Page 1829: ... 0 0 0 0 0 0 0 0 0 MFE AIE MFI AIV SZ CD ID RW CE R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R W R W R W R R R R R W R W R W R W R R W R W R W Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 MFE 0 R W Match Flag Enable Specifies whether or not to include the match ...

Page 1830: ...0 in the condition of CCRMF MF0 0 23 to 16 AIV All 0 R W ASID Specify Specifies the ASID value to be included in the match conditions 15 0 R Reserved For read write in this bit refer to General Precautions on Handling of Product 14 to 12 SZ All 0 R W Operand Size Select Specifies the operand size to be included in the match conditions This bit is valid only when the operand access cycle is specifi...

Page 1831: ... Reserved For read write in this bit refer to General Precautions on Handling of Product 2 1 RW All 0 R W Bus Command Select Specifies the read write cycle as the match condition This bit is valid only when the operand access cycle is specified as a match condition 00 Read cycle or write cycle 01 Read cycle 10 Write cycle 11 Read cycle or write cycle 0 CE 0 R W Channel Enable Validates invalidates...

Page 1832: ...the condition is determined to be satisfied 0 The match flag is not included in the match conditions thus not checked 1 The match flag is included in the match conditions 30 AIE 0 R W ASID Enable Specifies whether or not to include the ASID specified by the AIV bit of this register in the match conditions 0 The ASID is not included in the match conditions thus not checked 1 The ASID is included in...

Page 1833: ...s bit is valid only when the operand access cycle is specified as a match condition 000 The operand size is not included in the match condition thus not checked any operand size specifies the match condition 1 001 Byte access 010 Word access 011 Longword access 100 Quadword access 2 Others Reserved setting prohibited 11 ETBE 0 R W Execution Count Value Enable Specifies whether or not to include th...

Page 1834: ...erand Access Select Specifies the instruction fetch cycle or operand access cycle as the match condition 00 Instruction fetch cycle or operand access cycle 01 Instruction fetch cycle 10 Operand access cycle 11 Instruction fetch cycle or operand access cycle 3 0 R Reserved For read write in this bit refer to General Precautions on Handling of Product 2 1 RW All 0 R W Bus Command Select Specifies th...

Page 1835: ...ditions be sure to specify the operand size 2 If the quadword access is specified and the data value is included in the match conditions the upper and lower 32 bits of 64 bit data are each compared with the contents of both the match data setting register and the match data mask setting register 3 The OCBI instruction is handled as longword write access without the data value and the PREF OCBP and...

Page 1836: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R W R W Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 14 All 0 R Reserved For read write in this bit refer to General Precautions on Handling of Product 13 1 R Reserved This bit is always read as 1 The write value should always be 1 12 to 2 All 0 R Reserv...

Page 1837: ... R R R R R R R R R W R W Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 14 All 0 R Reserved For read write in this bit refer to General Precautions on Handling of Product 13 1 R Reserved This bit is always read as 1 The write value should always be 1 12 to 2 All 0 R Reserved For read write in this bit refer to General Precautions on Handling of Product...

Page 1838: ...s specifying the virtual address to be included in the break conditions for channels 0 and 1 respectively CAR0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CA CA R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Valu...

Page 1839: ...W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 0 CA Undefined R W Compare Address Specifies the address to be included in the break conditions When the operand bus has been specified using the CBR1 register specify the SAB address in CA 3...

Page 1840: ...24 23 22 21 20 19 18 17 16 CAM CAM R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 0 CAM Undefined R W Compare Address Mask Specifies the bits to be masked among the address bits which are ...

Page 1841: ... R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 0 CAM Undefined R W Compare Address Mask Specifies the bits to be masked among the address bits which are specified using the CAR1 register Set the bits to be masked to 1 0 Address bits CA n are included in the break condition 1 Address bits CA n are mas...

Page 1842: ...ta value in CD 31 0 Table 41 3 Settings for Match Data Setting Register Bus and Size Selected Using CBR1 CD 31 24 CD 23 16 CD 15 8 CD 7 0 Operand bus byte Don t care Don t care Don t care SDB7 to SDB0 Operand bus word Don t care Don t care SDB15 to SDB8 SDB7 to SDB0 Operand bus longword SDB31 to SDB24 SDB23 to SDB16 SDB15 to SDB8 SDB7 to SDB0 Notes 1 If the data value is included in the match cond...

Page 1843: ... R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 0 CDM Undefined R W Compare Data Value Mask Specifies the bits to be masked among the data value bits specified using the CDR1 register Set ...

Page 1844: ...emented by one every time the channel is hit When the channel is hit after the register value reaches H 001 a break occurs 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CET R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 R R R R R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W Bit Initial value R W Bit Bit Name In...

Page 1845: ...6 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MF1 MF0 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R W R W Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 2 All 0 R Reserved For read write in this bit refer to General Precautions on Handling of Product...

Page 1846: ...8 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBDE R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R W Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 1 All 0 R Reserved For read write in this bit refer to General Precautions on Handling of Product 0 UBDE 0 R W User Break Debu...

Page 1847: ...sed in contrast to address All types of operand access are classified into read or write access Special care must be taken in using the following instructions PREF OCBP and OCBWB Instructions for a read access MOVCA L and OCBI Instructions for a write access TAS B Instruction for a single read access or a single write access The operand access accompanying the PREF OCBP OCBWB and OCBI instructions...

Page 1848: ...atch condition is satisfied as a result of fetching the instruction using the match operation setting register CRR0 or CRR1 After having set all the bits in the match condition setting register except the CE bit and the other necessary registers set the CE bit and read the match condition setting register again This ensures that the set values in the control registers are valid for the subsequent ...

Page 1849: ...to be satisfied the corresponding condition match flag is set 7 If the sequential break conditions are set the condition match flag is set every time the match conditions are satisfied for each channel When the conditions have been satisfied for the first channel in the sequence but not for the second channel in the sequence clear the condition match flag for the first channel in the sequence in o...

Page 1850: ...tion break and the other exceptions refer to section 5 Exception Handling If pre instruction execution break is specified for the delayed slot of the delayed branch instruction the break is requested before the delayed branch instruction is executed However do not specify pre instruction execution break for the delayed slot of the RTE instruction 3 If post instruction execution break is specified ...

Page 1851: ...e following access cycles assuming that all the other conditions are satisfied Longword access to address H 00001000 Word access to address H 00001002 Byte access to address H 00001003 2 When the data value is included in the channel 1 match conditions If the data value is included in the match conditions be sure to select the quadword longword word or byte as the operand size using the operand si...

Page 1852: ...ting the next instruction However if the data value is included in the match conditions a break may occur after executing several instructions after the instruction which has satisfied the conditions therefore it is impossible to identify the instruction causing the break If such a break has occurred for the delayed branch instruction or its delayed slot the break does not occur until the first in...

Page 1853: ... the first channel in the sequence in order to release the first channel in the sequence from the match state 2 For channel 1 the execution count break condition can also be included in the sequential break conditions 3 If the match conditions for the first and second channels in the sequence are satisfied within a significantly short time sequential operation may not be guaranteed in some cases a...

Page 1854: ...estarts is saved in the SPC then the exception handling state is initiated A unique instruction causing a break can be identified unless the data value is included in the match conditions 1 When the instruction fetch cycle before instruction execution is specified as the match condition The address of the instruction which has satisfied the match conditions is saved in the SPC The instruction whic...

Page 1855: ... instructions after the instruction which has satisfied the match conditions The address of the instruction is saved in the SPC thus it is impossible to identify exactly where a break will occur If the conditions are satisfied for the delayed slot instruction the address of the branch destination is saved in the SPC If a branch instruction follows the instruction which has satisfied the match cond...

Page 1856: ... Trap Interrupt PC H A000 0000 PC VBR vector offset Execute RTE instruction PC SPC SR SSR SGR R15 PC DBR Debugging program R15 SGR STC instruction Reset exception CBCR UBDE 1 user break Exception operation ends INTEVT Interrupt code EXPEVT Exception code Yes No No Yes Hardware operations Exception handling routine TRA TRAPA imm EXPEVT H 160 Figure 41 2 Flowchart of User Break Debugging Support Fun...

Page 1857: ...uction fetch before executing instruction ASID data values and execution count are not included in the conditions With the above settings the user break occurs after executing the instruction at address H 00000404 or before executing the instruction at address H 00008010 to H 00008016 Example 1 2 Register settings CBR0 H 40800013 CRR0 H 00002000 CAR0 H 00037226 CAMR0 H 00000000 CBR1 H C0700013 CRR...

Page 1858: ...unt H 00000000 Bus cycle Instruction fetch before executing the instruction ASID data values and execution count are not included in the conditions With the above settings the user break occurs for channel 0 before executing the instruction at address H 00027128 No user break occurs for channel 1 since the instruction fetch is executed only at even addresses Example 1 4 Register settings CBR0 H 40...

Page 1859: ... Execution count H 00000005 Bus cycle Instruction fetch before executing the instruction Execution count 5 ASID and data values are not included in the conditions With the above settings the user break occurs for channel 0 before executing the instruction at address H 00000500 The user break occurs for channel 1 after executing the instruction at address H 00001000 four times before executing the ...

Page 1860: ...00000000 CETR1 H 00000000 CBCR H 00000000 Specified conditions Independent for channels 0 and 1 Channel 0 Address H 00123456 Address mask H 00000000 ASID H 80 Bus cycle Operand bus operand access and read operand size is not included in the conditions Channel 1 Address H 000ABCDE Address mask H 000000FF ASID H 70 Data H 0000A512 Data mask H 00000000 Execution count H 00000000 Bus cycle Operand bus...

Page 1861: ...ers is not necessary At only last updating the UBC register execute one of these methods 2 The PCB bit of the CRR0 and CRR1 registers is valid only when the instruction fetch is specified as the match condition 3 If the sequential break conditions are set the sequential break conditions are satisfied when the conditions for the first and second channels in the sequence are satisfied in this order ...

Page 1862: ... independently for channels 0 and 1 resulting in identical SPC values for both of the breaks the user break occurs only once However the condition match flags are set for both channels For example Instruction at address 110 post instruction execution break for instruction fetch for channel 0 SPC 112 CCMFR MF0 1 Instruction at address 112 pre instruction execution break for instruction fetch for ch...

Page 1863: ...re multiplexed with on chip modules And the H UDI has one chip mode setting pin MPMD The H UDI has two TAP controller blocks one is for the boundary scan test and another is H UDI function except the boundary scan test The H UDI initial state is for the boundary scan after power on or TRST asserted It is necessary to set H UDI switchover command to use the H UDI function And the CPU cannot access ...

Page 1864: ...TDO TDI TMS TRST Shift register Pin multiplexer TAP controller Decoder Peripheral bus SDINT Break controller Interrupt reset etc ASEBRK BRKACK Legend SDBPR Bypass register SDBSR Boundary scan register SDINT Interrupt source register SDIR Instruction register Boundary scan TAP controller Figure 42 1 H UDI Block Diagram ...

Page 1865: ... should be asserted for a given period regardless of whether or not the JTAG function is used which differs from the JTAG standard Fixed to ground or connected to the PRESET pin 3 TDI Data input Input Data Input Data is sent to the H UDI by changing this signal in synchronization with the TCK signal Open 1 TDO Data output Output Data Output Data is read from the H UDI in synchronization with the T...

Page 1866: ...e H UDI reset and interrupt functions Assertion of TRST for example at power on reset activates the boundary scan TAP controller and enables the boundary scan function prescribed in the JTAG standards Executing a switchover command to the H UDI allows usage of the H UDI reset and H UDI interrupts This LSI however has the following limitations Clock related pins EXTAL XTAL EXTAL2 and XTAL2 are out ...

Page 1867: ...t1 IR Update IR Run Test Idle Test Logic Reset Select DR Select IR Capture IR Shift IR Test Logic Reset Run Test Idle Test Logic Reset Run Test Idle Shift IR TCK TMS TRST TDI H UDI Run Test Idle TRST is asserted H UDI select command is input to boundary scan TAP controller H UDI is used TRST is asserted Boundary scan TAP controller External pins H UDI selection Status Status H UDI select command B...

Page 1868: ...B 2 The low level of the TRST pin or the Test Logic Reset state of the TAP controller initializes to these values Table 42 4 Register Configuration 2 H UDI Side Register Name Abbrev R W Size Initial Value 1 Instruction register SDIR R W 32 H FFFF FFFD fixed value 2 Interrupt source register SDINT W 3 32 H 0000 0000 Boundary scan register SDBSR Bypass register SDBPR R W 1 Undefined Note 1 The low l...

Page 1869: ...guaranteed when a reserved command is set to this register TI Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 0 1 1 1 1 1 1 1 1 R R R R R R R R R R R R R R R R Bit Bit Name Initial Value R W Description 15 to 8 TI 0000 1110 R Test Instruction Bits 7 to 0 0110 xxxx H UDI reset negate 0111 xxxx H UDI reset assert 101x xxxx H UDI interrupt 0000 1110 Initial state Other than ...

Page 1870: ...he INTREQ bit by the CPU While this bit is set to 1 an interrupt request will continue to be generated This bit therefore should be cleared by the interrupt handling routine It is initialized by TRST or in the Test Logic Reset state INTREQ Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R W Bit Bit Name Initial Value R W Des...

Page 1871: ...gh this register is not initialized by a power on reset and the TRST pin asserted initialized to 0 in the Capture DR state 42 4 4 Boundary Scan Register SDBSR SDBSR is a shift register located on the PAD for controlling the input Output pins which supports the boundary scan mode of the JTAG standard Using the EXTEST and SAMPLE PRELOAD commands a boundary scan test complying with the JTAG standards...

Page 1872: ...S16 TMU_TCLK OUTPUT 510 IOIS16 TMU_TCLK CONTROL 509 IOIS16 TMU_TCLK INPUT 508 CE2A OUTPUT 507 CE2A CONTROL 506 CE2A INPUT 505 CE2B OUTPUT 504 CE2B CONTROL 503 CE2B INPUT 502 A25 EX_SIZE2 OUTPUT 501 A25 EX_SIZE2 CONTROL 500 A25 EX_SIZE2 INPUT 499 A24 EX_SIZE1 OUTPUT 498 A24 EX_SIZE1 CONTROL 497 A24 EX_SIZE1 INPUT 496 A23 EX_SIZE0 OUTPUT 495 A23 EX_SIZE0 CONTROL 494 A23 EX_SIZE0 INPUT 493 A22 OUTPUT...

Page 1873: ...A15 CONTROL 482 A15 INPUT 481 A14 OUTPUT 480 A14 CONTROL 479 A14 INPUT 478 A19 OUTPUT 477 A19 CONTROL 476 A19 INPUT 475 A18 OUTPUT 474 A18 CONTROL 473 A18 INPUT 472 A13 OUTPUT 471 A13 CONTROL 470 A13 INPUT 469 A12 OUTPUT 468 A12 CONTROL 467 A12 INPUT 466 A17 OUTPUT 465 A17 CONTROL 464 A17 INPUT 463 A16 OUTPUT 462 A16 CONTROL 461 A16 INPUT 460 A7 OUTPUT 459 A7 CONTROL 458 A7 INPUT 457 A6 OUTPUT ...

Page 1874: ...INPUT 451 A10 OUTPUT 450 A10 CONTROL 449 A10 INPUT 448 A5 OUTPUT 447 A5 CONTROL 446 A5 INPUT 445 A4 OUTPUT 444 A4 CONTROL 443 A4 INPUT 442 A9 OUTPUT 441 A9 CONTROL 440 A9 INPUT 439 A8 OUTPUT 438 A8 CONTROL 437 A8 INPUT 436 A3 OUTPUT 435 A3 CONTROL 434 A3 INPUT 433 A2 OUTPUT 432 A2 CONTROL 431 A2 INPUT 430 A1 OUTPUT 429 A1 CONTROL 428 A1 INPUT 427 A0 OUTPUT 426 A0 CONTROL 425 A0 INPUT ...

Page 1875: ...EX_AD1 CONTROL 416 D1 EX_AD1 INPUT 415 D0 EX_AD0 OUTPUT 414 D0 EX_AD0 CONTROL 413 D0 EX_AD0 INPUT 412 WE1 WE OUTPUT 411 WE1 WE CONTROL 410 WE1 WE INPUT 409 CLKOUT CONTROL 408 CLKOUT OUTPUT 407 D3 EX_AD3 OUTPUT 406 D3 EX_AD3 CONTROL 405 D3 EX_AD3 INPUT 404 D2 EX_AD2 OUTPUT 403 D2 EX_AD2 CONTROL 402 D2 EX_AD2 INPUT 401 D9 EX_AD9 OUTPUT 400 D9 EX_AD9 CONTROL 399 D9 EX_AD9 INPUT 398 D8 EX_AD8 OUTPUT 3...

Page 1876: ...78 D6 EX_AD6 INPUT 377 D13 EX_AD13 OUTPUT 376 D13 EX_AD13 CONTROL 375 D13 EX_AD13 INPUT 374 D12 EX_AD12 OUTPUT 373 D12 EX_AD12 CONTROL 372 D12 EX_AD12 INPUT 371 PTL0 D16 EX_AD16 IRQ4 IRL4 ET0_COL DREQ0 LCD_D8 OUTPUT 370 PTL0 D16 EX_AD16 IRQ4 IRL4 ET0_COL DREQ0 LCD_D8 CONTROL 369 PTL0 D16 EX_AD16 IRQ4 IRL4 ET0_COL DREQ0 LCD_D8 INPUT 368 PTL1 D17 EX_AD17 IRQ5 IRL5 ET0_MDC DACK0 LCD_D9 OUTPUT 367 PTL...

Page 1877: ...XD LCD_D3 CONTROL 345 PTK1 ST1_D1 GET0_ETXD5 SIOF1_TXD LCD_D3 INPUT 344 PTK0 ST1_D0 GET0_ETXD4 SIOF1_SYNC LCD_D2 OUTPUT 343 PTK0 ST1_D0 GET0_ETXD4 SIOF1_SYNC LCD_D2 CONTROL 342 PTK0 ST1_D0 GET0_ETXD4 SIOF1_SYNC LCD_D2 INPUT 341 PTL4 D20 EX_AD20 ST0_REQ ET0_ETXD0 INTD LCD_D12 OUTPUT 340 PTL4 D20 EX_AD20 ST0_REQ ET0_ETXD0 INTD LCD_D12 CONTROL 339 PTL4 D20 EX_AD20 ST0_REQ ET0_ETXD0 INTD LCD_D12 INPUT...

Page 1878: ... D23 EX_AD23 ST0_VALID ET0_TX EN TEND1 LCD_D15 OUTPUT 316 PTL7 D23 EX_AD23 ST0_VALID ET0_TX EN TEND1 LCD_D15 CONTROL 315 PTL7 D23 EX_AD23 ST0_VALID ET0_TX EN TEND1 LCD_D15 INPUT 314 BS EX_BS OUTPUT 313 BS EX_BS CONTROL 312 BS EX_BS INPUT 311 PTM2 D26 EX_AD26 ST0_D2 ET0_WOL RMII0_CRS_DV PINT2 OUTPUT 310 PTM2 D26 EX_AD26 ST0_D2 ET0_WOL RMII0_CRS_DV PINT2 CONTROL 309 PTM2 D26 EX_AD26 ST0_D2 ET0_WOL R...

Page 1879: ... INPUT 290 PTM7 D31 EX_AD31 ST0_D7 ET0_RX DV RMII0_TXD0 PINT7 OUTPUT 289 PTM7 D31 EX_AD31 ST0_D7 ET0_RX DV RMII0_TXD0 PINT7 CONTROL 288 PTM7 D31 EX_AD31 ST0_D7 ET0_RX DV RMII0_TXD0 PINT7 INPUT 287 PTM6 D30 EX_AD30 ST0_D6 ET0_RX CLK RMII0_TXD1 PINT6 OUTPUT 286 PTM6 D30 EX_AD30 ST0_D6 ET0_RX CLK RMII0_TXD1 PINT6 CONTROL 285 PTM6 D30 EX_AD30 ST0_D6 ET0_RX CLK RMII0_TXD1 PINT6 INPUT 284 CS1 EX_CS0 OUT...

Page 1880: ...PTJ4 ST0M_D2I ET0_ERXD2 RMII1_RXD1 LCD_CL2 INPUT 254 PTJ5 ST0M_D3I ET0_ERXD3 RMII1_RXD0 LCD_DON OUTPUT 253 PTJ5 ST0M_D3I ET0_ERXD3 RMII1_RXD0 LCD_DON CONTROL 252 PTJ5 ST0M_D3I ET0_ERXD3 RMII1_RXD0 LCD_DON INPUT 251 PTJ6 ST0M_D4I ET0_CRS RMII1_TXD_EN LCD_FLM OUTPUT 250 PTJ6 ST0M_D4I ET0_CRS RMII1_TXD_EN LCD_FLM CONTROL 249 PTJ6 ST0M_D4I ET0_CRS RMII1_TXD_EN LCD_FLM INPUT 248 PTJ7 INTB ST0M_D5I IRQO...

Page 1881: ...LK LCD_VCPWC OUTPUT 225 PTK7 ST1_D7 GET0_ERXD7 SIOF2_MCLK LCD_VCPWC CONTROL 224 PTK7 ST1_D7 GET0_ERXD7 SIOF2_MCLK LCD_VCPWC INPUT 223 PTI0 STATUS0 ST1_CLK ST1_STRB RMII0_MDC OUTPUT 222 PTI0 STATUS0 ST1_CLK ST1_STRB RMII0_MDC CONTROL 221 PTI0 STATUS0 ST1_CLK ST1_STRB RMII0_MDC INPUT 220 PTI1 STATUS1 ST1_REQ RMII0_MDIO OUTPUT 219 PTI1 STATUS1 ST1_REQ RMII0_MDIO CONTROL 218 PTI1 STATUS1 ST1_REQ RMII0...

Page 1882: ...WC OUTPUT 196 PTD6 REQ2 PCC_BVD1 GET1_ETXD5 SSI1_SCK LCDM_VCPWC CONTROL 195 PTD6 REQ2 PCC_BVD1 GET1_ETXD5 SSI1_SCK LCDM_VCPWC INPUT 194 PTE1 PCICLK GET1_ETXD4 DACK2 OUTPUT 193 PTE1 PCICLK GET1_ETXD4 DACK2 CONTROL 192 PTE1 PCICLK GET1_ETXD4 DACK2 INPUT 191 PTG4 AD30 ET1_LINKSTA OUTPUT 190 PTG4 AD30 ET1_LINKSTA CONTROL 189 PTG4 AD30 ET1_LINKSTA INPUT 188 PTG0 GNT1 ET1_WOL OUTPUT 187 PTG0 GNT1 ET1_WO...

Page 1883: ...TO2 ET1_CRS RMII1M_TXD_EN CONTROL 165 PTH6 AD27 TPU_TO2 ET1_CRS RMII1M_TXD_EN INPUT 164 PTF3 CBE3 ET1_TX CLK OUTPUT 163 PTF3 CBE3 ET1_TX CLK CONTROL 162 PTF3 CBE3 ET1_TX CLK INPUT 161 PTG5 GNT3 ET1_RX CLK OUTPUT 160 PTG5 GNT3 ET1_RX CLK CONTROL 159 PTG5 GNT3 ET1_RX CLK INPUT 158 PTH2 AD24 TPU_TI2A ET1_ERXD0 RMII1M_TXD1 OUTPUT 157 PTH2 AD24 TPU_TI2A ET1_ERXD0 RMII1M_TXD1 CONTROL 156 PTH2 AD24 TPU_T...

Page 1884: ...1 CBE2 PCC_VS2 SIOF0_TXD HAC_SD_OUT LCDM_D15 OUTPUT 133 PTD1 CBE2 PCC_VS2 SIOF0_TXD HAC_SD_OUT LCDM_D15 CONTROL 132 PTD1 CBE2 PCC_VS2 SIOF0_TXD HAC_SD_OUT LCDM_D15 INPUT 131 PTD5 AD18 PCC_CD2 GET1_ERXD6 SSI1_SDATA LCDM_D14 OUTPUT 130 PTD5 AD18 PCC_CD2 GET1_ERXD6 SSI1_SDATA LCDM_D14 CONTROL 129 PTD5 AD18 PCC_CD2 GET1_ERXD6 SSI1_SDATA LCDM_D14 INPUT 128 PTE2 AD16 PCC_IOIS16 GET1_ERXD7 TEND2 OUTPUT 1...

Page 1885: ...06 PTD4 STOP PCC_CD1 SIOF0_MCLK SSI1_WS LCDM_DON CONTROL 105 PTD4 STOP PCC_CD1 SIOF0_MCLK SSI1_WS LCDM_DON INPUT 104 PTA0 PAR SCIF1_SCK OUTPUT 103 PTA0 PAR SCIF1_SCK CONTROL 102 PTA0 PAR SCIF1_SCK INPUT 101 PTB1 SERR PINT9 LCDM_D9 OUTPUT 100 PTB1 SERR PINT9 LCDM_D9 CONTROL 99 PTB1 SERR PINT9 LCDM_D9 INPUT 98 PTB4 CBE1 PINT12 LCDM_D8 OUTPUT 97 PTB4 CBE1 PINT12 LCDM_D8 CONTROL 96 PTB4 CBE1 PINT12 LC...

Page 1886: ...CDM_D4 OUTPUT 73 PTC3 AD8 MMC_ODMOD LCDM_D4 CONTROL 72 PTC3 AD8 MMC_ODMOD LCDM_D4 INPUT 71 PTB6 CBE0 PINT14 LCDM_D3 OUTPUT 70 PTB6 CBE0 PINT14 LCDM_D3 CONTROL 69 PTB6 CBE0 PINT14 LCDM_D3 INPUT 68 PTB7 AD6 PINT15 LCDM_D2 OUTPUT 67 PTB7 AD6 PINT15 LCDM_D2 CONTROL 66 PTB7 AD6 PINT15 LCDM_D2 INPUT 65 PTC4 AD7 MMC_CMD LCDM_CL2 OUTPUT 64 PTC4 AD7 MMC_CMD LCDM_CL2 CONTROL 63 PTC4 AD7 MMC_CMD LCDM_CL2 INP...

Page 1887: ...T 41 PTN1 SCIF0_RXD MD3 OUTPUT 40 PTN1 SCIF0_RXD MD3 CONTROL 39 PTN1 SCIF0_RXD MD3 INPUT 38 PTN2 SCIF0_TXD MD1 OUTPUT 37 PTN2 SCIF0_TXD MD1 CONTROL 36 PTN2 SCIF0_TXD MD1 INPUT 35 PTN3 SCIF0_CTS MD4 OUTPUT 34 PTN3 SCIF0_CTS MD4 CONTROL 33 PTN3 SCIF0_CTS MD4 INPUT 32 PTN4 SCIF0_RTS MD2 OUTPUT 31 PTN4 SCIF0_RTS MD2 CONTROL 30 PTN4 SCIF0_RTS MD2 INPUT 29 PTN5 NMI OUTPUT 28 PTN5 NMI CONTROL 27 PTN5 NMI...

Page 1888: ...DATA1 RMII0M1_MDC CONTROL 12 PTO2 AUDATA1 RMII0M1_MDC INPUT 11 PTO3 AUDATA2 RMII0M1_MDIO SSI2_SCK OUTPUT 10 PTO3 AUDATA2 RMII0M1_MDIO SSI2_SCK CONTROL 9 PTO3 AUDATA2 RMII0M1_MDIO SSI2_SCK INPUT 8 PTO4 AUDATA3 EX_INT SSI3_WS OUTPUT 7 PTO4 AUDATA3 EX_INT SSI3_WS CONTROL 6 PTO4 AUDATA3 EX_INT SSI3_WS INPUT 5 PTO5 AUDCK DREQ1M SSI3_SDATA OUTPUT 4 PTO5 AUDCK DREQ1M SSI3_SDATA CONTROL 3 PTO5 AUDCK DREQ1...

Page 1889: ...TCK signal and shifted at the falling edge of the TCK signal The TDO value is changed at the falling edge of the TCK signal The TDO signal is in a Hi Z state other than in the Shift DR or Shift IR state A transition to the Test Logic Reset by clearing TRST to 0 is performed asynchronously with the TCK signal Test Logic Reset Capture DR Shift DR Exit1 DR Pause DR Exit2 DR Update DR Select DR Scan R...

Page 1890: ... UDI Reset 42 5 3 H UDI Interrupt The H UDI interrupt function generates an interrupt by setting the appropriate command in SDIR from the H UDI An H UDI interrupt request signal is asserted when the INTREQ bit in SDINT is set to 1 by setting the appropriate command Since the interrupt request signal is not negated until the INTREQ bit is cleared to 0 by software it is not possible to lose the inte...

Page 1891: ...ply voltage VDD DLL1 2 0 3 to 1 8 V Analog power supply voltage AVcc 0 3 to 4 6 V Vin 0 3 to VCCQ 0 3 3 0 3 to VDD RTC 0 3 3 Input voltage Vin DDR 0 3 to VCCQ DDR 0 3 3 V Analog input voltage VAN 0 3 to AVcc 0 3 V Operating temperature Topr 20 to 75 C Storage temperature Tstg 55 to 125 C Notes 1 The LSI may be permanently damaged if the maximum ratings are exceeded 2 The LSI may be permanently dam...

Page 1892: ... internal circuit states are undefined until a low level is input to the RESETP pin after voltage is applied to all power supplies While the internal circuit states are undefined the state of each pin is also undefined Accordingly the system should be designed so that a system malfunction is not caused by such undefined state 43 2 2 Power Off Order There are no restrictions on the power off order ...

Page 1893: ...tion to the RTC power supply backup mode is excluded 2 A transition to the DDR power supply backup mode is excluded A power supply that is turned off first VCCQ VDD RTC 1 AVCC VCCQ DDR 2 VDD VDD PLL or VDD DLL Figure 43 1 Power On and Power Off Timing Table 43 2 Power On and Power Off Timing Item Symbol Maximum time Unit Time lags among powering on VCCQ VDD RTC AVCC VCCQ DDR and VDD VDD PLL1 to 3 ...

Page 1894: ...TBI pin is low After these power supplies become stable bring the XRTCSTBI pin high and negate the PRESET pin to high level 43 2 4 Power Off and Power On Order in DDR SDRAM Power Supply Backup Mode To use DDR SDRAM power supply backup mode the DDR SDRAM should be placed in the self refresh state After the DDR SDRAM is placed in the self refresh state bring the M CKE pin low Make sure that the SELF...

Page 1895: ... 3 3 6 V When not in use the same voltage as VCCQ Reference voltage DDR VREF 1 15 1 25 1 35 V Normal operation IDD 950 1200 mA Ick 266MHz IDD PLL 10 mA IDD DLL 12 mA ICCQ 200 300 mA IDD RTC 0 9 mA VDD RTC 3 3V ICCQ DDR 250 mA DDRck 133MHz IDD 800 mA Ick 266MHz Sleep mode ICCQ 25 mA RTC backup mode IDD RTC 50 µA Current dissipation DDR backup mode ICCQ DDR 155 µA A D conversion period 30 A D and D ...

Page 1896: ...CQ 0 3 Other PCI pins VCCQ 0 5 VCCQ 0 3 Other input pins VIH 2 VCCQ 0 3 V VCCQ 3 0 to 3 6V Input pin group 1 0 3 VCCQ 0 1 VCCQ 3 0 to 3 6 V DDR pins 0 3 DDR VREF 0 18 M_BKPRST 0 3 VCCQ DDR 0 2 DDR VREF 1 15 to 1 35V VCCQ DDR 2 3 to 2 7V PCICLK 0 3 VCCQ 0 2 Other PCI pins 0 3 VCCQ 0 3 Input voltage Other input pins VIL 0 3 VCCQ 0 2 V VCCQ 3 0 to 3 6V DDR pins L 2 VIN 0 5 to VCCQ DDR 0 5V Input leak...

Page 1897: ...3_SCK SSI_CLK SIOF1_MCLK SIOF1_RXD SCIF0_SCK SCIF0_RTS SCIF0_RXD SCIF0_CTS ET1_PHY INT ST1_START ST1_VALID ST0M_VALIDI ST0M_D7I ST0M_D6I REF125CK HAC_BITCLK USB_CLK USB_OVRCRT USBF_VBUS 2 The current dissipation values are for VIH min VDDQ 0 5 V and VIL max 0 5 V with all output pins unload Table 43 5 DC Characteristics 2 b I2 C Related Pins Conditions VCCQ VDD_RTC AVCC 3 0 to 3 6 V VCCQ DDR 2 3 t...

Page 1898: ...eiver related pins USBP USBM Table 43 7 Permissible Output Currents Conditions VCCQ VDD_RTC AVCC 3 0 to 3 6 V VCCQ DDR 2 3 to 2 7 V VDD 1 15 to 1 35 V Ta 20 to 75 C Item Symbol Min Typ Max Unit Permissible output low current per pin DDR1 pins 16 Permissible output low current per pin PCI1 pins 4 Permissible output low current per pin other than DDR and PCI pins IOL 2 mA Permissible output low curr...

Page 1899: ... setup time and hold times for each input signal are observed Table 43 8 Maximum Operating Frequency Conditions VCCQ VDD_RTC AVCC 3 0 to 3 6 V VCCQ DDR 2 3 to 2 7 V VDD 1 15 to 1 35 V Ta 20 to 75 C Item Symbol Min Typ Max Unit CPU FPU cache TLB 200 267 DDR SDRAM bus 100 134 External bus 50 67 PCI bus 32 67 Peripheral modules 0 50 67 Peripheral modules 1 25 34 MHz Operating frequency RTC oscillator...

Page 1900: ... clock output cycle time tCLKOUTcyc 15 20 ns 43 3 CLKOUT clock output low level pulse width tCLKOUTL1 3 ns 43 3 CLKOUT clock output high level pulse width tCLKOUTH1 3 ns 43 3 CLKOUT clock output rise time tCLKOUTr 3 ns 43 3 CLKOUT clock output fall time tCLKOUTf 3 ns 43 3 CLKOUT clock output low level pulse width tCLKOUTL2 3 ns 43 4 CLKOUT clock output high level pulse width tCLKOUTH2 3 ns 43 4 Po...

Page 1901: ...n a 3rd overtone crystal resonator is used an external tank circuit is necessary 2 The load capacitance connected to the CLKOUT pin should be a maximum of 50 pF 3 tcyc shows 1 cycle time of a CLKOUT clock tEXcyc tEXH tEXL tEXr tEXf 1 2VCCQ VIH VIH VIL VIL EXTAL input VIH 1 2VCCQ Notes When the clock is input from EXTAL pin Figure 43 2 EXTAL Clock Input Timing tCLKOUTcyc tCLKOUTH1 CLKOUT tCLKOUTL1 ...

Page 1902: ...5V 1 5V tCLKOUTL2 Figure 43 4 CLKOUT Clock Output Timing 2 VDD MDn PRESET TRST tOSC1 VDD min tMDRH tOSCMD tTRSTRH tRESPW CLKOUT BKPRST Note Oscillation settling time when on chip resonator is used Stable oscillation Internal clock STATUS0 STATUS1 tRESH Stable oscillation Figure 43 5 Power On Oscillation Settling Time ...

Page 1903: ...ut Figure 43 6 PLL Synchronization Settling Time CLKOUT Stable oscillation Standby tSOC2 NMI IRQ7 IRQ0 Note Internal clock Oscillation setting time when on chip resonator is used Figure 43 7 Oscillation Settling Time on Return from Standby NMI or IRQ CLKOUT tRESMS tRESMH MRESET tRESMW tRESMS Figure 43 8 Reset Input Timing ...

Page 1904: ...a 20 to 75 C Item Symbol Min Max Unit Figure BREQ setup time tBREQS 6 ns 43 9 BREQ hold time tBREQH 3 ns 43 9 BACK delay time tBACKD 1 13 ns 43 9 Bus three state delay time tBOFF1 13 ns 43 9 Bus buffer on time tBON1 13 ns 43 9 STATUS0 STATUA1 delay time tSTD 20 ns 43 10 Note tcyc One CLK cycle time CLKOUT A 25 0 CSn BS RDWR CE2A CE2B WEn RD BREQ BACK tBREQH tBREQS tBREQH tBACKD tBACKD tBOFF1 tBON1...

Page 1905: ...ristics Rev 1 00 Oct 01 2007 Page 1839 of 1956 REJ09B0256 0100 CLKOUT tBOFF1 tBOFF1 tSTD tBON1 tBON1 Normal mode Standby mode Normal mode STATUS0 STATUS1 A25 A0 D15 D0 RD RDWR CSn WEn BS Figure 43 10 Pin Drive Timing in Standby Mode ...

Page 1906: ...6 ns 43 11 to 43 22 43 24 43 26 43 27 Read data hold time tRDH 2 ns 43 11 to 43 22 43 24 43 26 43 27 WEn delay time falling edge tWEDF 13 ns 43 11 to 43 14 43 19 43 26 43 27 WEn delay time tWED1 1 13 ns 43 11 to 43 14 43 19 43 22 43 23 43 26 43 27 Write data delay time tWDD 1 13 ns 43 11 to 43 14 43 19 to 43 25 RDY setup time tRDYS 6 ns 43 12 43 13 43 16 43 18 to 43 27 RDY hold time tRDYH 2 5 ns 4...

Page 1907: ...e 1841 of 1956 REJ09B0256 0100 T1 tAD tAD T2 CLKOUT A25 A0 CSn RDWR RD D31 D0 read D31 D0 write BS DACK tWDD tWDD tWDD tRDH tRDS tCSD tCSD tRWD tRWD tRSD tRSD tRSD tWED1 tWEDF tWEDF tBSD tBSD tDACD tDACD RDY WEn Figure 43 11 SRAM Bus Cycle Basic Bus Cycle No Wait ...

Page 1908: ...EJ09B0256 0100 tWDD tWDD tWDD CLKOUT A25 A0 CSn RDWR RD D31 D0 read D31 D0 write BS DACK RDY WEn T1 tAD Tw T2 tAD tRDH tRDS tCSD tRWD tRWD tCSD tRSD tRSD tRSD tWED1 tWEDF tWEDF tRDYH tRDYS tBSD tBSD tDACD tDACD Figure 43 12 SRAM Bus Cycle Basic Bus Cycle One Wait only by Software ...

Page 1909: ...CLKOUT A25 A0 CSn RDWR RD D31 D0 read D31 D0 write BS DACK RDY WEn T1 tAD Tw Twe T2 tAD tRDH tRDS tCSD tRWD tRWD tCSD tRSD tRSD tRSD tWED1 tWEDF tWEDF tRDYH tRDYS tRDYH tRDYS tBSD tBSD tDACD tDACD Figure 43 13 SRAM Bus Cycle Basic Bus Cycle One Wait by Software One Wait by RDY RDY Signal is Synchronous Input ...

Page 1910: ...D tWDD tWDD TS1 tAD T1 T2 TH1 tAD tRDH tRDS tCSD tRWD tRWD tCSD tRSD tRSD tRSD tWED1 tWEDF tWEDF tBSD tBSD tDACD tDACD CLKOUT A25 A0 CSn RDWR RD D31 D0 read D31 D0 write BS DACK RDY WEn Figure 43 14 SRAM Bus Cycle Basic Bus Cycle No Wait No Address Setup Hold Time Insertion RDS 1 RDH 0 WTS 1 WTH 1 ...

Page 1911: ... 2007 Page 1845 of 1956 REJ09B0256 0100 CLKOUT A25 A5 T1 T2 CSn RDWR RD D31 D0 read BS RDY A4 A0 TB2 TB1 TB2 TB1 TB2 TB1 tCSD tAD tRWD tBSD tRDS tBSD tRSD tRSD tRDH tAD tAD tCSD tRWD tRDH tRSD tRDS DACK tDACD tDACD Figure 43 15 Burst ROM Bus Cycle No Wait ...

Page 1912: ...Twb Twb Twe Tw t AD t CSD t RSD t RDH t RDS t BSD t AD t RDH t RSD t RDS t AD t CSD t RDYH t RDYS t RDYH t RDYS t RDYH t RDYS t DACD t DACD t RWD t RWD CLKOUT A25 A5 CSn RDWR RD D31 D0 read BS RDY A4 A0 DACK Figure 43 16 Burst ROM Bus Cycle 1st Data One Wait by Software One Wait by RDY 2nd 3rd 4th Data One Wait only by software ...

Page 1913: ...t CSD t RWD t BSD t RDS t BSD t RSD t AD TS1 TB1 TB2 t AD t RDH TB1 TB2 T2 TB1 t AD t CSD t RWD t RDH t RSD t RDS TH1 TS1 TH1 TS1 TH1 TS1 TH1 CLKOUT A25 A5 CSn RDWR RD D31 D0 read BS RDY A4 A0 DACK t DACD t DACD Figure 43 17 Burst ROM Bus Cycle No Wait No Address Setup Hold Time Insertion RDS 1 RDH 0 ...

Page 1914: ...Twb Twbe Twb T2 TB2 Twbe TB1 CLKOUT A25 A5 A4 A0 D31 D0 read t AD t AD t AD t RDH t RDS t RDH t RDS BS RDY DACK RD t BSD t BSD t BSD t BSD t RSD t RSD CSn t RWD t CSD t RWD t CSD t DACD t DACD t RSD RDWR t RDYH t RDYS t RDYH t RDYS t RDYH t RDYS t RDYH t RDYS Figure 43 18 Burst ROM Bus Cycle One Wait by Software One Wait by RDY ...

Page 1915: ...ad D15 D0 write BS DACK RDY WE1 tAD tAD tWDD tBSD tBSD tBSD tBSD tWDD tWDD tRWD tCSD tCSD tRWD tRSD tRSD tRSD tWEDF tWED1 tWEDF tDACD tRDH tRDS tRDYH tRDYS tRDYH tRDYS tDACD tAD tAD tWDD tWDD tWDD tRWD tCSD tCSD tRWD tRSD tRSD tRSD tWEDF tWED1 tWEDF tDACD tRDH tRDS tDACD A25 A0 1 TED 0 TEH 0 No Wait 2 TED 1 TEH 1 One Internal Wait One External Wait Figure 43 19 PCMCIA Memory Bus Cycle ...

Page 1916: ... tAD tAD tBSD tBSD tBSD tBSD tWDD tWDD tRWD tCSD tCSD tRWD tIORSD tIORSD tIOWSDF tIOWSDF tDACD tRDH tRDS tRDYH tRDYS tRDYH tRDYS tIO16H tIO16S tIO16H tIO16S tDACD tAD tAD tWDD tWDD tWDD tRWD tCSD tCSD tRWD tIORSD tIORSD tIORSD tIOWSDF tIOWSDF tIOWSDF tDACD tRDH tRDS tDACD D15 D0 read D15 D0 write A25 A0 1 TED 0 TEH 0 No Wait 2 TED 1 TEH 1 One Internal Wait One External Wait Figure 43 20 PCMCIA I O...

Page 1917: ...KOUT A25 A1 A0 CExx PCCREG WE0 RDWR IORD WE2 D15 D0 read D15 D0 write BS RDY IOIS16 IOWR WE3 tBSD tBSD tAD tAD tWDD tWDD tWDD tWDD tWDD tRWD tRWD tAD tCSD tCSD tCSD tIORSD tIORSD tIORSD tIOWSDF tIOWSDF tIOWSDF tIOWSDF tIOWSDF tRDH tRDS tRDYS tRDYH tIO16S tIO16H tRDYS tRDYH Figure 43 21 PCMCIA I O Bus Cycle TEDA TEDB 1 TEHA TEHB 1 IW PCIW 1 Dynamic Bus Sizing ...

Page 1918: ... tFMD tCSD tCSD tRDH tRDS tWDD A D0 tWDD tWDD A tWDD tRWD tRWD tWED1 tWED1 tDACD tDACD tRDYH tRDYS tRDYH tRDYS 1st data bus cycle information D31 D29 Access size 000 Byte 001 Word 2 bytes 010 Long 4 bytes 1xx Burst 32 bytes D25 D0 Address 1 1st Data One Internal Wait 2 1st Data One Internal Wait One External Wait 1st data bus cycle information D31 D29 Access size 000 Byte 001 Word 2 bytes 010 Long...

Page 1919: ... Tmd1we Tmd1 t FMD t FMD t BSD t BSD t CSD t CSD t DACD t DACD t WED1 t WED1 D0 t RWD t RWD A t WDD t WDD t WDD 1st data bus cycle information D31 D29 Access size 000 Byte 001 Word 2 bytes 010 Long 4 bytes 1xx Burst 32 bytes D25 D0 Address 1 1st Data No Wait 1st data bus cycle information D31 D29 Access size 000 Byte 001 Word 2 bytes 010 Long 4 bytes 1xx Burst 32 bytes D25 D0 Address 2 1st Data On...

Page 1920: ... t BSD t BSD t CSD t CSD t RDYS t RDYH t DACD t DACD D8 t RWD t RWD A t WDD D7 D3 D1 D2 t WDD t RDH t RDS t RDYS t RDYH t RDYH 1 1st Data One Internal Wait 2nd to 8th Data No Internal Wait 1st data bus cycle information D31 D29 Access size 000 Byte 001 Word 2 bytes 010 Long 4 bytes 1xx Burst 32 bytes D25 D0 Address 1st data bus cycle information D31 D29 Access size 000 Byte 001 Word 2 bytes 010 Lo...

Page 1921: ...w Tmd2 Tmd3 Tmd7 Tmd8we Tmd8 t FMD t FMD t BSD t BSD t CSD t CSD t RDYS t RDYH t DACD t DACD t RWD t RWD A t WDD t WDD t WDD t RDYS t RDYH 1st data bus cycle information D31 D29 Access size 000 Byte 001 Word 2 bytes 010 Long 4 bytes 1xx Burst 32 bytes D25 D0 Address 1 No Internal Wait 2 1st Data One Internal Wait 2nd to 8th Data No Internal Wait External Wait Control 1st data bus cycle information...

Page 1922: ... RWD t RDYH t RDYS t RDYH t RDYS t AD t AD t AD t AD T1 Tw Twe T2 t RSD t RSD t RSD t RSD t RSD t RSD t RSD t RSD t WED1 t WED1 t WEDF t WED1 t WEDF t WED1 t WEDF t WED1 t CSD t CSD t DACD t BSD t BSD t BSD t BSD t BSD t BSD t DACD t RWD t RWD t RSD t AD t AD t RDH t RDS t RDH t RDS t RDH t RDS 1 Basic Read Cycle No Wait 2 Basic Read Cycle One Internal Wait 3 Basic Read Cycle One Internal Wait One...

Page 1923: ...0256 0100 CLKOUT CSn RDWR RD WE D31 D0 read BS DACK RDY A25 A0 TS1 T1 T2 TH1 tRSD tRSD tWED1 tWEDF tWED1 tCSD tCSD tDACD tBSD tBSD tDACD tRWD tRWD tRSD tAD tAD tRDH tRDS Figure 43 27 Byte Control SRAM Bus Cycle Basic Read Cycle No Wait No Address Setup Hold Time Insertion RDS 1 RDH 0 ...

Page 1924: ...nd command signal hold time to M_CLK rising edge tADCTLH 1 2 ns 43 29 43 30 DDR266 1 0 1 0 DDR200 M_CLK to M_DQSn skew time read tRMDQS MCLK 0 8 0 8 ns 43 29 DDR266 0 7 DDR200 M_DQSn to M_Dn skew read tRMDQSQ 0 6 ns 43 29 DDR266 Write command to first M_DQSn delay time rising edge tWMDQSS 0 75 1 2 tMCLK 43 30 M_DQSn falling edge setup time to M_CLK rising edge write tWDSS 0 25 tMCLK 43 30 M_DQSn f...

Page 1925: ...0 tMCLK tMCLKL tMCLKH M_CLK1 Figure 43 28 DDRIF MCLK Output Timing M_CLK1 M_CLK0 M_DQSn D0 D1 D2 D3 D0 D1 D2 D3 M_DQSn M_D31 M_D0 M_D31 M_D0 M_CKE M_CS M_WE M_BAn M_RAS M_CAS M_A13 M_A0 tADCTLS tRMDQSQ tRMDQS MCLK Min tADCTLH tRMDQSQ tRMDQS MCLK Max Figure 43 29 Read Timing of DDR SDRAM 2 Burst Read ...

Page 1926: ...LK0 M_DQSn D0 D1 D2 D3 M_D31 M_D0 M_DQMn M_CKE M_CS M_WE M_BAn M_RAS M_CAS M_A13 M_A0 tADCTLS Write command tWDS tWDH tWMDQSS Min tADCTLH tWMDQSH tWDSS tWDSH tWMDQSL M_DQSn D0 D1 D2 D3 M_D31 M_D0 M_DQMn tWDS tWDH tWMDQSS Max tWMDQSH tWDSS tWDSH tWMDQSL Figure 43 30 Write Timing of DDR SDRAM 2 Burst Write ...

Page 1927: ...NMI pulse width Low tNMIL 5 tcyc 43 31 normal mode sleep mode IRQ7 IRL7 to IRQ0 IRL0 setup time tIRQS 8 ns 43 32 IRQ input IRQ7 IRL7 to IRQ0 IRL0 hold time tIRQH 3 ns 43 32 IRQ input IRQ7 IRL7 to IRQ0 IRL0 setup time tIRLS 8 ns 43 32 IRL input IRQ7 IRL7 to IRQ0 IRL0 hold time tIRLH 3 ns 43 32 IRL input PINTn interrupt setup tGPIOS 15 ns 43 32 GPIO interrupt input PINTn interrupt hold time tGPIOH 8...

Page 1928: ...Electrical Characteristics Rev 1 00 Oct 01 2007 Page 1862 of 1956 REJ09B0256 0100 IRQn IRLn PINTn IRQOUT CLKOUT tIRQS tIRLS tGPIOS tIRQH tIRLH tGPIOH tIRQOD Figure 43 32 IRQ IRL PINT Input and IRQOUT Output Timing ...

Page 1929: ...3 33 External CPU bus release request BREQ hold time tTMS 3 ns 43 33 External CPU bus request acknowledge BACK delay time tDEBAK 1 13 ns 43 33 Address write data setup time tSEDA 6 ns 43 33 Address write data hold time tHEDA 3 ns 43 33 Read data delay time tDED 1 13 ns 43 33 EX_CSn setup time tSECS 6 ns 43 33 EX_CSn hold time tHECS 3 ns 43 33 EX_BS setup time tSEBS 6 ns 43 33 EX_BS hold time tHEBS...

Page 1930: ...tDERY tSERW tSEFR tSEBS tSECS tSEDA tHEDA tSEDA tDEBAK tSEBRQ tHEBRQ tDEBAK tSEDA tHEDA tHEDA tDED tDED tHECS tHEBS tHEFR tHERW tDERY tDERY CLKOUT BREQ BACK EX_CSn EX_BS EX_RDWR EX_RDY EX_FRAME EX_AD31 EX_AD0 write EX_AD31 EX_AD0 read Figure 43 33 External CPU Interface Read Write Access Timing ...

Page 1931: ...me tPCIVAL 10 10 ns 43 35 Tri state drive delay time tPCION 10 10 ns 43 35 Tri state high impedance delay time tPCIOFF 12 12 ns 43 35 Input setup time tPCISU 4 4 ns 43 36 AD31 to AD0 CBE3 to CBE0 PAR PCIFRAME IRDY TRDY STOP LOCK DEVSEL PERR Input hold time tPCIH 0 0 ns 43 36 Output data delay time tPCIVAL 10 10 ns 43 35 Tri state drive delay time tPCION 10 10 ns 43 35 Tri state high impedance dela...

Page 1932: ...DDQ 0 5VDDQ tPCICYC PCICLK tPCIHIGH VH VH VH VL VL tPCILOW tPCIf tPCIr Figure 43 34 PCI Clock Input Timing Output delay Tri state output PCICLK tPCIVAL 0 4VDDQ 0 4VDDQ tPCION tPCIOFF Figure 46 35 Output Signal Timing Input PCICLK 0 4VDDQ 0 4VDDQ 0 4VDDQ tPCIH tPCISU Figure 43 36 Input Signal Timing ...

Page 1933: ...itions VCCQ VDD_RTC AVCC 3 0 to 3 6 V VCCQ DDR 2 3 to 2 7 V VDD 1 15 to 1 35 V Ta 20 to 75 C Item Symbol Min Max Unit Figure Remarks DREQn setup time tDRQS 6 ns 43 37 DREQn hold time tDRQH 5 ns 43 37 TENDn delay time tTENDD 13 ns 43 37 DACKn delay time tDACKD 13 ns 43 37 tTENDD tDACKD tDRQH tDRQH tDRQS tDRQS CLKOUT DREQ TEND DACK Figure 43 37 DREQ TEND and DACK Timing ...

Page 1934: ...to 3 6 V VCCQ DDR 2 3 to 2 7 V VDD 1 15 to 1 35 V Ta 20 to 75 C Item Symbol Min Max Unit Figure Remarks Timer clock pulse width High tTCLKWH 4 tPcyc0 43 38 Timer clock pulse width Low tTCLKWL 4 tPcyc0 43 38 Timer clock rise time tTCLKr 0 8 tPcyc0 43 38 Timer clock fall time tTCLKf 0 8 tPcyc0 43 38 Note tPcyc0 One Pck0 cycle time tTCLKWH TCLK tTCLKWL tTCLKf tTCLKr Figure 43 38 TCLK Input Timing ...

Page 1935: ... Min Max Unit Figure Remarks Timer output delay tTOD 15 Ns 43 39 Timer clock input setup time tTCKS 15 ns 43 40 Count at rising or falling edge tTCKWH tTCKWL 2 tPcyc0 43 40 Timer clock pulse width Count at both edge tTCKWH tTCKWL 3 tPcyc0 43 40 Note tPcyc0 is a cycle time of a peripheral clock 0 Pck0 CLKOUT TPU_TO0 TPU_TO1 tTOD TPU_TO2 TPU_TO3 Figure 43 39 TPU Output Timing CLKOUT TPU_TI2A TPU_TI2...

Page 1936: ... 20 to 75 C Item Symbol Min Typ Max Unit Figure ETn_TX CLK cycle time tTcyc 40 ns 43 41 ETn_TX EN output delay time tTEND 3 20 ns 43 41 ETn_ETXD 3 0 output delay time tTEDD 3 20 ns 43 41 ETn_RX CLK cycle time tRcyc 40 ns 43 42 ETn_RX DV setup time tRDVS 10 ns 43 42 ETn_RX DV hold time tRDVH 3 ns 43 42 ETn_ERXD 3 0 setup time tERDS 10 ns 43 42 ETn_ERXD 3 0 hold time tERDH 3 ns 43 42 ETn_RX ER setup...

Page 1937: ...D SFD DATA CRC ETn_TX CLK ETn_TX EN ETn_ETXD3 to ETn_ETXD0 ETn_TX ER ETn_CRS ETn_COL tETDD Preamble Figure 43 41 MII Transmit Timing normal operation SFD DATA CRC ETn_RX CLK ETn_RX DV ETn_ERXD3 to ETn_ERXD0 ETn_RX ER tERDS tERDH tRDVH tRDVS Preamble Figure 43 42 MII Receive Timing normal operation ...

Page 1938: ...g GMII Table 43 20 Ethernet Controller Signal Timing GMII Conditions VCCQ VDD_RTC AVCC 3 0 to 3 6 V VCCQ DDR 2 3 to 2 7 V VDD 1 15 to 1 35 V Ta 20 to 75 C Item Symbol Min Typ Max Unit Figure GETn_GTX CLK cycle time tGtcyc 8 ns 43 45 Etn_TX EN output delay time tGTEND 0 5 5 5 ns 43 45 GETn_ETXD 7 4 ETn_ETXD 3 0 output delay time tGETDD 0 5 5 5 ns 43 45 ETn_RX CLK cycle time tGRcyc 8 ns 43 46 ETn_RX...

Page 1939: ...hold time tGRERH 0 5 ns 43 47 ETn_WOL output delay time tGWOLD 0 18 ns 43 48 tGTEND SFD DATA CRC GETn_GTX_CLK ETn_TX EN GETn_ETXD7 to GETn_ETXD4 ETn_ETXD3 to ETn_ETXD0 ETn_TX ER ETn_CRS ETn_COL tGETDD Preamble Figure 43 45 GMII Transmit Timing normal operation SFD DATA CRC ETn_RX CLK ETn_RX DV GETn_ERXD7 to GETn_ERXD4 ETn_ERXD3 to ETn_ERXD0 ETn_RX ER tGERDS tGERDH tGRDVH tGRDVS Preamble Figure 43 ...

Page 1940: ...I Table 43 21 Ethernet Controller Signal Timing RMII Conditions VCCQ VDD_RTC AVCC 3 0 to 3 6 V VCCQ DDR 2 3 to 2 7 V VDD 1 15 to 1 35 V Ta 20 to 75 C Item Symbol Min Typ Max Unit Figure REF50CK cycle time tRtcyc 20 ns 43 49 RMIIn_TXD EN RMII1M_TXD EN output delay time tRTEND 2 5 10 ns 43 49 RMIIn_TXD1 RMIIn_TXD0 RMII1M_TXD1 RMII1M_TXD0 output delay time tRETDD 2 5 10 ns 43 49 RMIIn_CRS_DV RMII1M_C...

Page 1941: ...p time tRRERS 4 ns 43 51 RMIIn_RX_ER hold time tRRERH 2 5 ns 43 51 tRTEND SFD DATA CRC REF50CK RMIIn_TXD_EN RMII1M_TXD_EN RMIIn_TXD1 RMIIn_TXD0 RMII1M_TXD1 RMII1M_TXD0 tRETDD Preamble Figure 43 49 RMII Transmit Timing SFD DATA CRC REF50CK tRERDS tRERDH tRRDVH tRRDVS Preamble RMIIn_RXD1 RMIIn_RXD0 RMII1M_RXD1 RMII1M_RXD0 RMIIn_RX_ER RMII1M_RX_ER RMIIn_CRS_DV RMII1M_CRS_DV Figure 43 50 RMII Receive ...

Page 1942: ...ce Module Timing 1 Clock Valid Reception Table 43 22 STIF Clock Valid Reception Signal Timing Conditions VCCQ VDD_RTC AVCC 3 0 to 3 6 V VCCQ DDR 2 3 to 2 7 V VDD 1 15 to 1 35 V Ta 20 to 75 C Item Symbol Min Max Unit Figure ST_CLK cycle time tSTCYC 30 ns 43 52 ST_REQ delay time tSTRQD 4 21 ns 43 52 ST_START setup time tSTSTS 7 ns 43 52 ST_START hold time tSTSTH 4 ns 43 52 ST_VALID setup time tSTVLS...

Page 1943: ... STIF Clock Valid Receive Timing 2 Clock Valid Transmission Table 43 23 STIF Clock Valid Transmission Signal Timing Conditions VCCQ VDD_RTC AVCC 3 0 to 3 6 V VCCQ DDR 2 3 to 2 7 V VDD 1 15 to 1 35 V Ta 20 to 75 C Item Symbol Min Max Unit Figure ST_CLK cycle time tSTCYC 30 ns 43 53 ST_REQ setup time tSTRQS 7 ns 43 53 ST_REQ hold time tSTRQH 5 ns 43 53 ST_START delay time tSTSTD 3 21 ns 43 53 ST_VAL...

Page 1944: ...gnal Timing Conditions VCCQ VDD_RTC AVCC 3 0 to 3 6 V VCCQ DDR 2 3 to 2 7 V VDD 1 15 to 1 35 V Ta 20 to 75 C Item Symbol Min Max Unit Figure ST_STRB low level width tSTSLW 30 ns 43 54 ST_STRB high level width tSTSHW 30 ns 43 54 ST_REQ output delay time tSTRQD 0 ns 43 54 ST_DATA setup time tSTDS 7 ns 43 54 ST_DATA hold time tSTDH 4 ns 43 54 tSTSLW tSTSHW tSTDS tSTDH STn_STRB ST0M_STRBI STn_REQ ST0M...

Page 1945: ...Ta 20 to 75 C Item Symbol Min Max Unit Figure STn_REQ hold time to STn_VALID tSTRQRDH 0 ns 43 55 STn_STRB delay time from STn_REQ tSTSRRQD 2 3 tSTYCYC 43 55 STn_STRB hold time from STn_REQ tSTRQSRH 0 ns 43 55 ST_START delay time from STn_STRB tSTSTSRD 2 ns 43 55 ST_DATA delay time from STn_STRB tSTDSRD 1 ns 43 55 tSTRQRDH tSTSRRQD tSTSTSRD tSTDSRD tSTRQSRH STn_VALID STn_REQ STn_STRB STn_START STn_...

Page 1946: ...to 75 C Item Symbol Min Typ Max Unit Figure IICn_SCL frequency tICYC 0 400 kHz 43 56 43 57 IICn_SCL IICn_SDA fall time tICF 300 ns RP CB 257 10 9 to 275 10 9 Ω pF IICn_SDA input bus free time tICBF 1 3 ns VPU 3 3V IICn_SCL start condition input hold time tICH 0 6 ns IICn_SCL retransmission start condition input setup time tICS 0 6 ns IICn_SDA stop condition input setup time tICST 0 6 ns IICn_SDA s...

Page 1947: ... IICn_SDA P S Sr P tICBF tICF tICYC tICDH tICF tICS tICST tDAS tICH S P and Sr indicate as below S Start condition P Stop condition Sr Retransmission start condition 0 Figure 43 56 I2 C Bus Interface Input Output Timing VPU RP IICn_SDA IICn_SCL CB This LSI Figure 43 57 AC Characteristic Load Condition ...

Page 1948: ...ck cycle asynchronous 8 tPcyc0 43 58 Input clock cycle synchronous tScyc 24 tPcyc0 43 58 Input clock pulse width tSCKW 0 4 0 6 tPcyc0 43 58 Input clock rise time tSCKr 0 8 tPcyc0 43 58 Input clock fall time tSCKf 0 8 tPcyc0 43 58 Transfer data delay time tTXD 6 tPcyc0 50 ns 43 59 Receive data setup time synchronous tRXS 4 tPcyc0 ns 43 59 Receive data hold time synchronous tRXH 4 tPcyc0 ns 43 59 No...

Page 1949: ...Section 43 Electrical Characteristics Rev 1 00 Oct 01 2007 Page 1883 of 1956 REJ09B0256 0100 SCIFn_TXD SCIFn_SCK SCIFn_RXD tScyc tRXS tRXH tTXD tTXD Figure 43 59 SCIFn I O Synchronous Mode Clock Timing ...

Page 1950: ...tPcyc0 ns 43 61 to 43 65 SIOFn_SCK output high level width tSWHO 0 4 tMCYC ns 43 61 to 43 64 SIOFn_SCK output low level width tSWLO 0 4 tMCYC ns 43 61 to 43 64 SIOFn_SYNC output delay time tFSD 20 ns 43 61 to 43 64 SIOFn_SCK input high level width tSWHI 0 4 tSICYC ns 43 65 SIOFn_SCK input low level width tSWLI 0 4 tSICYC ns 43 65 SIOFn_SYNC input setup time tFSS 20 ns 43 65 SIOFn_SYNC input hold t...

Page 1951: ... tFSD SIOF_SCK output SIOF_SYNC output SIOF_TXD SIOF_RXD Figure 43 61 SIOF Transmission Reception Timing Master Mode 1 Sampling at the Falling Edge tSICYC tSWHO tSWLO tFSD tSTDD tSTDD tSRDS tSRDH tFSD SIOF_SCK output SIOF_SYNC output SIOF_TXD SIOF_RXD Figure 43 62 SIOF Transmission Reception Timing Master Mode 1 Sampling at the Rising Edge ...

Page 1952: ... tFSD SIOF_SCK output SIOF_SYNC output SIOF_TXD SIOF_RXD Figure 43 63 SIOF Transmission Reception Timing Master Mode 2 Sampling at the Falling Edge tSICYC tSWHO tSWLO tSTDD tSTDD tSTDD tSTDD tSRDS tSRDH tFSD tFSD SIOF_SCK output SIOF_SYNC output SIOF_TXD SIOF_RXD Figure 43 64 SIOF Transmission Reception Timing Master Mode 2 Sampling at the Rising Edge ...

Page 1953: ...tics Rev 1 00 Oct 01 2007 Page 1887 of 1956 REJ09B0256 0100 tSICYC tSWLI tSWHI tFSH tSTDD tSTDD tSRDS tSRDH tFSS SIOF_SCK input SIOF_SYNC input SIOF_TXD SIOF_RXD Figure 43 65 SIOF Transmission Reception Timing Slave Mode 1 Slave Mode 2 ...

Page 1954: ...2 3 to 2 7 V VDD 1 15 to 1 35 V Ta 20 to 75 C Item Symbol Min Max Unit Figure SIM_CLK clock cycle tSMCYC 2 tPcyc0 16 tPcyc0 ns SIM_CLK clock high level width tSMCWH 0 4 tSMCYC ns SIM_CLK clock low level width tSMCWL 0 4 tSMCYC ns SIM_RST reset output delay tSMRD 20 ns 43 66 Note tPcyc0 is a cycle time of a peripheral clock Pch0 tSMCWH tSMCWL tSMRD tSMRD tSMCYC SIM_CLK SIM_RST Figure 43 66 SIM Modu...

Page 1955: ...ns 43 67 MMC_CLK clock high level width tMMWH 0 4 tMMCYC ns 43 67 MMC_CLK clock low level width tMMWL 0 4 tMMcyc ns 43 67 MMC_CMD output data delay time tMMCD 10 ns 43 67 MMC_CMD input data setup time tMMRCS 10 ns 43 68 MMC_CMD input data hold time tMMRCH 10 ns 43 68 MMC_DAT output data delay time tMMTDD 10 ns 43 67 MMC_DAT input data setup time tMMRDS 10 ns 43 68 MMC_DAT input data hold time tMMR...

Page 1956: ...43 Electrical Characteristics Rev 1 00 Oct 01 2007 Page 1890 of 1956 REJ09B0256 0100 tMMRDS tMMRDH tMMRCH tMMRCS MMC_CLK MMC_CMD input MMC_DAT input Figure 43 68 MMCIF Receive Timing Sampling at the Rising Edge ...

Page 1957: ...RST_LOW 1000 ns 43 69 HAC_SYNC active high pulse width tSYN_HIGH 1000 ns 43 70 HAC_SYNC delay time 1 tSYNCD1 0 15 ns 43 72 HAC_SYNC delay time 2 tSYNCD2 0 15 ns 43 72 HAC_SD_OUT delay time tSDOUTD 0 15 ns 43 72 HAC_SD_IN setup time tSDINS 10 ns 43 72 HAC_SD_IN hold time tSDINH 10 ns 43 72 HAC_BITCLK input high level width tICL_HIGH tPcyc0 ns 43 71 HAC_BITCLK input low level width tICL_LOW tPcyc0 n...

Page 1958: ...1 00 Oct 01 2007 Page 1892 of 1956 REJ09B0256 0100 tICL_HIGH tICL_LOW HAC_BITCLK Figure 43 71 HAC Clock Input Timing HAC_BITCLK HAC_SD_IN HAC_SD_OUT HAC_SYNC tSDINS tSDINH tSDOUTD tSYNCD1 tSYNCD2 Figure 43 72 HAC Interface Module Signal Timing ...

Page 1959: ...nput 43 73 Input high level width Output high level width tIHC tOHC 15 ns input output 43 73 Input low level width Output low level width tILC tOLC 15 ns input output 43 73 SSI_SCK output rise time tRC 10 ns output 43 73 SSI_SDATA WS output delay time tDTR 25 ns transmit 43 74 43 75 SSI_SDATA WS input setup time tSR 10 ns receive 43 76 43 77 SSI_SDATA WS input hold time tHTR 10 ns receive 43 76 43...

Page 1960: ... Oct 01 2007 Page 1894 of 1956 REJ09B0256 0100 tDTR SSI_SCK SSI_WS SSI_SDATA Figure 43 75 SSI Transmit Timing 2 tSR tHTR SSI_SCK SSI_WS SSI_SDATA Figure 43 76 SSI Receive Timing 1 tSR tHTR SSI_SCK SSI_WS SSI_SDATA Figure 43 77 SSI Receive Timing 2 ...

Page 1961: ...ll time tF48 4 ns Duty tHIGH tLOW tDUTY 90 110 43 78 tHIGH tLOW tFREQ 10 USB_CLK input tR48 tF48 90 Figure 43 78 USB Clock Timing Table 43 34 USB Electrical Characteristics Full Speed Item Symbol Min Max Unit Condition 1 Transition time rise 2 tR 4 20 ns CL 50 pF Transition time fall 2 tF 4 20 ns CL 50 pF Rise fall time matching tRFM 90 111 TR TF Output signal crossover power supply voltage VCRS 1...

Page 1962: ...LCDC Module Signal Timing Table 43 36 LCDC Module Signal Timing Conditions VCCQ VDD_RTC AVCC 3 0 to 3 6 V VCCQ DDR 2 3 to 2 7 V VDD 1 15 to 1 35 V Ta 20 to 75 C Item Symbol Min Max Unit Figure LCD_CLK input clock frequency tFREQ 66 MHz LCD_CLK input clock rise time tr 3 ns LCD_CLK input clock fall time tf 3 ns LCD_CLK input clock duty tDUTY 90 110 Clock LCD_CL2 cycle time tCC 25 ns Clock LCD_CL2 h...

Page 1963: ... tVD 0 8Vcc 0 2Vcc 0 8Vcc tVT 0 2Vcc Figure 43 79 LCDC Module Signal Timing 43 4 22 GPIO Signal Timing Table 43 37 GPIO Signal Timing Conditions VCCQ VDD_RTC AVCC 3 0 to 3 6 V VCCQ DDR 2 3 to 2 7 V VDD 1 15 to 1 35 V Ta 20 to 75 C Item Symbol Min Max Unit Figure GPIO output delay time tIOPD 0 15 ns 43 80 GPIO input setup time tIOPS 15 ns 43 80 GPIO input hold time tIOPH 5 ns 43 80 CLKOUT GPIO outp...

Page 1964: ... 43 81 Input clock pulse width Low tTCKL 15 ns 43 81 Input clock rise time tTCKr 10 ns 43 81 Input clock fall time tTCKf 10 ns 43 81 ASEBRK setup time tASEBRKS 10 tcyc 43 82 ASEBRK hold time tASEBRKH 10 tcyc 43 82 TDI TMS setup time tTDIS 15 ns 43 83 TDI TMS hold time tTDIH 15 ns 43 83 TDO data delay time tTDO 0 10 ns 43 83 ASEBRK pin break pulse width tPINBRK 2 tPcyc0 43 84 Notes 1 tcyc One CLKOU...

Page 1965: ...Oct 01 2007 Page 1899 of 1956 REJ09B0256 0100 ASEBRK BRKACK PRESET tASEBRKH tASEBRKS Figure 43 82 PRESET Hold Timing TDI TMS TCK TDO tTCKcyc tTDO tTDIH tTDIS Figure 43 83 H UDI Data Transfer Timing ASEBRK tPINBRK Figure 43 84 ASEBRK Pin Break Timing ...

Page 1966: ...tem Min Typ Max Unit Resolution 10 10 10 bits Conversion time 8 5 µs Analog input capacitance 20 pF Permissible signal source single source impedance 3 5 kΩ Absolute accuracy 4 0 LSB 43 5 2 D A Converter Characteristics Table 43 40 D A Converter Characteristics Conditions VCCQ VDD_RTC AVCC 3 0 to 3 6 V VCCQ DDR 2 3 to 2 7 V VDD 1 15 to 1 35 V Ta 20 to 75 C Item Min Typ Max Unit Test Conditions Res...

Page 1967: ... DDR VDDQ 3 0 to 3 6V VCCQ_DDR 2 3 to 2 7V The output load circuit is shown in figure 43 85 IOL IOH 3 CL RT Reference level LSI output pin VTT DDR VREF DDR pins only DUT output Notes 1 CL 30pF All pins CL is the total value that includes the capacitance of measurement instruments The capacitance of each pin is set to 30 pF 2 RT 50Ω DDR pins only 3 IOL IOH 7 6 mA DDR pins 4 mA PCI pins 2 mA Other o...

Page 1968: ...arger than the stipulated value 30 pF is connected to the LSI pins When connecting an external device with a load capacitance exceeding the regulation use the chart in figure 43 86 as reference for system design Note that if the load capacitance to be connected exceeds the range shown in figure 43 86 the graph will not be a straight line 4 0 ns 3 0 ns 2 0 ns 1 0 ns 0 0 ns 0 pF 25 pF 50 pF Load cap...

Page 1969: ...e CPU store instruction not the access from SuperHyway bus master except CPU After the CPUOPM is updated read CPUOPM once and execute one of the following two methods 1 Execute a branch using the RTE instruction 2 Execute the ICBI instruction for any address including non cacheable area After one of these methods are executed it is guaranteed that the CPU runs under the updated CPUOPM value 31 30 ...

Page 1970: ...utine return is issued speculatively When this bit is set to 0 refer to appendix C Speculative Execution for Subroutine Return 1 Instruction fetch for subroutine return is not issued speculatively 4 0 R Reserved The write value must be the initial value 3 INTMU 0 R W Interrupt mode switch bit 0 SR IMASK is not changed when an interrupt is accepted 1 SR IMASK is changed to the accepted interrupt le...

Page 1971: ...1 presupposes a case in which the instruction ADD indicated by the program counter PC and the address H 04000002 instruction prefetch are executed simultaneously It is also assumed that the program branches to an area other than area 1 after executing the following JMP instruction and delay slot instruction In this case a bus access instruction prefetch to area 1 may unintentionally occur from the...

Page 1972: ...UOPM But this speculative instruction fetch may issue the access to the address that should not be accessed from the program Therefore a bus access to an unexpected area or an internal instruction address error may cause a problem As for the effect of this bus access to unexpected memory area refer to appendix B Instruction Prefetching and Its Side Effects Usage Condition When the speculative exec...

Page 1973: ... PCI operating mode at a power on reset MD8 Mode control pin 8 Input Selects whether to use the crystal resonator at a power on reset MD10 Mode control pin 10 Input Selects the external CPU at a power on reset MPMD Chip mode control pin Input Selects either emulation support mode or LSI operation mode at a power on reset The state of the mode control pins of this LSI is sampled white a power on re...

Page 1974: ...ed with inputs or supplies outputs This LSI This LSI This LSI MDn PRESET MDn PRESET MDn PRESET Device to be connected Devicce to be connected Device to be connected Mode settings high or low level Mode settings high or low level Mode settings high or low level Power on reset from system Power on reset from system Power on reset from system I O control signal Figure D 1 Schematic Diagram of Externa...

Page 1975: ...ollowing table shows the pairs of a Vss or Vdd power supply pin and a Vcc pin in terms of the specific pin numbers Power Supply Pin Pair for Vss Vdd Pin Number Vcc Pin Number V1 K10 V2 L10 V3 M10 V4 N10 V5 P10 W5 Y5 AA9 R10 AA10 T10 AA11 T11 W21 V21 U21 T21 N21 M21 K21 J21 G21 F21 D20 E20 E16 E17 Internal circuits 1 25V Vdd V CC E8 E9 B1 B2 C2 C3 E4 F4 E5 F5 G4 H4 G5 H5 K4 J4 K5 J5 DDR SDRAM I O 2...

Page 1976: ...Vcc Pin Number N5 P5 R4 T3 R5 U3 T4 U4 T5 U5 D11 D10 E11 E10 D8 D9 D7 D6 E7 E6 C4 D5 D3 D4 DDR SDRAM I O 2 5V VCCQ DDR VSSQ DDR A2 A1 AE2 AE1 AD3 AD2 AC4 AC3 AB5 AB4 AA6 AA5 AA8 AA7 AA12 AA14 AA13 AB14 AA15 AA16 AB15 AA17 AA18 AA19 AA20 AA21 Y21 AB22 AB23 AA22 R21 P21 L21 B23 H21 A24 I O 3 3V VCCQ VSSQ E21 A25 ...

Page 1977: ...rcuits 3 3V AVcc AVss AD25 AA25 AA24 AC23 T16 M4 L4 DLL 1 25V Vcc DLL Vss DLL M5 L5 AE24 AD24 AE21 AD21 PLL 1 25V Vcc PLL Vss PLL AE20 AD20 RTC 3 3V VDD RTC VSS RTC D12 E12 Note See figure E 1 Connection Exmple of Bypass Capacitors for Analog Power Supply This LSI AD25 AVcc AA25 AVcc AA24 AVcc AC23 AVss T16 AVss 0 1µF 0 1µF 0 1µF AVcc Figure E 1 Connection Example of Bypass Capacitors for Analog P...

Page 1978: ...0 2 0 Max 0 4 0 05 C 449 φ 0 50 0 05 φ 0 08 M C A B 0 30 C B 0 30 C A 0 35 C 0 15 C 21 00 21 00 A 0 90 0 80 0 90 0 80 B Index 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 7 5 3 1 8 6 4 2 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE Unit mm Figure F 1 Package Dimensions 449 Pin ...

Page 1979: ... L L L O O A11 M_A3 O L L L O O A12 XTAL2 O O O O O O A13 USBM IO I I I I I A14 PTI2 ST0M_STARTI IIC0_SCL SIOF1_RXD USB_OVRCRT USBF_VBUS I I IO I I I I I I I IO I I I I I I IO I I I A15 PTI0 STATUS0 ST1_CLK RMII0_MDC IO O IO O H H P O O O Z O Z O P O IO O A16 PTK4 ST1_D4 GET0_ERXD4 SIOF2_TXD LCD_D6 IO IO I O O M M P IV I O O Z Z Z Z O P IO I O O A17 PTI6 IRQ2 IRL2 ST0M_D6I IIC1_SCL I I I I IO I I ...

Page 1980: ...IO IO IO IO IO I Z Z P Z Z IV I O IV Z P Z Z IO I O I A22 PTM4 D28 EX_AD28 ST0_D4 ET0_PHY INT RMII0_RXD0 PINT4 IO IO IO IO I I I Z Z P Z Z IV I I IV Z P Z Z IO I I I A23 CS0 O H H H Z ZV B3 M_BKPRST I M M M M I B4 M_CKE O O O O O O B5 M_A13 O L L L O O B6 M_CAS O H H H O O B7 M_CS O H H H O O B8 M_BA1 O L L L O O B9 M_A0 O L L L O O B10 M_A2 O L L L O O B11 M_A4 O L L L O O B12 EXTAL2 I I I I I I ...

Page 1981: ...I IO I I I I I I IO I I I I I IO B18 PTJ4 ST0M_D2I ET0_ERXD2 RMII1_RXD1 LCD_CL2 IO I I I O M M P IV I I O Z Z Z Z O P I I I O B19 RDY EX_RDY PCC_WAIT I O I M M IV O IV IV O IV IV O IV B20 CS2 EX_CS1 O I H H H I Z ZV B21 PTM7 D31 EX_AD31 ST0_D7 ET0_RX DV RMII0_TXD0 PINT7 IO IO IO IO I O I Z Z P Z Z IV I O IV Z P Z Z IO I O I B22 PTM5 D29 EX_AD29 ST0_D5 ET0 RX ER RMII0_TXD_EN PINT5 IO IO IO IO I O I...

Page 1982: ...L L O O C12 XRTCSTBI I I I I I I C14 PTI1 STATUS1 ST1_REQ RMII0_MDIO IO O IO IO H H P O O I Z O Z Z P O IO IO C15 PTK6 ST1_D6 GET0_ERXD6 SIOF2_SCK LCD_VEPWC IO IO I IO O M M P IV I O O Z Z Z Z O P IO I IO O C16 PTI4 MD8 ST1_START ET1_PHY INT RMII0M0_MDC USB_PWREN USBF_UPLUP IO I IO I O O O I I P I I O O O Z Z Z O O O P IO I O O O C17 PTJ7 INTB ST0M_D5I IRQOUT IRMII1_TXD0 LCD_D0 IO I I O O O M M IO...

Page 1983: ...Z Z IO O I I C25 PTM1 D25 EX_AD25 ST0_D1 ET0_TX CLK RMII0_RX_ER PINT1 IO IO IO IO I I I Z Z P Z Z IV I I IV Z P Z Z IO I I I D1 M_D1 IO Z Z Z Z IO D2 M_D16 IO Z Z Z Z IO D15 PTK5 ST1_D5 GET0_ERXD5 SIOF2_RXD LCD_D7 IO IO I I O M M P IV I IV O Z Z Z Z O P IO I I O D17 PTJ6 ST0M_D4I ET0_CRS RMII1_TXD_EN LCD_FLM IO I I O O M M P IV I O O Z Z Z O O P I I O O D18 PTJ2 ST0M_D0I ET0_ERXD0 RMII1_TXD1 LCD_M...

Page 1984: ... Z Z O O O P Z Z IO O O O E1 M_D2 IO Z Z Z Z IO E2 M_D17 IO Z Z Z Z IO E3 M_D18 IO Z Z Z Z IO E22 PTK3 ST1_D3 GET0_ETXD7 SIOF2_SYNC LCD_D5 IO IO O IO O M M P IV O O O Z Z O Z O P IO O IO O E23 PTK2 ST1_D2 GET0_ETXD6 SIOF1_SCK LCD_D4 IO IO O IO O M M P IV O O O Z Z O Z O P IO O IO O E24 PTL6 D22 EX_AD22 ST0_START ET0_ETXD2 DACK1 LCD_D14 IO IO IO IO O O O Z Z P Z Z IV O O O Z Z Z Z O O O P Z Z IO O ...

Page 1985: ...XD0 INTD LCD_D12 IO IO IO IO O I O Z Z P Z Z O O IV O Z Z Z Z O IV O P Z Z IO O I O F25 PTJ0 ST0M_REQO GET0_ GTX CLK REF50CK IO O O I M M P O O I Z Z O Z P O O I G1 M_D4 IO Z Z Z Z IO G2 M_D21 IO Z Z Z Z IO G3 M_D22 IO Z Z Z Z IO G22 PTL3 D19 EX_AD19 IRQ7 IRL7 ET0_MDIO INTC LCD_D11 IO IO IO I I IO I O Z Z P Z Z IV IV I IV O Z Z Z IV IV Z IV O P Z Z I I IO I O G23 PTL2 D18 EX_AD18 IRQ6 IRL6 ET0_ETX...

Page 1986: ...Z Z Z IV IV O O O P Z Z I I O O O H24 D15 EX_AD15 IO IO Z Z Z ZV Z H25 D14 EX_AD14 IO IO Z Z Z ZV Z J1 M_D7 IO Z Z Z Z IO J2 M_D6 IO Z Z Z Z IO J3 M_DQM2 O H H H O O J22 D7 EX_AD7 IO IO Z Z Z ZV Z J23 D6 EX_AD6 IO IO Z Z Z ZV Z J24 D13 EX_AD13 IO IO Z Z Z ZV Z J25 D12 EX_AD12 IO IO Z Z Z ZV Z K1 M_DQM0 O H H H O O K2 M_DQS0 IO Z Z Z Z IO K3 M_DQS3 IO Z Z Z Z IO K22 D5 EX_AD5 IO IO Z Z Z ZV Z K23 D...

Page 1987: ... ZV Z M24 WE1 WE O O H H H Z ZV M25 CLKOUT O O O O O O N1 M_D9 IO Z Z Z Z IO N2 M_D26 IO Z Z Z Z IO N3 M_D27 IO Z Z Z Z IO N22 RD FRAME EX_FRAME O O I H H H H I Z ZV N23 WE0 PCC_REG O O H H H O Z ZV N24 A1 O O V 1 O V 1 O Z ZV N25 A0 O O V 1 O V 1 O Z ZV P1 M_D10 IO Z Z Z Z IO P2 M_D28 IO Z Z Z Z IO P3 M_D29 IO Z Z Z Z IO P22 A9 O O V 1 O V 1 O Z ZV P23 A8 O O V 1 O V 1 O Z ZV P24 A3 O O V 1 O V 1...

Page 1988: ... Z ZV U23 A18 O O V 1 O V 1 O Z ZV U24 A13 O O V 1 O V 1 O Z ZV U25 A12 O O V 1 O V 1 O Z ZV V22 A21 O O V 1 O V 1 O Z ZV V23 A20 O O V 1 O V 1 O Z ZV V24 A15 O O V 1 O V 1 O Z ZV V25 A14 O O V 1 O V 1 O Z ZV W1 PTG1 GNT2 ET1_ETXD0 IO O O Z Z IO Z O Z Z O IO O O W2 PTG2 REQ1 ET1_ETXD1 IO I O I I IO I O Z Z O IO I O W3 PTG3 REQ3 ET1_ETXD2 IO I O I I IO I O Z Z O IO I O W4 PTF0 GNT0 GNTIN SIM_D ET1_...

Page 1989: ... O I I I IO I O O I Z Z O O Z IO IO O O I Y4 PTD7 PCIRESET PCC_RESET GET1_ETXD7 LCDM_VEPWC O O O O O O O O O O O O O O O O O O Y22 CE2A O V V O ZV ZV Y23 CE2B O V V O ZV ZV Y24 DA1 O O O O O O Y25 DA0 O O O O O O AA1 PTF1 REQ0 REQOUT SIM_CLK ET1_MDC DACK3 IO IO O O O O I I IO IO I 1 O O O O Z Z Z Z O O IO IO O O O O AA2 PTF2 AD31 SIM_RST ET1_MDIO TEND3 IO IO O IO O I O IO I IO 2 O I O Z Z Z Z O IO...

Page 1990: ...I IO 2 I I I Z IO IO I I IO AB7 PTD5 AD18 PCC_CD2 GET1_ERXD6 SSI1_SDATA LCDM_D14 IO IO I I IO O I O IO I IO 2 I I I O Z Z Z Z Z O IO IO I I IO O AB8 PTD3 PCIFRAME PCC_BVD2 SIOF0_SCK HAC_RES LCDM_D12 IO IO I IO O O I I IO I I O O O Z Z Z Z O O IO IO I IO O O AB9 PTD4 STOP PCC_CD1 SIOF0_MCLK SSI1_WS LCDM_DON IO IO I I IO O I I IO I I I I O Z Z Z Z Z O IO IO I I IO O AB10 PTA3 AD15 SCIF1_CTS IO IO IO...

Page 1991: ...6 AD27 TPU_TO2 ET1_CRS RMII1M_TXD_ EN IO IO O I O I O IO I IO 2 O I O Z Z O Z O IO IO O I O AC2 PTH0 AD25 TPU_TI3A ET1_COL RMII1M_RX_ ER IO IO I I I I O IO I IO 2 I I I Z IO IO I I I AC5 PTH1 IDSEL TPU_TI3B ET1_RX ER RMII1M_CRS_ DV IO I I I I I I IO I I I I Z IO I I I I AC6 PTE3 AD20 SCIF2_SCK GET1_ERXD5 SSI0_WS IO IO IO I IO I O IO I IO 2 I I I Z IO IO IO I IO AC7 PTE2 AD16 PCC_IOIS16 GET1_ERXD7 ...

Page 1992: ... 2 I O Z Z Z O IO IO I O AC13 PTC2 AD2 LCDM_D0 IO IO O I O IO I IO 2 O Z Z O IO IO O AC14 PTC5 AD0 MMC_CD LCDM_FLM IO IO I O I O IO I IO 2 I O Z Z Z O IO IO I O AC15 PTN2 SCIF0_TXD MD1 IO O I I I IO O Z Z IO O AC16 MRESET I I I I I I AC17 PTO7 IRQ1 IRL1 TEND1M SSI3_SCK MD6 IO I I O IO I I I P I I O I Z I I O Z P I I O IO AC18 PTO3 AUDATA2 RMII0M1_MDIO SSI2_SCK IO O IO IO M M P O I IV Z O Z Z P O I...

Page 1993: ... IRDY PCC_VS1 SIOF0_SYNC HAC_SD_IN LCDM_D13 IO IO I IO I O I I IO I I O I O Z Z Z Z Z O IO IO I IO I O AD8 PTA2 LOCK SCIF1_TXD IO IO O I I IO I O Z IO IO O AD9 PTB1 SERR PINT9 LCDM_D9 IO IO I O I I IO I I O Z Z Z O IO IO I O AD10 PTB5 AD14 PINT13 LCDM_M_DISP IO IO I O I O IO I IO 2 I O Z Z Z O IO IO I O AD11 PTC0 AD10 MMC_DAT LCDM_D5 IO IO IO O I O IO I IO 2 IO O Z Z Z O IO IO IO O AD12 PTC4 AD7 M...

Page 1994: ...G5 GNT3 ET1_RX CLK IO O I Z Z IO Z I Z IO O I AE4 PTH5 AD23 TPU_TO1 ET1_ERXD1 RMII1M_TXD0 IO IO O I O I O IO I IO 2 O I O Z Z O Z O IO IO O I O AE5 PTH4 AD19 TPU_TO0 ET1_ERXD3 RMII1M_RXD0 IO IO O I I I O IO I IO 2 O I I Z Z O Z Z IO IO O I I AE6 PTD1 CBE2 PCC_VS2 SIOF0_TXD HAC_SD_OUT LCDM_D15 IO IO I O O O I O IO I IO 2 I O O O Z Z Z Z O O IO IO I O O O AE7 PTA1 DEVSEL SCIF1_RXD IO IO I I I IO I I...

Page 1995: ...D5 LCDM_CL1 IO IO O I O IO I IO 2 O Z Z Z O IO IO O AE13 PTA6 AD1 MMC_VDDON IO IO O I O IO I IO 2 O Z IO IO O AE14 PTN1 SCIF0_RXD MD3 IO I I I I IO Z Z Z IO I AE15 PTN4 SCIF0_RTS MD2 IO IO I I I IO O Z Z IO IO AE16 PRESET I I I I I I AE17 PTO1 AUDATA0 RMII1_MDIO SSI2_SDATA IO O IO IO M M P O I IV Z O Z Z P O IO IO AE18 PTO5 AUDCK DREQ1M SSI3_SDATA IO O I IO M M P O IV IV Z O Z Z P O I IO AE19 TCK ...

Page 1996: ...ff output buffer off pulled up M Input buffer on output buffer off pulled up IV Input buffer on output buffer off pulled up or not according to the GPIO register settings Z High impedance state input buffer off output buffer off ZV High impedance or pulled up according to the LBSC GPIO register settings P Input buffer on or off output buffer on or off pulled up or not according to register setting...

Page 1997: ..._VBUS I I IO I I I Pulled up A15 PTI0_STATUS0 ST1_CLK RMII0_MDC IO O IO O Open PTK4 ST1_D4 SIOF2_TXD LCD_D6 IO IO O O Open A16 GET0_ERXD4 I Pulled up A17 PTI6 IRQ2 IRL2 ST0M_D6I IIC1_SCL I I I I IO Pulled up PTJ5 LCD_DON IO O Open A18 ST0M_D3I ET0_ERXD3 RMII1_RXD0 I I I Pulled up PTJ1 ST0M_CLKIO IO IO Open A19 RMII1_RX_ER LCK_CLK I I Pulled up A20 CS5 CE1A O O Open PTM6 D30 EX_AD30 ST0_D6 RMII0_TX...

Page 1998: ...up B16 PTI5 MD10 ST1_VALID LCD_D1 IO I IO O Always used B17 PTI7 IRQ3 IRL3 ST0M_D7I IIC1_SDA I I I I IO Pulled up PTJ4 LCD_CL2 IO O Open B18 ST0M_D2I ET0_ERXD2 RMII1_RXD1 I I I Pulled up RDY I Pulled down EX_RDY O Open B19 PCC_WAIT I Pulled up CS2 O Open B20 EX_CS1 I Pulled up PTM7 D31 EX_AD31 ST0_D7 RMII0_TXD0 IO IO IO IO O Open B21 ET0_RX DV PINT7 I I Pulled up PTM5 D29 EX_AD29 ST0_D5 RMII0_TXD_...

Page 1999: ...ET1_PHY INT RMII0M0_MDC USB_PWREN USBF_UPLUP IO I IO I O O O Always used PTJ7 IRQOUT IRMII1_TXD0 LCD_D0 IO O O O Open C17 INTB ST0M_D5I I I Pulled up PTJ3 LCD_CL1 IO O Open C18 ST0M_D1I ET0_ERXD1 RMII1_CRS_DV I I I Pulled up C19 CS6 CE1B O O Open CS1 O Open C20 EX_CS0 I Pulled up BS O Open C23 EX_BS I Pulled up PTM2 D26 EX_AD26 ST0_D2 ET0_WOL IO IO IO IO O Open C24 RMII0_CRS_DV PINT2 I I Pulled up...

Page 2000: ... EN TEND1 LCD_D15 IO IO IO IO O O O Open E1 M_D2 IO Open E2 M_D17 IO Open E3 M_D18 IO Open E22 PTK3 ST1_D3 GET0_ETXD7 SIOF2_SYNC LCD_D5 IO IO O IO O Open E23 PTK2 ST1_D2 GET0_ETXD6 SIOF1_SCK LCD_D4 IO IO O IO O Open E24 PTL6 D22 EX_AD22 ST0_START ET0_ETXD2 DACK1 LCD_D14 IO IO IO IO O O O Open PTL5 D21 EX_AD21 ST0_CLK ET0_ETXD1 LCD_D13 IO IO IO IO O O Open E25 DREQ1 I Pulled up F1 M_D3 IO Open F2 M...

Page 2001: ... IO IO O O O Open G23 IRQ6 IRL6 I I Pulled up G24 WE3 IOWR O O Open G25 WE2 IORD O O Open H1 M_D5 IO Open H2 M_D23 IO Open H3 M_DQS2 IO Open PTL0 D16 EX_AD16 LCD_D8 IO IO IO O Open H22 IRQ4 IRL4 ET0_COL DREQ0 I I I I Pulled up PTL1 D17 EX_AD17 ET0_MDC DACK0 LCD_D9 IO IO IO O O O Open H23 IRQ5 IRL5 I I Pulled up H24 D15 EX_AD15 IO IO Open H25 D14 EX_AD14 IO IO Open J1 M_D7 IO Open J2 M_D6 IO Open J...

Page 2002: ... L3 M_DQM3 O Open L22 D3 EX_AD3 IO IO Open L23 D2 EX_AD2 IO IO Open L24 D9 EX_AD9 IO IO Open L25 D8 EX_AD8 IO IO Open M1 M_D8 IO Open M2 M_D24 IO Open M3 M_D25 IO Open M22 D1 EX_AD1 IO IO Open M23 D0 EX_AD0 IO IO Open M24 WE1 WE O O Open M25 CLKOUT O Open N1 M_D9 IO Open N2 M_D26 IO Open N3 M_D27 IO Open RD FRAME O O Open N22 EX_FRAME I Pulled up N23 WE0 PCC_REG O O Open N24 A1 O Open N25 A0 O Ope...

Page 2003: ...n R23 A10 O Open R24 A5 O Open R25 A4 O Open T1 M_D13 IO Open T2 M_D12 IO Open T22 A17 O Open T23 A16 O Open T24 A7 O Open T25 A6 O Open U1 M_D15 IO Open U2 M_D14 IO Open U22 A19 O Open U23 A18 O Open U24 A13 O Open U25 A12 O Open V22 A21 O Open V23 A20 O Open V24 A15 O Open V25 A14 O Open W1 PTG1 GNT2 ET1_ETXD0 IO O O Open PTG2 ET1_ETXD1 IO O Open W2 REQ1 I Pulled up PTG3 ET1_ETXD2 IO O Open W3 R...

Page 2004: ...TXD5 SSI1_SCK LCDM_VCPWC IO O IO O Open Y2 REQ2 PCC_BVD1 I I Pulled up PTE0 PCC_DRV GET1_ETXD6 IO O O Open Y3 INTA DREQ2 IO I Pulled up Y4 PTD7 PCIRESET PCC_RESET GET1_ETXD7 LCDM_VEPWC O O O O O Open Y22 CE2A O Open Y23 CE2B O Open Y24 DA1 O Open Y25 DA0 O Open PTF1 REQOUT SIM_CLK ET1_MDC DACK3 IO O O O O Open AA1 REQ0 IO Pulled up AA2 PTF2 AD31 SIM_RST ET1_MDIO TEND3 IO IO O IO O Open AA3 PTG0 GN...

Page 2005: ...IOF0_MCLK IO I I Pulled up AB10 PTA3 AD15 SCIF1_CTS IO IO IO Open PTB2 AD11 LCDM_D7 IO IO O Open AB11 PINT10 I Pulled up PTB6 CBE0 LCDM_D3 IO IO O Open AB12 PINT14 I Pulled up AB13 PTC1 AD4 LCDM_D1 IO IO O Open AB16 MPMD I Always used AB17 PTO6 IRQ0 IRL0 DACK1M MD5 IO I I O I Always used AB18 PTO2 AUDATA1 RMII0M1_MDC IO O O Open AB20 TDO O Open AB24 AN3 I Open AB25 AN2 I Open PTH6 AD27 TPU_TO2 RMI...

Page 2006: ... up AC13 PTC2 AD2 LCDM_D0 IO IO O Open PTC5 AD0 LCDM_FLM IO IO O Open AC14 MMC_CD I Pulled up AC15 PTN2 SCIF0_TXD MD1 IO O I Always used AC16 MRESET I Always used AC17 PTO7 IRQ1 IRL1 TEND1M SSI3_SCK MD6 IO I I O IO I Always used AC18 PTO3 AUDATA2 RMII0M1_MDIO SSI2_SCK IO O IO IO Open AC19 TRST I Always used AC20 TDI I Open AC21 TMS I Open AC22 BACK O Open AC24 AN1 I Open AC25 AN0 I Open PTF3 CBE3 ...

Page 2007: ...C_CLK IO IO O Open AD14 PTN0 SCIF0_SCK MD0 IO IO I Always used AD15 PTN3 SCIF0_CTS MD4 IO IO I Always used PTN5 IO Open AD16 NMI I Pulled up AD17 PTO0 AUDSYNC RMII1_MDC SSI2_WS IO O O IO Open AD18 PTO4 AUDATA3 EX_INT SSI3_WS IO O O IO Open AD19 ASEBRK BRKACK IO Open AD22 BREQ I Pulled up PTG5 GNT3 IO O Open AE3 ET1_RX CLK I Pulled up PTH5 AD23 TPU_TO1 RMII1M_TXD0 IO IO O O Open AE4 ET1_ERXD1 I Pul...

Page 2008: ...D8 MMC_ODMOD LCDM_D4 IO IO O O Pulled up AE12 PTC6 AD5 LCDM_CL1 IO IO O Open AE13 PTA6 AD1 MMC_VDDON IO IO O Open AE14 PTN1 SCIF0_RXD MD3 IO I I Always used AE15 PTN4 SCIF0_RTS MD2 IO IO I Always used AE16 PRESET I Always used AE17 PTO1 AUDATA0 RMII1_MDIO SSI2_SDATA IO O IO IO Open PTO5 AUDCK SSI3_SDATA IO O IO Open AE18 DREQ1M I Pulled up AE19 TCK I Open AE22 EXTAL I Always used AE23 XTAL O Alway...

Page 2009: ...ocessor Version Register PVR Bit Initial value R W R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 0 1 0 Bit Initial value R W R R R R R R R R R R R R R R R R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 R R R R R Version information Version information 2 Product Register PRR Bit Initial value R W R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial ...

Page 2010: ...nteed values or measures J 1 Heat Resistance Simulation Conditions 1 Circuit Board Model on which this LSI is Mounted JEDEC Standard Board PCB Structure Four layer board of 101 5 mm 114 5 mm t1 6 mm 2S2P Routing rate 20 100 100 20 2 Heat Resistance Simulation Environment Heat resistance simulation environment JEDEC standard environment 300 mm cubic casing Ta ambient temperature 75 C or 60 C windle...

Page 2011: ...vided Therefore if Ta possibly exceeds 60 C heat radiation measures are indispensable Table J 1 Heat Resistance Simulation Results Power Consumption W Heat Sink Ta C Tj C θja C W 2 4 Not provided 75 136 9 25 8 2 4 Provided 75 116 9 17 4 2 4 Not provided 60 122 9 26 2 Note Tj and θja vary depending on the PCB casing heat source and other environmental factors Casing PCB Heat sink This LSI Figure J ...

Page 2012: ... 2007 Page 1946 of 1956 REJ09B0256 0100 This LSI Top view perspective 25 4 mm Side view perspective 25 4 mm 10 0 mm Note A heat sink is attached to this LSI using adhesive 0 125 mm thick and 0 6 W mK Figure J 2 Heat Sink Model ...

Page 2013: ...enerator for External Clock BRG 1181 Big endian 52 Block diagram 13 Branch instructions 72 Break 1115 1176 BRI 1114 1175 Buffer operation 734 Burst mode 602 Bus Arbitration 405 C Cacheability bit 158 Caches 187 CAM function 969 Clock pulse generator CPG 633 Clock valid reception 1017 Clock valid transmission 1021 Clocked Synchronous Mode 1152 Clocked synchronous serial communication mode 1059 Comp...

Page 2014: ...43 Floating point single precision instructions 75 FPU exception 131 Free running operation 755 G GEINT0 974 GEINT1 974 GEINT2 974 General FPU disable exception 128 General illegal instruction exception 126 General interrupt request 133 General Purpose I O GPIO 1679 General registers 38 Gigabit Ethernet controller GETHER 783 GMII MII frame 986 H Hardware ITLB miss handling 164 H UDI reset 116 I I2...

Page 2015: ...le standby mode 680 Multi Buffer frame 971 Multiple interrupts 307 Multiple virtual memory mode 145 N NMI nonmaskable interrupt 132 NMI interrupt 292 Notes on display off mode LCDC stopped 1638 O On chip module interrupts 295 On Chip peripheral module request mode 592 One shot operation 755 Operand access cycle break 1785 P P0 P3 and U0 areas 142 P1 area 142 P2 area 142 P4 area 142 Padding inserti...

Page 2016: ...CDCR 824 CDMR1 1777 CDR1 1776 CEECR 832 CEFCR 826 CERCR 831 CETR1 1778 CHATR 1324 CHCR 576 CLKON 1316 CMCNT 754 CMCOR 754 CMCSR 752 CMDR 1298 CMDSTRT 1302 CMDTYR 1292 CMSTR 751 CPUOPM 1903 CRR0 1770 CRR1 1770 CSTR 1308 CSWR 1322 CTLR0 1546 CTLR1 1548 CTOCR 1306 CVR 1543 DACR 1676 DADR 1675 DAR 573 DARB 574 DASTS 1537 DBK 429 DBR 47 DMA 1540 DMACR 1319 DMAOR 584 DMARS 587 DR 1318 DTOUTR 1307 ECMR 8...

Page 2017: ...398 HACPCML 1399 HACPCMR 1401 HACRIER 1405 HACRSR 1406 HACTIER 1402 HACTSR 1403 ICCCR 1041 ICMAR 1041 ICMCR 1036 ICMIER 1040 ICMSR 1038 ICR0 246 ICR1 248 ICRXD 1043 ICSAR 1035 ICSCR 1029 ICSIER 1034 ICSSR 1031 ICTXD 1043 IER0 1520 IFR0 1504 INT2A0 268 INT2A01 269 INT2A1 272 INT2A11 274 INT2B 283 INT2GPIC 289 INT2MSKCR 279 INT2MSKCR1 281 INT2MSKR 276 INT2MSKR1 277 INT2PRI 266 INTCR 1310 INTCR2 1320...

Page 2018: ...FCR 833 MAHR 818 MALR 819 MIM 417 MMUCR 149 MPR 835 MSTPCR0 672 MSTPCR1 673 NMIFCR 263 OPCR 1304 PACR 1693 PADR 1721 PASCR 152 PBCR 1695 PBDR 1722 PC 47 PCC0CSCIER 1376 PCC0CSCR 1372 PCC0GCR 1369 PCC0ISR 1366 PCCR 1696 PCDR 1723 PDCR 1698 PDDR 1724 PEDR 1725 PFCR 1701 PFDR 1726 PFRCR 838 PFTCR 837 PGCR 1703 PGDR 1727 PHCR 1705 PHDR 1728 PICR 1707 PIDR 1729 PIPR 822 PIPUPR 1736 PIR 817 PJCR 1709 PJ...

Page 2019: ...AR 772 RMONCNT 768 RPADIR 935 RSECAR 769 RSECCNT 764 RSPR 1300 RSPTYR 1293 RWKAR 770 RWKCNT 766 RXALCR0 894 RXALCR1 900 RXNLCR0 893 RXNLCR1 899 RYRAR 777 RYRCNT 768 SAR 572 SARB 573 SBRIVCLV 315 SCBRR 1083 1141 1247 SCFCR 1084 1142 SCFDR 1144 SCFRDR 1068 1126 SCFSR 1077 1135 SCFTDR 1069 1127 SCGRD 1262 SCLSR 1090 1147 SCR 421 SCRDR 1258 SCRER 1091 SCRFDR 1086 SCRSR 1068 1126 1258 SCSC2R 1261 SCSCM...

Page 2020: ...2 STITSC 1011 STR 423 SWSR 1323 TBCR 1297 TBNCR 1298 TCNT 695 TCOR 695 TCPR2 698 TCR 574 696 TCRB 575 TDFAR 930 TDFFR 932 TDFXR 931 TDLAR 908 TFTR 924 TGR 727 TIER 723 TIOR 721 TLFRCR 829 TMDR 719 TOCR 692 TPAUSER 836 TRA 106 TRG 1536 TROCR 823 TRSCER 920 TSFRCR 828 TSR 725 TSTR 693 TSU_ADQT0 867 TSU_ADQT1 868 TSU_ADRH 889 TSU_ADRL 890 TSU_ADSBSY 871 TSU_BSYSL0 845 TSU_BSYSL1 847 TSU_CTRST 841 TSU...

Page 2021: ... Round robin mode 595 RTC power supply backup 684 RXI 1114 1175 S SCIF Interrupt Sources 1175 Self Refresh and initialization 681 Self Refresh mode 433 Sequential break 1787 Serial communication interface with FIFO 1059 Serial communication interface with FIFO IrDA interface SCIF IrDA 1119 Serial I O with FIFO SIOF 1185 Serial interface engine SIE 1491 Serial Sound Interface SSI 1419 Setting the d...

Page 2022: ...t 58 TAP control 1823 TCNT Count Timing 701 TICPI 704 Time setting 778 Timer Unit 687 Transmission in Master Mode 1229 Transmission in Slave Mode 1231 Transmit Descriptor 939 Transmit Receive Reset 1233 TUNI 704 TXI 1114 1175 Types of exceptions 110 U Unconditional trap 125 USB function controller USBF 1495 User break controller 1759 User break operation 1782 User debugging interface 1797 User mod...

Page 2023: ...lication Date Rev 1 00 Oct 01 2007 Published by Sales Strategic Planning Div Renesas Technology Corp Edited by Customer Support Department Global Strategic Communication Div Renesas Solutions Corp 2007 Renesas Technology Corp All rights reserved Printed in Japan ...

Page 2024: ...8 Renesas Technology Hong Kong Ltd 7th Floor North Tower World Finance Centre Harbour City 1 Canton Road Tsimshatsui Kowloon Hong Kong Tel 852 2265 6688 Fax 852 2730 6071 Renesas Technology Taiwan Co Ltd 10th Floor No 99 Fushing North Road Taipei Taiwan Tel 886 2 2715 2888 Fax 886 2 2713 2999 Renesas Technology Singapore Pte Ltd 1 Harbour Front Avenue 06 10 Keppel Bay Tower Singapore 098632 Tel 65...

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Page 2026: ...SH7763 Hardware Manual ...

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