Section 6 Memory Management Unit (MMU)
Rev. 1.00 Oct. 01, 2007 Page 173 of 1956
REJ09B0256-0100
6.6.1
ITLB Address Array
The ITLB address array is allocated to addresses H'F200 0000 to H'F2FF FFFF in the P4 area. An
address array access requires a 32-bit address field specification (when reading or writing) and a
32-bit data field specification (when writing). Information for selecting the entry to be accessed is
specified in the address field, and VPN, V, and ASID to be written to the address array are
specified in the data field.
In the address field, bits [31:24] have the value H'F2 indicating the ITLB address array and the
entry is specified by bits [9:8]. As only longword access is used, 0 should be specified for address
field bits [1:0].
In the data field, bits [31:10] indicate VPN, bit [8] indicates V, and bits [7:0] indicate ASID.
The following two kinds of operation can be used on the ITLB address array:
1. ITLB address array read
VPN, V, and ASID are read into the data field from the ITLB entry corresponding to the entry
set in the address field.
2. ITLB address array write
VPN, V, and ASID specified in the data field are written to the ITLB entry corresponding to
the entry set in the address field.
Address field
31
23
0
1 1 1 1 0 0
0 0
1 0
E
Data field
31
10 9
0
V
VPN
VPN:
V:
E:
*
:
24
Virtual page number
Validity bit
Entry
Don't care
10 9 8 7
2 1
9 8 7
ASID
ASID:
:
Address space identifier
Reserved bits (write value should be 0,
and read value is undefined )
* * * * * * * * * * * * *
* * * * * *
Figure 6.12 Memory-Mapped ITLB Address Array
Summary of Contents for SH7763
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Page 122: ...Section 2 Programming Model Rev 1 00 Oct 01 2007 Page 56 of 1956 REJ09B0256 0100 ...
Page 144: ...Section 3 Instruction Set Rev 1 00 Oct 01 2007 Page 78 of 1956 REJ09B0256 0100 ...
Page 170: ...Section 4 Pipelining Rev 1 00 Oct 01 2007 Page 104 of 1956 REJ09B0256 0100 ...
Page 282: ...Section 7 Caches Rev 1 00 Oct 01 2007 Page 216 of 1956 REJ09B0256 0100 ...
Page 378: ...Section 9 Interrupt Controller INTC Rev 1 00 Oct 01 2007 Page 312 of 1956 REJ09B0256 0100 ...
Page 514: ...Section 12 DDR SDRAM Interface DDRIF Rev 1 00 Oct 01 2007 Page 448 of 1956 REJ09B0256 0100 ...
Page 630: ...Section 13 PCI Controller PCIC Rev 1 00 Oct 01 2007 Page 564 of 1956 REJ09B0256 0100 ...
Page 710: ...Section 16 Clock Pulse Generator CPG Rev 1 00 Oct 01 2007 Page 644 of 1956 REJ09B0256 0100 ...
Page 732: ...Section 17 Watchdog Timer and Reset WDT Rev 1 00 Oct 01 2007 Page 666 of 1956 REJ09B0256 0100 ...
Page 752: ...Section 18 Power Down Mode Rev 1 00 Oct 01 2007 Page 686 of 1956 REJ09B0256 0100 ...
Page 772: ...Section 19 Timer Unit TMU Rev 1 00 Oct 01 2007 Page 706 of 1956 REJ09B0256 0100 ...
Page 824: ...Section 21 Compare Match Timer CMT Rev 1 00 Oct 01 2007 Page 758 of 1956 REJ09B0256 0100 ...
Page 1124: ...Section 26 I 2 C Bus Interface IIC Rev 1 00 Oct 01 2007 Page 1058 of 1956 REJ09B0256 0100 ...
Page 1350: ...Section 30 SIM Card Module SIM Rev 1 00 Oct 01 2007 Page 1284 of 1956 REJ09B0256 0100 ...
Page 1484: ...Section 33 Audio Codec Interface HAC Rev 1 00 Oct 01 2007 Page 1418 of 1956 REJ09B0256 0100 ...
Page 1560: ...Section 35 USB Host Controller USBH Rev 1 00 Oct 01 2007 Page 1494 of 1956 REJ09B0256 0100 ...
Page 1720: ...Section 37 LCD Controller LCDC Rev 1 00 Oct 01 2007 Page 1654 of 1956 REJ09B0256 0100 ...
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