Command reference
R&S
®
ZNA
1482
User Manual 1178.6462.02 ─ 20
STATus:QUEStionable:INTegrity:HARDware:ENABle
<BitPattern>
STATus:QUEStionable:LIMit<Lev>:ENABle
<BitPattern>
Sets the enable mask which allows true conditions in the
EVENt
part of the
QUEStionable...
registers to be reported in the summary bit. If a bit is 1 in the
enable register and its associated event bit transitions to true, a positive transition will
occur in the summary bit (e.g. bit 10 of the
QUEStionable
register for the
LIMit1
register, bit 0 of the
LIMit1
register for the
LIMit2
register).
See also
Chapter 6.5.1, "Overview of status registers"
on page 867 and
"Reset values of the status reporting system"
Suffix:
<Lev>
.
Selects one of the two
QUEStionable:LIMit
registers; see
"STATus:QUEStionable:LIMit<1|2>"
Parameters:
<BitPattern>
Range:
0 to 65535 (decimal representation)
*RST:
n/a
Example:
STAT:QUES:LIM2:ENAB 6
Set bits no. 1 and 2 of the
QUEStionable:LIMit2:ENABle
register
STATus:QUEStionable:NTRansition
<BitPattern>
STATus:QUEStionable:INTegrity:NTRansition
<BitPattern>
STATus:QUEStionable:INTegrity:HARDware:NTRansition
<BitPattern>
STATus:QUEStionable:LIMit<Lev>:NTRansition
<BitPattern>
Sets the negative transition filters of the
QUEStionable...
status registers. If a bit is
set, a 1 to 0 transition in the corresponding bit of the associated condition register cau-
ses a 1 to be written in the associated bit of the corresponding event register.
Suffix:
<Lev>
.
Selects one of the two
QUEStionable:LIMit
registers; see
"STATus:QUEStionable:LIMit<1|2>"
Parameters:
<BitPattern>
Range:
0 to 65535 (decimal representation)
*RST:
n/a
Example:
STAT:QUES:LIM2:NTR 6
Set bits no. 1 and 2 of the
QUEStionable:LIMit2:NTRansition
register
STATus:QUEStionable:PTRansition
<BitPattern>
STATus:QUEStionable:INTegrity:PTRansition
<BitPattern>
STATus:QUEStionable:INTegrity:HARDware:PTRansition
<BitPattern>
STATus:QUEStionable:LIMit<Lev>:PTRansition
<BitPattern>
Configures the positive transition filters of the
QUEStionable...
status registers. If a
bit is set, a 0 to 1 transition in the corresponding bit of the associated condition register
causes a 1 to be written in the associated bit of the corresponding event register.
SCPI command reference