NXP Semiconductors LPC43Sxx, Руководство пользователя

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UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2015. All rights reserved.
User manual Rev. 2.1 — 10 December 2015 949 of 1441
30.1 How to read this chapter
The SCT without the dither engine is available on all flashless LPC43xx/LPC43Sxx parts
(LPC4370/50/30/20/10).
30.2 Basic configuration
The SCT is configured as follows:
•
See Table 714 for clocking and power control.
•
The SCT is reset by the SCT_RST (reset #37).
•
Connect inputs and outputs of the SCT through the GIMA (see Chapter 18 ).
•
The SCT combined interrupt is connected to slot # 10 in the NVIC. SCT outputs 2, 6,
14 are ORed with timer match channels and connected to slots # 13, 14, 16 in the
Event router (see
Table 83 ).
•
To connect the SCT outputs 0 and 1 to the GPDMA, use the DMAMUX register in the
CREG block (see
Table 101 ).
•
The SCT outputs are ORed with various timer match outputs if bit CTOUTCTRL in
CREG6 is zero (see
Table 105 ; this is the default). Set the CTOUTCTRL bit to one to
use the SCT outputs without interference from the timers.
30.3 Features
•
Two 16-bit counters or one 32-bit counter.
•
Counters clocked by bus clock or selected input.
•
Up counters or up-down counters.
•
State variable allows sequencing across multiple counter cycles.
•
The following conditions define an event: a counter match condition, an input (or
output) condition, a combination of a match and/or and input/output condition in a
specified state.
•
Events control outputs, interrupts, and DMA requests.
•
Selected events can limit, halt, start, or stop a counter.
•
Supports:
– 8 inputs
– 16 outputs
UM10503
Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer
(SCT)
Rev. 2.1 — 10 December 2015 User manual
Table 714. SCT clocking and power control
Base clock Branch clock Operating
frequency
SCT BASE_M4_CLK CLK_M4_SCT up to 204 MHz