NXP Semiconductors LPC43Sxx, Руководство пользователя

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User manual Rev. 2.1 — 10 December 2015 954 of 1441
NXP Semiconductors
UM10503
Chapter 30: LPC43xx/LPC43Sxx State Configurable Timer (SCT)
30.6 Register description
The register addresses of the State Configurable Timer are shown in Table 716 . For most
of the SCT registers, the register function depends on the setting of certain other register
bits:
1. The UNIFY bit in the CONFIG register determines whether the SCT is used as one
32-bit register (for operation as one 32-bit counter/timer) or as two 16-bit
counter/timers named L and H. The setting of the UNIFY bit is reflected in the register
map:
– UNIFY = 1: Only one register is used (for operation as one 32-bit counter/timer).
– UNIFY = 0: Access the L and H registers by a 32-bit read or write operation or can
be read or written to individually (for operation as two 16-bit counter/timers).
Typically, the UNIFY bit is configured by writing to the CONFIG register before any
other registers are accessed.
2. The REGMODEn bits in the REGMODE register determine whether each set of
Match/Capture registers uses the match or capture functionality:
– REGMODEn = 0: Registers operate as match and reload registers.
– REGMODEn = 1: Registers operate as capture and capture control registers.
Table 716. Register overview: State Configurable Timer (base address 0x4000 0000)
Name Access Address
offset
Description Reset value Reference
CONFIG R/W 0x000 SCT configuration register 0x0000 7E00 Table 717
CTRL R/W 0x004 SCT control register 0x0004 0004 Table 718
CTRL_L R/W 0x004 SCT control register low counter 16-bit 0x0004 0004 Table 718
CTRL_H R/W 0x006 SCT control register high counter 16-bit 0x0004 0004 Table 718
LIMIT R/W 0x008 SCT limit register 0x0000 0000 Table 719
LIMIT_L R/W 0x008 SCT limit register low counter 16-bit 0x0000 0000 Table 719
LIMIT_H R/W 0x00A SCT limit register high counter 16-bit 0x0000 0000 Table 719
HALT R/W 0x00C SCT halt condition register 0x0000 0000 Table 720
HALT_L R/W 0x00C SCT halt condition register low counter 16-bit 0x0000 0000 Table 720
HALT_H R/W 0x00E SCT halt condition register high counter 16-bit 0x0000 0000 Table 720
STOP R/W 0x010 SCT stop condition register 0x0000 0000 Table 721
STOP_L R/W 0x010 SCT stop condition register low counter 16-bit 0x0000 0000 Table 721
STOP_H R/W 0x012 SCT stop condition register high counter 16-bit 0x0000 0000 Table 721
START R/W 0x014 SCT start condition register 0x0000 0000 Table 722
START_L R/W 0x014 SCT start condition register low counter 16-bit 0x0000 0000 Table 722
START_H R/W 0x016 SCT start condition register high counter 16-bit 0x0000 0000 Table 722
- - 0x018 -
0x03C
Reserved -
COUNT R/W 0x040 SCT counter register 0x0000 0000 Table 723
COUNT_L R/W 0x040 SCT counter register low counter 16-bit 0x0000 0000 Table 723
COUNT_H R/W 0x042 SCT counter register high counter 16-bit 0x0000 0000 Table 723
STATE R/W 0x044 SCT state register 0x0000 0000 Table 724