NXP Semiconductors LPC43Sxx, Руководство пользователя

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UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2015. All rights reserved.
User manual Rev. 2.1 — 10 December 2015 169 of 1441
NXP Semiconductors
UM10503
Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)
– Integer divider A: maximum division factor = 4 (see Table 139 ).
– Integer dividers B, C, D: maximum division factor = 16 (see Table 140 ).
– Integer divider E: maximum division factor = 256 (see Table 141 ).
The output stages select a clock source from the clock source bus for each base clock
(see
Table 123 ). Except for the base clocks to the WWDT (BASE_SAFE_CLK) and USB0
(BASE_USB0_CLK), the clock source for each output stage can be any of the external
and internal clocks and oscillators directly or one of the PLL outputs or any of the outputs
of the integer dividers.
[1] Maximum frequency that guarantees stable operation of the LPC43xx.
Table 122 shows all available input clock sources for each clock generator.
Table 121. CGU0 base clocks
Number Name Frequency
[1]
Description
0 BASE_SAFE_CLK 12 MHz Base safe clock (always on) for WWDT
1 BASE_USB0_CLK 480 MHz Base clock for USB0
2 BASE_PERIPH_CLK 204 MHz Base clock for Cortex-M0SUB subsystem,
SPI, and SGPIO
3 BASE_USB1_CLK 204 MHz Base clock for USB1
4 BASE_M4_CLK 204 MHz System base clock for ARM Cortex-M4
core and APB peripheral blocks #0 and #2
5 BASE_SPIFI_CLK 204 MHz Base clock for SPIFI
6 BASE_SPI_CLK 204 MHz Base clock for SPI
7 BASE_PHY_RX_CLK 75 MHz Base clock for Ethernet PHY Receive
clock
8 BASE_PHY_TX_CLK 75 MHz Base clock for Ethernet PHY Transmit
clock
9 BASE_APB1_CLK 204 MHz Base clock for APB peripheral block # 1
10 BASE_APB3_CLK 204 MHz Base clock for APB peripheral block # 3
11 BASE_LCD_CLK 204 MHz Base clock for LCD
12 BASE_ADCHS_CLK 80 MHz Base clock for ADCHS
13 BASE_SDIO_CLK 204 MHz Base clock for SD/MMC
14 BASE_SSP0_CLK 204 MHz Base clock for SSP0
15 BASE_SSP1_CLK 204 MHz Base clock for SSP1
16 BASE_UART0_CLK 204 MHz Base clock for UART0
17 BASE_UART1_CLK 204 MHz Base clock for UART1
18 BASE_UART2_CLK 204 MHz Base clock for UART2
19 BASE_UART3_CLK 204 MHz Base clock for UART3
20 BASE_OUT_CLK 204 MHz Base clock for CLKOUT pin
24-21 - - Reserved
25 BASE_AUDIO_CLK 204 MHz Base clock for audio system (I2S)
26 BASE_CGU_OUT0_CLK 204 MHz Base clock for CGU_OUT0 clock output
27 BASE_CGU_OUT1_CLK 204 MHz Base clock for CGU_OUT1 clock output