UM10503
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User manual
Rev. 2.1 — 10 December 2015
2 of 1441
NXP Semiconductors
UM10503
LPC43xx/LPC43Sxx User manual
Revision history
Rev
Date
Description
2.1
20151210
LPC43xx/LPC43Sxx User manual
Modifications:
•
Added CREG1 register. See
Table 98 “CREG1 register (CREG1, address 0x4004 3008) bit
•
Updated text in
Section 13.2.1 “Configuring the BASE_M4_CLK for high operating frequencies”
: To
ramp up the clock frequency to an operating frequency above 110 MHz configure the core clock
BASE_M4_CLK as described in
•
Updated description for USB0 (Event 9) and USB1(Event 10) peripheral in
; USB0: Wake-up request signal. Not active in power-down and deep power-down mode. Use
for wake-up from sleep and deep-sleep mode; USB1: USB1 AHB_NEED_CLK signal. Not active in
power-down and deep power-down mode. Use for wake up from sleep and deep-sleep mode.
•
Replaced
Figure 15 “Boot process flowchart for LPC43xx parts with flash”
with a new one.
2.0
20151104
LPC43xx/LPC43Sxx User manual
Modifications:
•
Updated keywords in Document information to add LPC436x and LPC 43S6x. See Table “Document
information”.
•
Added text, the Cortex-M0 coprocessor hardware multiply is implemented as a 32-cycle iterative
multiplier in Section 1.1 “Introduction”.
•
Changed the title of each chapter to add LPC43Sxx.
•
Updated ordering information table to add S parts. See Table 1 “Ordering information”.
•
Updated ordering options table to add S-parts. See Table 2 “Ordering options”.
•
Updated on-chip memory (parts with on-chip flash) list item in Section 1.2 “Features”: Upto 154 kB
SRAM for code and data use.
•
Added block diagram of LPC436x/LPC43S6x. See Figure 5 “LPC436x/LPC43S6x block diagram
(parts with on-chip flash, dual-core)”
•
Updated Table 10 “LPC43xx/LPC43Sxx SRAM configuration” to add LPC436x and LPC43S6x parts.
•
Updated Figure 10 “Parts with on-chip flash: Memory mapping (overview)”.
•
Added device and hex coding information for S parts to Table 46 “LPC43xx part identification
numbers”.
•
Fixed CBC to read Cipher Block Chaining instead of Cipher Book Chaining in Section 8.2 “Features”.
•
Updated Section 30.6 “Register description” text. Was REGMODEn = 1: Registers operate as match
and reload registers. REGMODEn = 0: Registers operate as capture and capture control registers. 0
and 1 reversed to read, REGMODEn = 0: Registers operate as match and reload registers.
REGMODEn = 1: Registers operate as capture and capture control registers.
•
Updated Section 31.3 “Register description” text. Was REGMODEn = 1: Registers operate as match
and reload registers. REGMODEn = 0: Registers operate as capture and capture control registers. 0
and 1 reversed to read, REGMODEn = 0: Registers operate as match and reload registers.
REGMODEn = 1: Registers operate as capture and capture control registers.
•
Updated Table 54 “IAP Copy RAM to Flash command”
Param1(SRC):
Source internal SRAM address from which data bytes are to be read. This address
should be a word boundary.
•
Fixed broken link in Section 11.4.13 “Cortex-M0SUB TXEV event clear register” and Section 11.4.14
“Cortex-M0APP TXEV event clear register”.
•
Added a Remark to Section 25.9.1 “Endpoint queue head (dQH)”: In USB device control case if the
system error occurs, check if the endpoint transfer descriptor are programmed perfectly by software
application during set_configuration request. The system error will occur if the hardware accesses
inaccessible memory space for end point access.
•
Changed the IAP command array size to 5: See Section 6.8 “IAP commands”.
Define data structure or pointers to pass the IAP command table and result table to the IAP function:
unsigned long command[5]; unsigned long result[5];
