UM10503
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© NXP B.V. 2015. All rights reserved.
User manual
Rev. 2.1 — 10 December 2015
1182 of 1441
NXP Semiconductors
UM10503
Chapter 42: LPC43xx/LPC43Sxx SSP0/1
Both the SSP and the off-chip serial slave device then clock each data bit into their serial
shifter on the falling edge of each CLK. The received data is transferred from the serial
shifter to the receive FIFO on the first rising edge of CLK after the LSB has been latched.
42.7.2 SPI frame format
The SPI interface is a four-wire interface where the SSEL signal behaves as a slave
select. The main feature of the SPI format is that the inactive state and phase of the SCK
signal are programmable through the CPOL and CPHA bits within the SSPCR0 control
register.
42.7.2.1 Clock Polarity (CPOL) and Phase (CPHA) control
When the CPOL clock polarity control bit is 0, it produces a steady state low value on the
SCK pin. If the CPOL clock polarity control bit is 1, a steady state high value is placed on
the CLK pin when data is not being transferred.
The CPHA control bit selects the clock edge that captures data and allows it to change
state. It has the most impact on the first bit transmitted by either allowing or not allowing a
clock transition before the first data capture edge. When the CPHA phase control bit is 0,
data is captured on the first clock edge transition. If the CPHA clock phase control bit is 1,
data is captured on the second clock edge transition.
42.7.2.2 SPI format with CPOL=0,CPHA=0
Single and continuous transmission signal sequences for SPI format with CPOL = 0,
CPHA = 0 are shown in
a. Single transfer with CPOL=0 and CPHA=0
b. Continuous transfer with CPOL=0 and CPHA=0
Fig 136. SPI frame format with CPOL=0 and CPHA=0 (a) Single and b) Continuous Transfer)
SCK
SSEL
MOSI
MSB
LSB
Q
MSB
LSB
4 to 16 bits
MISO
SCK
SSEL
MOSI
MISO
4 to 16 bits
4 to 16 bits
MSB
LSB
MSB
LSB
Q
MSB
LSB
Q
MSB
LSB
