NXP Semiconductors LPC43Sxx, Руководство пользователя

Страница: 1016 / 1441

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2015. All rights reserved.
User manual Rev. 2.1 — 10 December 2015 1016 of 1441
32.1 How to read this chapter
The timers are available on all LPC43xx/LPC43Sxx parts.
32.2 Basic configuration
The Timers are configured as follows:
•
See Table 780 for clocking and power control.
•
The Timer0/1/2/3 are reset by the TIMER0/1/2/3_RST (reset #32/33/34/35).
•
The Timer0/1/2/3 interrupts are connected to slot # 12/13/14/15 in the NVIC. Match
channels 2 of Timer0/1/3 are connected to slots # 13, 14, 16 in the Event router.
(These outputs are ORed with SCT outputs 2, 6, 14.)
•
For connecting the match channels 0 and 1 of Timer0/1/2/3 to the GPDMA, use the
DMAMUX register in the CREG block (see
Table 101 ) and enable the GPDMA
channel in the DMA Channel Configuration registers ( Section 21.6.20 ).
•
The timer registers can be also accessed by the GPDMA as memory-to-memory
transfer.
•
To connect a timer capture input to a pin, first select either the CTIN_m or Tn_CAPm
input in the SCU (
Section 17.3.11 ), and then configure the capture input multiplexer
for the selected pin through the GIMA (see Section 18.3 ).
•
The timer match outputs are connected to dedicated Tn_MATm pins and to the
CTOUT_m pins, where they may be ORed with the SCT outputs. See
Table 105 and
Table 715 .
32.3 Features
•
A 32 bit Timer/Counter with a programmable 32 bit Prescaler.
•
Counter or Timer operation
•
Up to four 32-bit capture channels per timer, that can take a snapshot of the timer
value when an input signal transitions. A capture event may also optionally generate
an interrupt.
UM10503
Chapter 32: LPC43xx/LPC43Sxx Timer0/1/2/3
Rev. 2.1 — 10 December 2015 User manual
Table 780. Timer0/1/2/3 clocking and power control
Base clock Branch clock Operating
frequency
Clock to the timer0 register interface and
timer0 peripheral clock PCLK. BASE_M4_CLK CLK_M4_TIMER0 up to
204 MHz
Clock to the timer1 register interface and
timer1 peripheral clock PCLK. BASE_M4_CLK CLK_M4_TIMER1 up to
204 MHz
Clock to the timer2 register interface and
timer2 peripheral clock PCLK. BASE_M4_CLK CLK_M4_TIMER2 up to
204 MHz
Clock to the timer3 register interface and
timer3 peripheral clock PCLK. BASE_M4_CLK CLK_M4_TIMER3 up to
204 MHz