UM10503
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© NXP B.V. 2015. All rights reserved.
User manual
Rev. 2.1 — 10 December 2015
476 of 1441
20.1 How to read this chapter
The SGPIO is available on all LPC43xx/LPC43Sxx parts.
20.2 Basic configuration
The SGPIO is configured as follows:
•
See
for clocking and power control.
•
The SGPIO is reset by the SGPIO_RST (reset #57).
•
The SGPIO interrupt is connected to interrupt slot #31 in the ARM Cortex-M4 NVIC.
•
SGPIO output pins SGPIO3 and SGPIO12 are connected through the GIMA to the
event recorder, the timers, and the SCT (see
). SGPIO output pins SGPIO3
and SGPIO12 also support a divided-by-128 signal to the GIMA (SGPIO3_DIV and
SGPIO12_DIV).
•
SGPIO output pins SGPIO10 and SGPIO12 can trigger the 12-bit ADC.
•
SGPIO output pins SGPIO14 and SGPIO15 can trigger a GPDMA request (see
20.3 Features
•
Each SGPIO input/output slice can be used to perform a serial to parallel or parallel to
serial data conversion.
•
16 SGPIO input/output slices each with a 32-bit FIFO can shift the input value from a
pin or an output value to a pin with every cycle of a shift clock.
•
Each slice is double-buffered.
•
Interrupt is generated on a full FIFO, shift clock, or pattern match.
•
Slices can be concatenated to increase buffer size.
•
Each slice has a 32-bit pattern match filter.
UM10503
Chapter 20: LPC43xx/LPC43Sxx Serial GPIO (SGPIO)
Rev. 2.1 — 10 December 2015
User manual
Table 270. SGPIO clocking and power control
Base clock
Branch clock
Operating
frequency
Notes
SGPIO peripheral
clock
(SGPIO_CLOCK)
BASE_PERIPH_
CLK
CLK_PERIPH_
SGPIO
up to
204 MHz
This clock is
asynchronous to the
main clock and can be
freely chosen to create
a desired SGPIO data
rate.
