NXP Semiconductors LPC43Sxx, Руководство пользователя

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User manual Rev. 2.1 — 10 December 2015 180 of 1441
NXP Semiconductors
UM10503
Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)
13.6.3.4 PLL0USB NP-divider register
Remark: The PLL NP-divider register does not use the direct binary representations of N
= nsel and P = psel directly. Instead, it uses encoded versions NDEC and PDEC of N and
P respectively.
•
The valid range for N = nsel is from 1 to 2^8. This value is encoded into a 10-bit NDEC
value. The relationship can be expressed through the following code snippet:
#define PLL0_NSEL_MAX (1<<8)
/* pre-divider: compute ndec from nsel */
unsigned ndec_new (unsigned nsel) {
unsigned x=0x80, in;
switch (nsel) {
case 0: return 0xFFFFFFFF;
case 1: return 0x302;
case 2: return 0x202;
default:for (in = nsel; in <= PLL0_NSEL_MAX; in++)
x = ((x ^ x>>2 ^ x>>3 ^ x>>4) & 1) << 7 | x>>1 & 0xFF;
return x;
} }
•
The valid range for P = psel is from 1 to 2^5. This value is encoded into a 7-bit PDEC
value. The relationship can be expressed through the following code snippet:
#define PLL0_PSEL_MAX (1<<5)
/* post-divider: compute pdec from psel */
unsigned pdec_new (unsigned psel) {
unsigned x=0x10, ip;
switch (psel) {
case 0: return 0xFFFFFFFF;
case 1: return 0x62;
case 2: return 0x42;
default:for (ip = psel; ip <= PLL0_PSEL_MAX; ip++)
x = ((x ^ x>>2) & 1) << 4 | x>>1 & 0x3F;
return x;
} }
For specific examples see Section 13.8.3 and Section 13.8.4 .
Table 131. PLL0USB NP-divider register (PLL0USB_NP_DIV, address 0x4005 0028) bit
description
Bit Symbol Description Reset
value Access
6:0 PDEC Decoded P-divider coefficient value 000 0010 R/W
11:7 - Reserved - -
21:12 NDEC Decoded N-divider coefficient value 1011 0001 R/W
31:22 - Reserved - -