UM10503
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© NXP B.V. 2015. All rights reserved.
User manual
Rev. 2.1 — 10 December 2015
585 of 1441
NXP Semiconductors
UM10503
Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface
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Command field of the ATA task file set to E0h
–
Reserved fields of the task file cleared to 0
•
BLKSIZ register bits [15:0] and BYTCNT register - Set to 16
–
FLUSH CACHE EXT - No data transfer (RW_BLK) is expected for this ATA
command. For devices that buffer/cache written data, the FLUSH CACHE EXT
command ensures that buffered data is written to the device media. For devices
that do not buffer written data, FLUSH CACHE EXT returns a success status. The
cpu issues RW_REG for the ATA command, and the status is retrieved through
CMD39/RW_REG; there can be error status for this ATA command, in which case
fields other than the status field of the ATA task file are valid.
•
The CPU uses the following settings while sending the RW_REG for STANDBY
IMMEDIATE ATA command:
•
CMD register setting - data_expected field set to 0
•
CMDARG register settings:
•
Bit [31] set to 1
•
Bits [7:2] set to 4
•
Task file settings:
•
Command field of the ATA task file set to EAh
•
Reserved fields of the task file cleared to 0
•
BLKSIZ register bits [15:0] and BYTCNT register - Set to 16
22.7.5.3 Controller/DMA/FIFO Reset Usage
Communication with the card involves the following:
•
Controller - Controls all functions of the Module.
•
FIFO - Holds data to be sent or received.
•
DMA - If DMA transfer mode is enabled, then transfers data between system memory
and the FIFO.
•
Controller reset - Resets the controller by setting the controller_reset bit (bit 0) in the
CTRL register; this resets the CIU and state machines, and also resets the
BIU-to-CIU interface. Since this reset bit is self-clearing, after issuing the reset, wait
until this bit is cleared.
•
FIFO reset - Resets the FIFO by setting the fifo_reset bit (bit 1) in the CTRL register;
this resets the FIFO pointers and counters of the FIFO. Since this reset bit is
self-clearing, after issuing the reset, wait until this bit is cleared.
DMA reset - Resets the internal DMA controller logic by setting the dma_reset bit (bit
2) in the CTRL register, which abruptly terminates any DMA transfer in process. Since
this reset bit is self-clearing, after issuing the reset, wait until this bit is cleared.
The following are recommended methods for issuing reset commands:
•
Non-DMA transfer mode - Simultaneously sets controller_reset and fifo_reset; clears
the RAWINTS register @0x44 using another write in order to clear any resultant
interrupt.
