NXP Semiconductors LPC43Sxx, Руководство пользователя

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UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2015. All rights reserved.
User manual Rev. 2.1 — 10 December 2015 866 of 1441
NXP Semiconductors
UM10503
Chapter 28: LPC43xx/LPC43Sxx Ethernet
The System Time Update logic requires a 50-MHz clock frequency to achieve 20-ns
accuracy. The frequency division is the ratio of the reference clock frequency to the
required clock frequency. Hence, if the reference clock is, for example, 66 MHz, this ratio
is calculated as 66 MHz / 50 MHz = 1.32. Hence, the default addend value to be set in the
register is 2
32
/ 1.32, 0xC1F07C1F.
If the reference clock drifts lower, to 65 MHz for example, the ratio is 65 / 50, or 1.3 and
the value to set in the addend register is 2
32
/ 1.30, or 0xC4EC4EC4. If the clock drifts
higher, to 67 MHz for example, the addend register must be set to 0xBF0B7672. When
the clock drift is nil, the default addend value of 0xC1F07C1F (2
32
/ 1.32) must be
programmed.
In Figure 82 , the constant value used to accumulate the sub-second register is decimal
43, which achieves an accuracy of 20 ns in the system time (in other words, it is
incremented in 20-ns steps).
The software must calculate the drift in frequency based on the Sync messages and
update the Addend register accordingly.
Fig 82. System update using fine method
Addend register
+
Accumulator register
Sub-second register
+
Constant value
Second register
addend_val[31:0]
addend_updt
incr_sub_sec_reg
incr_sec_reg