UM10503
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User manual
Rev. 2.1 — 10 December 2015
569 of 1441
NXP Semiconductors
UM10503
Chapter 22: LPC43xx/LPC43Sxx SD/MMC interface
One data-transfer requirement between the FIFO and cpu is that the number of transfers
should be a multiple of the FIFO data width (F_DATA_WIDTH), which is 32. So if you want
to write only 15 bytes to an SD/MMC/CE-ATA card (BYTCNT), the cpu should write 16
bytes to the FIFO or program the DMA to do 16-byte transfers, if DMA mode is enabled.
The software can still program the Byte Count register to only 15, at which point only 15
bytes will be transferred to the card. Similarly, when 15 bytes are read from a card, the
cpu should still read all 16 bytes from the FIFO.
It is recommended that you do not change the FIFO threshold register in the middle of
data transfers.
22.7.4 Programming sequence
22.7.4.1 Initialization
Once the power and clocks are stable, reset_n should be asserted (active-low) for at least
two clocks of clk or cclk_in, whichever is slower. The reset initializes the registers, ports,
FIFO-pointers, DMA interface controls, and state-machines in the design. After power-on
reset, the software should do the following:
1. After power on reset, configure the SD/MMC pins using the SFSP registers in the
syscon block (
2. Set masks for interrupts by clearing appropriate bits in the Interrupt Mask register
@0x024. Set the global int_enable bit of the Control register @0x00. It is
recommended that you write 0xffff_ffff to the Raw Interrupt register @0x044 in order
to clear any pending interrupts before setting the int_enable bit.
3. Enumerate card stack - Each card is enumerated according to card type; for details,
refer to "Enumerated Card Stack". For enumeration, you should restrict the clock
frequency to 400 KHz in accordance with SD_MMC/CE-ATA standards.
4. Changing clock. The cards operate at a maximum of 26 MHz (at maximum of 52 MHz
in high-speed mode).
5. Set other IP parameters, which normally do not need to be changed with every
command, with a typical value such as time-out values in cclk_out according to
SD_MMC/CE-ATA specifications.
ResponseTimeOut = 0x40
DataTimeOut = highest of one of the following:
–
(10
((TAAC
Fop) + (100
NSAC))
–
Cpu FIFO read/write latency from FIFO empty/full
FIFO threshold value in bytes in the FIFOTH register @0x04C. Typically, the
threshold value can be set to half the FIFO depth (=32); that is:
–
RX_WMark = (FIFO_DEPTH/2) - 1;
–
TX_WMark = FIFO_DEPTH/2
6. If the software decides to handle the interrupts provided by the IP core, you should
create another thread to handle interrupts.
22.7.4.2 Enumerated Card Stack
The card stack does the following:
