NXP Semiconductors LPC43Sxx, Руководство пользователя

Страница: 598 / 1441

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2015. All rights reserved.
User manual Rev. 2.1 — 10 December 2015 598 of 1441
NXP Semiconductors
UM10503
Chapter 23: LPC43xx/LPC43Sxx External Memory Controller (EMC)
23.6 Pin description
23.7 Register description
This chapter describes the EMC registers and provides details required when
programming the microcontroller. The EMC registers are shown in
Table 414 .
Reset value reflects the data stored in used bits only. It does not include the content of
reserved bits.
EMC_CS3 0x1F00 0000 - 0x1FFF FFFF Static 16 MB
EMC_DYCS0 0x2800 0000 - 0x2FFF FFFF Dynamic 128 MB
EMC_DYCS1 0x3000 0000 - 0x3FFF FFFF Dynamic 256 MB
EMC_DYCS2 0x6000 0000 - 0x6FFF FFFF Dynamic 256 MB
EMC_DYCS3 0x7000 0000 - 0x7FFF FFFF Dynamic 256 MB
Table 412. Memory bank selection
Chip select pin Address range Memory type Size of range
Table 413. EMC pin description
Pin function Direction Description
EMC_A[23:0] O Address bus
EMC_D[31:0] I/O Data bus
EMC_BLS[3:0] O Byte lane select
EMC_CS[3:0] O Static RAM memory bank select
EMC_OE O Output enable
EMC_WE O Write enable
EMC_CKEOUT[3:0] O SDRAM clock enable signals
EMC_CLK[3:0];
EMC_CLK01;
EMC_CLK23 O SDRAM clock signals
EMC_DQMOUT[3:0] O Data mask output to SDRAM memory banks
EMC_DYCS[3:0] O SDRAM memory bank select
EMC_CAS O Column address strobe
EMC_RAS O Row address strobe
Table 414. Register overview: External memory controller (base address 0x4000 5000)
Name Access Address
offset
Description Reset
value Reset
value
after
EMC
boot Reference
CONTROL R/W 0x000 Controls operation of the memory
controller. 0x3
[1]
0x1 Table 415
STATUS RO 0x004 Provides EMC status information. 0x5 0x5 Table 416
CONFIG R/W 0x008 Configures operation of the memory
controller. 0 0 Table 417