NXP Semiconductors LPC43Sxx, Руководство пользователя

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UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2015. All rights reserved.
User manual Rev. 2.1 — 10 December 2015 1335 of 1441
48.1 How to read this chapter
The 12-bit ADC is only available on parts LPC4370 and LPC43S70.
48.2 Features
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12-bit high-speed analog to digital converter.
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Input multiplexing among 6 pins.
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Descriptor based conversion sequence for single or multiple inputs.
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Integrated 14-bit timer
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Optional automatic high/low threshold detection.
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Power-down mode.
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Measurement range 0 to 1.2 V.
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12-bit conversion rate of 80 MSamples/s.
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Optional conversion on transition on input pin or various internal signals.
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16-word output FIFO with DMA support.
48.3 Basic configuration
The ADCHS is configured as follows:
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See Table 1119 for clocking and power control.
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The ADCHS is reset by the ADCHS_RST (reset # 60).
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The ADCHS interrupt is connected to interrupt slot # 45 in the Cortex-M4 NVIC and to
slots #30 in the Cortex-M0 subsystem core and in the Cortex-M0 core.
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For connecting to the GPDMA, use the DMAMUX register ( Table 101 ) in the CREG
block and enable the GPDMA channel in the DMA Channel Configuration registers
Section 21.6.20 .
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The ADCHS conversion triggers are connected through the GIMA (see Table 235 ) to
the timers or SCT outputs.
UM10503
Chapter 48: 12-bit ADC (ADCHS)
Rev. 2.1 — 10 December 2015 User manual
Table 1119. ADCHS clocking and power control
Base clock Branch clock Operating
frequency Notes
AHB clock BASE_M4_CLK CLK_M4_ADCHS up to
204 MHz. For register interface.
ADCHS
clock BASE_ADCHS_CLK CLK_ADCHS up to 80 MHz For conversion rate.