NXP Semiconductors LPC43Sxx, Руководство пользователя

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UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2015. All rights reserved.
User manual Rev. 2.1 — 10 December 2015 167 of 1441
NXP Semiconductors
UM10503
Chapter 13: LPC43xx/LPC43Sxx Clock Generation Unit (CGU)
A similar two-step procedure applies when changing the BASE_M4_CLK from low to high
frequencies using the PLL0AUDIO as the clock source.
13.3 Features
•
PLL control
•
Supports three PLLs:
– the PLL0USB for creating the 480 MHz clock for the high-speed USB0
– the PLL0AUDIO with fractional divider for creating a wide variety of frequencies for
audio applications with high accuracy
– the PLL1 for creating the core and peripheral clocks.
•
Oscillator control
•
Clock generation and clock source multiplexing
•
Integer dividers for clock output stages
13.4 General description
The CGU generates multiple independent clocks for the core and the peripheral blocks of
the LPC43x. Each independent clock is called a base clock and itself is one of the inputs
to the two Clock Control Units (CCUs) which control the branch clocks to the individual
peripherals (see
Chapter 14 ).
Fig 35. BASE_M4_CLK ramp-up procedure
12 MHz
90 MHz
110 MHz
204 MHz
BASE_M4_CLK
enable
crystal
oscillator
wake-up from
deep-sleep mode
power-down mode
PLL1
(crystal osc)
IRC
BASE_M4_CLK
clock source =
PSEL = 0,
DIRECT = 0,
connect
PLL1 to
BASE_M4_CLK
PSEL = 0,
DIRECT = 1
250 μs
PLL1 lock
time
50 μs
f
outPLL
f
outPLL/2
set PLL1 M, N dividers,
connect PLL1 to crystal
oscillator