UM10503
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User manual
Rev. 2.1 — 10 December 2015
1149 of 1441
NXP Semiconductors
UM10503
Chapter 40: LPC43xx/LPC43Sxx USART0_2_3
40.7.5.2 Synchronous slave mode
This mode is enabled by setting the CSRC bit of the control register to ‘0’. During
synchronous slave mode, an external clock is required that clocks the serial input and
output data. Note that internally, the serial clock is treated as a data signal. Edge detection
on the serial clock is performed to synchronize the serial clock with the USART clock
domain, hence no registers are clocked with the serial clock.
Reception
By default the received character is similar to the character in asynchronous mode. The
serial data stream is kept HIGH when no data is available. During this time it is not
required for the external serial clock to be running. The first bit that will be received is the
start bit. During this time, the external serial clock must be running. The beginning of the
start bit can either be aligned with the rising edge of the serial clock (sampling on the
falling edge) or the falling edge (sampling on the rising edge), see the FES bit in
. When sampling on the rising edge, it is not required that the beginning of the
start bit is aligned with a clock edge (the clock may not have been running before). In this
case, the edge on the serial input data due to the start bit (logic 1 to 0) is used to
determine the start of the character.
The NOSTARTSTOPBITS bit of the Synchronous Mode Control register allows the user to
disable the transmission/ reception of the start and stop bits, improving the efficiency of
the USART. As a character is no longer identified by the start and stop bits, the serial clock
is used to determine the data bits. When the serial clock is running, all data that is
sampled is regarded as valid data.
In order to be able to identify the start of a character, the beginning of the character must
be aligned with the rising edge of the serial clock. For this reason, the FES bit of the
Synchronous Mode Control register is forced in hardware to ‘1’.
Directly after sampling the last bit, the character is stored in the receive FIFO.
Transmission
During synchronous slave mode, data can only be transmitted when the external serial
clock is running. Hence, when no start and stop bits are sent, transmission can only take
place when data is received from the master. When the start and stop bits are transmitted,
the external clock may only be detected after the first half of the received start bit
(sampling at the rising edge of the external serial clock). By using the edge created by the
received start bit (logic 1 to 0), it is made sure that the start bit of the character that is to be
transmitted by the slave is stable before this rising edge the external slave clock. In this
way it is ensured, that the master receives as many bits as it has transmitted.
When the first sample edge of the incoming serial clock samples a ‘1’ on the serial input
data (and start-stop bits are transmitted, thus the master has not initiated a transaction
yet), it is assumed that the master is running a continuous clock (instead of only running
the clock when sending data characters). The USART will not wait for a start bit from the
master, but will immediately start transmitting data when available. Note that in this
situation, the number of bits transmitted by the master and the number of bits transmitted
by the slave (received by the master) may not be aligned. It is assumed that a higher level
protocol ensures that complete characters are received when the master stops the clock.
