UM10503
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© NXP B.V. 2015. All rights reserved.
User manual
Rev. 2.1 — 10 December 2015
31 of 1441
NXP Semiconductors
UM10503
Chapter 2: LPC43xx/LPC43Sxx Multi-Core configuration and
The command queue is filled by the ARM Cortex-M4 and emptied by the ARM Cortex-M0;
the write pointer is advanced by the ARM Cortex-M4 every time it adds a new command
to the queue. The read pointer is advanced by the ARM Cortex-M0 every time it removes
a command from the queue.
The message queue is filled by the ARM Cortex-M0 and emptied by the ARM Cortex-M4;
the write pointer is advanced by the ARM Cortex-M0 every time it adds a new message to
the queue. The read pointer is advanced by the ARM Cortex-M4 every time it removes a
message from the queue.
When a new command or message has been added to the queue and the write pointer
had been updated, an interrupt is raised to the other processor. The commands are
acknowledged by a return message (accept or fail).
The ARM Cortex-M4 and ARM Cortex-M0 only have one IPC write and one IPC read task.
If multiple instances exist then a local arbiter shall ensure that all write and read
operations are atomic; after data has been written (read) the write (read) pointer is
updated before another write (read) operation can start.
It is the responsibility of the process writing to a queue making sure that the queue is not
filled completely; before loading a new item the process should confirm that the write
pointer will not be equal to, or overtake the read pointer and will leave at least one free
space. On the other hand the receiving side shall promptly process and remove items
from the queue.
No explicit error handling is performed. It is assumed that the ARM Cortex-M0 will always
respond to a ARM Cortex-M4 command.
2.5.2 Protocol
The ARM Cortex-M0 is used as a co-processor to off-load the ARM Cortex-M4 and to
perform serial IO tasks. The ARM Cortex-M4 initializes tasks executed on the ARM
Cortex-M0. The ARM Cortex-M0 is able to signal to the ARM Cortex-M4 when these tasks
have completed or failed by issuing commands from ARM Cortex-M4 to ARM Cortex-M0,
where the ARM Cortex-M0 responds with messages. This command and message
interface resembles a hardware register level interface with command and status
registers.
The ARM Cortex-M4 issues 32-bit commands to the ARM Cortex-M0. Each command
starts with the argument id (P), followed by the read/write bit, followed by a 16-bit ID that
defines which task is referred to. The least significant bit of the task ID indicates the
command type. A Write command is followed by a 32-bit operand. When a new command
is available, the ARM Cortex-M4 signals this to the ARM Cortex-M0 by raising an
interrupt.
The ARM Cortex-M0 return 32-bit messages to the ARM Cortex-M4. A messages starts
the argument id (P or S), followed by a 16-bit ID that indicates which tasks the message
refers to. The least significant byte indicates the message type. A Read response
message is followed by the 32-bit read operand. When a new message is available, the
ARM Cortex-M0 signals this to the ARM Cortex-M4 by raising an interrupt.
