NXP Semiconductors SAFE ASSURE Qorivva MPC5601P, Reference Manual

Page: 809 / 954

Chapter 32 Cyclic Redundancy Check (CRC)
MPC5602P Microcontroller Reference Manual, Rev. 4
Freescale Semiconductor 809
32.5.1 CRC Configuration Register (CRC_CFG)
0x0014 CRC_INP—CRC Input Register, Context 2 on page 810
0x0018 CRC_CSTAT—CRC Current Status Register, Context 2 on page 810
0x001C CRC_OUTP—CRC Output Register, Context 2 on page 811
0x0020–0x3FFF Reserved
Address: Context 1: Base + 0x0000
Context 2: Base + 0x0010
Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0
POL
Y
G
SW
A
P
INV
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 32-4. CRC Configuration Register (CRC_CFG)
Table 32-2. CRC_CFG field descriptions
Field Description
0:28 Reserved
These are reserved bits. These bits are always read as 0 and must always be written with 0.
29 POLYG: Polynomial selection
0: CRC-CCITT polynomial.
1: CRC-32 polynomial.
This bit can be read and written by the software.
This bit can be written only during the configuration phase.
30 SWAP: SWAP selection
0: No swap selection applied on the CRC_OUTP content
1: Swap selection (MSB -> LSB, LSB -> MSB) applied on the CRC_OUTP content. In case of
CRC-CCITT polynomial the swap operation is applied on the 16 LSB bits.
This bit can be read and written by the software.
This bit can be written only during the configuration phase.
31 INV: INV selection
0: No inversion selection applied on the CRC_OUTP content
1: Inversion selection (bit x bit) applied on the CRC_OUTP content. In case of CRC-CCITT polynomial
the inversion operation is applied on the 16 LSB bits.
This bit can be read and written by the software.
This bit can be written only during the configuration phase.
Table 32-1. CRC memory map (continued)
Offset from
CRC_BASE
0xFFE6_8000
Register Location