Chapter 17 Flash Memory
MPC5602P Microcontroller Reference Manual, Rev. 4
Freescale Semiconductor
313
buffer for bank0 in parallel with the requested data being forwarded to the AHB. For bank1, the data is
captured in the page-wide temporary holding register as the requested data is forwarded to the AHB bus.
Timing diagrams of basic read accesses from the Flash array are shown in
.
If the Flash access was the direct result of an AHB transaction, the page buffer is marked as
most-recently-used as it is being loaded. If the Flash access was the result of a speculative prefetch to the
next sequential line, it is first loaded into the least-recently-used buffer. The status of this buffer is not
changed to most-recently-used until a subsequent buffer hit occurs.
17.2.9
Read cycles — buffer hit
Single cycle read responses to the AHB are possible with the platform Flash controller when the requested
read access was previously loaded into one of the bank0 page buffers. In these “buffer hit” cases, read data
is returned to the AHB data phase with a 0 wait state response.
Likewise, the bank1 logic includes a single 128-bit temporary holding register and sequential accesses that
“hit” in this register are also serviced with a 0 wait state response.
17.2.10 Write cycles
In a write cycle, address, write data, and control signals are launched off the same edge of hclk at the
completion of the first AHB data phase cycle. Write cycles to the Flash array are initiated by driving a valid
access address on bk
n
_fl_addr[23:0], driving write data on bk
n
_fl_wdata[63:0], and asserting
bk
n
_fl_wr_en. Again, the controller drives the address and control information for the required setup time
before the rising edge of hclk, and provides the required amount of hold time. The platform Flash
controller then waits for the appropriate number of write wait states before terminating the write operation.
On the cycle following the programmed wait state value, the platform Flash controller asserts hready_out
to indicate to the AHB port that the cycle has terminated.
17.2.11 Error termination
The platform Flash controller follows the standard procedure when an AHB bus cycle is terminated with
an ERROR response. First, the platform Flash controller asserts hresp[0] and negates hready_out to signal
an error has occurred. On the following clock cycle, the platform Flash controller asserts hready_out and
holds both hresp[0] and hready_out asserted until hready_in is asserted.
The first case that can cause an error response to the AHB is when an access is attempted by an AHB
master whose corresponding Read Access Control or Write Access Control settings do not allow the
access, thus causing a protection violation. In this case, the platform Flash controller does not initiate a
Flash array access.
The second case that can cause an error response to the AHB is when an access is performed to the Flash
array and is terminated with a Flash error response. See
Section 17.2.13, “Flash error response operation.
This may occur for either a read or a write operation.
The third case that can cause an error response to the AHB is when a write access is attempted to the Flash
array and is disallowed by the state of the bk
n
_fl_ary_access control input. This case is similar to case 1.
