Chapter 15 Error Correction Status Module (ECSM)
MPC5602P Microcontroller Reference Manual, Rev. 4
292
Freescale Semiconductor
If an attempt to force a non-correctable inversion (by asserting EEGR[FRCNCI] or EEGR[FRC1NCI])
and EEGR[ERRBIT] equals 64, then no data inversion will be generated.
The only allowable values for the 4 control bit enables {FR11BI, FRC1BI, FRCNCI, FR1NCI} are
{0,0,0,0}, {1,0,0,0}, {0,1,0,0}, {0,0,1,0} and {0,0,0,1}. All other values result in undefined behavior.
15.4.2.13 Flash ECC Address Register (FEAR)
The FEAR is a 32-bit register for capturing the address of the last properly enabled ECC event in the flash
memory. Depending on the state of the ECC Configuration Register, an ECC event in the flash causes the
address, attributes and data associated with the access to be loaded into the FEAR, FEMR, FEAT and
FEDR registers, and the appropriate flag (F1BC or FNCE) in the ECC Status Register to be asserted.
6
FRCNCI
Force RAM Continuous Non-Correctable Data Inversions
0 No RAM continuous 2-bit data inversions generated
1 2-bit data inversions in the RAM continuously generated
The assertion of this bit forces the RAM controller to create 2-bit data inversions, as defined by the bit
position specified in ERRBIT[6:0] and the overall odd parity bit, continuously on every write operation.
After this bit has been enabled to generate another continuous non-correctable data inversion, it must be
cleared before being set again to properly re-enable the error generation logic.
The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position
defined by ERRBIT and the overall odd parity bit are inverted to introduce a 2-bit ECC error in the RAM.
7
FR1NCI
Force RAM One Non-Correctable Data Inversions
0 No RAM single 2-bit data inversions generated
1 One 2-bit data inversion in the RAM generated
The assertion of this bit forces the RAM controller to create one 2-bit data inversion, as defined by the bit
position specified in ERRBIT[6:0] and the overall odd parity bit, on the first write operation after this bit is
set.
The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position
defined by ERRBIT and the overall odd parity bit are inverted to introduce a 2-bit ECC error in the RAM.
After this bit has been enabled to generate a single 2-bit error, it must be cleared before being set again
to properly re-enable the error generation logic.
9-15
ERRBIT
[6:0]
Error Bit Position
The vector defines the bit position that is complemented to create the data inversion on the write
operation. For the creation of 2-bit data inversions, the bit specified by this field plus the odd parity bit of
the ECC code are inverted.
The RAM controller follows a vector bit ordering scheme where LSB=0. Errors in the ECC syndrome bits
can be generated by setting this field to a value greater than the RAM width. For example, consider a
32-bit RAM implementation.
The 32-bit ECC approach requires 7 code bits for a 32-bit word. For PRAM data width of 32 bits, the actual
SRAM (32 bits data + 7 bits for ECC) = 39 bits. The following association between the ERRBIT field and
the corrupted memory bit is defined:
if ERRBIT = 0, then RAM[0] of the odd bank is inverted.
if ERRBIT = 1, then RAM[1] of the odd bank is inverted.
...
if ERRBIT = 31, then RAM[31] of the odd bank is inverted.
if ERRBIT = 64, then ECC Parity[0] of the odd bank is inverted.
if ERRBIT = 65, then ECC Parity[1] of the odd bank is inverted.
...
if ERRBIT = 70, then ECC Parity[6] of the odd bank is inverted.
For ERRBIT values of 32 to 63 and greater than 70, no bit position is inverted.
Table 15-12. EEGR field descriptions (continued)
Field
Description
