NXP Semiconductors SAFE ASSURE Qorivva MPC5601P, Reference Manual

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Chapter 9 Interrupt Controller (INTC)
MPC5602P Microcontroller Reference Manual, Rev. 4
Freescale Semiconductor 205
9.5.2.4 INTC End-of-Interrupt Register (INTC_EOIR)
Writing to the end-of-interrupt register signals the end of the servicing of the interrupt request. When the
INTC_EOIR is written, the priority last pushed on the LIFO is popped into INTC_CPR. An exception to
this behavior is described in
Section 9.4.1.2, “Hardware vector mode. The values and size of data written
to the INTC_EOIR are ignored. The values and sizes written to this register neither update the
INTC_EOIR contents or affect whether the LIFO pops. For possible future compatibility, write four bytes
of all 0s to the INTC_EOIR.
Reading the INTC_EOIR has no effect on the LIFO.
9.5.2.5 INTC Software Set/Clear Interrupt Registers
(INTC_SSCIR0_3–INTC_SSCIR4_7)
Address Base + 0x0018 Access: Write-only
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 9-5. INTC End-of-Interrupt Register (INTC_EOIR)
Address Base + 0x0020 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0
CLR
0
0 0 0 0 0 0 0
CLR
1
W SET0 SET1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0
CLR
2
0 0 0 0 0 0 0
CLR
3
W SET2 SET3
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 9-6. INTC Software Set/Clear Interrupt Register 0–3 (INTC_SSCIR[0:3])