NXP Semiconductors SAFE ASSURE Qorivva MPC5601P, Reference Manual

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Chapter 5 Clock Generation Module (MC_CGM)
MPC5602P Microcontroller Reference Manual, Rev. 4
Freescale Semiconductor 119
5.5.10 Auxiliary Clock 2 Divider Configuration Register (CGM_AC2_DC0)
This register controls the auxiliary clock 2 divider.
5.6 Functional Description
5.7 System Clock Generation
Figure 5-12 shows the block diagram of the system clock generation logic. The MC_ME provides the
system clock select and switch mask (see MC_ME chapter for more details), and the MC_RGM provides
the safe clock request (see MC_RGM chapter for more details). The safe clock request forces the selector
to select the 16 MHz int. RC osc. as the system clock and to ignore the system clock select.
Address 0xC3FE_0394 Access: User read, Supervisor read/write, Test read/write
R
DE0
0 0 0
DIV0
0 0 0 0 0 0 0 0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 5-11. Auxiliary Clock 2 Divider Configuration Register (CGM_AC2_DC0)
Table 5-12. Auxiliary Clock 2 Divider Configuration Register (CGM_AC2_DC0) Field Descriptions
Field Description
DE0 Divider 0 Enable
0 Disable auxiliary clock 2 divider 0
1 Enable auxiliary clock 2 divider 0
DIV0 Divider 0 Division Value — The resultant (unused) will have a period DIV0 + 1 times that of auxiliary
clock 2. If the DE0 is set to 0 (Divider 0 is disabled), any write access to the DIV0 field is ignored and the
(unused) remains disabled.