NXP Semiconductors SAFE ASSURE Qorivva MPC5601P, Reference Manual

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Chapter 5 Clock Generation Module (MC_CGM)
MPC5602P Microcontroller Reference Manual, Rev. 4
114 Freescale Semiconductor
5.5.3 System Clock Select Status Register (CGM_SC_SS)
This register provides the current system clock source selection.
5.5.4 System Clock Divider Configuration Register (CGM_SC_DC0)
This register controls the system clock divider.
Address 0xC3FE_0378 Access: User read, Supervisor read, Test read
R 0 0 0 0 SELSTAT 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 5-4. System Clock Select Status Register (CGM_SC_SS)
Table 5-5. System Clock Select Status Register (CGM_SC_SS) Field Descriptions
Field Description
SELSTAT System Clock Source Selection Status — This value indicates the current source for the system clock.
0000 16 MHz int. RC osc.
0001 reserved
0010 4 MHz crystal osc.
0011 reserved
0100 system PLL
0101 reserved
0110 reserved
0111 reserved
1000 reserved
1001 reserved
1010 reserved
1011 reserved
1100 reserved
1101 reserved
1110 reserved
1111 system clock is disabled
Address 0xC3FE_037C Access: User read, Supervisor read/write, Test read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DE0
0 0 0
DIV0
0 0 0 0 0 0 0 0
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 5-5. System Clock Divider Configuration Register (CGM_SC_DC0)