Chapter 22 FlexCAN
MPC5602P Microcontroller Reference Manual, Rev. 4
Freescale Semiconductor
555
in the Error and Status Register). After the transition to ‘Error Passive’ state, the Tx_Err_Counter
does not increment anymore by acknowledge errors. Therefore the device never goes to the ‘Bus
Off’ state.
•
If the Rx_Err_Counter increases to a value greater than 127, it is not incremented further, even if
more errors are detected while being a receiver. At the next successful message reception, the
counter is set to a value between 119 and 127 to resume to ‘Error Active’ state.
22.3.4.8
Error and Status Register (ESR)
This register reflects various error conditions, some general status of the device and it is the source of four
interrupts to the CPU. The reported error conditions (bits 16–21) are those that occurred since the last time
the CPU read this register. The CPU read action clears bits 16–21. Bits 22–28 are status bits.
Most bits in this register are read only, except TWRN_INT, RWRN_INT, BOFF_INT, and ERR_INT, that
are interrupt flags that can be cleared by writing 1 to them (writing 0 has no effect). See
for more details.
Address: Base + 0x001C
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
Rx_Err_Counter
Tx_Err_Counter
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 22-10. Error Counter Register (ECR)
Address: Base + 0x0020
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TWR
N_INT
RWR
N_INT
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R BIT1_
ERR
BIT0_
ERR
ACK_
ERR
CRC_
ERR
FRM_
ERR
STF_
ERR
TX_
WRN
RX_
WRN
IDLE
TXR
X
FLT_CONF
0
BOFF
_INT
ERR_
INT
WAK_
INT
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 22-11. Error and Status Register (ESR)
