Chapter 36 Nexus Development Interface (NDI)
MPC5602P Microcontroller Reference Manual, Rev. 4
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Freescale Semiconductor
register provides the capability of signaling the system level clock controller that the CPU clock should be
activated if not already active.
Updates to the DBCRx and DBSR registers via the OnCE interface should be performed with the CPU in
debug mode to guarantee proper operation. Due to the various points in the CPU pipeline where control is
sampled and event handshaking is performed, it is possible that modifications to these registers while the
CPU is running may result in early or late entry into debug mode, and may have incorrect status posted in
the DBSR register.
If resource sharing is enabled via DBERC0, updates to the DBERC0, DBCRx, and DBSR registers must
be performed with the CPU in debug mode, since simultaneous updates of register portions could
otherwise be attempted, and such updates are not guaranteed to properly occur. The results of such an
attempt are undefined.
36.12.1 OnCE Introduction
The e200z0h on-chip emulation circuitry (OnCE™/Nexus Class 1 interface) provides a means of
interacting with the e200z0h core and integrated system so that a user may examine registers, memory, or
on-chip peripherals facilitating hardware/software development. OnCE operation is controlled via an
industry standard IEEE 1149.1 TAP controller. By using public instructions, the external hardware
debugger can freeze or halt the CPU, read and write internal state, and resume normal execution. The core
does not contain IEEE 1149.1 standard boundary cells on its interface, as it is a building block for further
integration. It does not support the JTAG related boundary scan instruction functionality, although JTAG
public instructions may be decoded and signaled to external logic.
The OnCE logic provides for Nexus Class 1 static debug capability (utilizing the same set of resources
available to software while in internal debug mode), and is present in all e200z0h-based designs. The
OnCE module also provides support for directly integrating a Nexus class 2 or class 3 Real-Time Debug
unit with the e200z0h core for development of real-time systems where traditional static debug is
insufficient. The partitioning between a OnCE module and a connected Nexus module to provide real-time
debug allows for capability and cost trade-offs to be made.
The e200z0h core is designed to be a fully integratable module. The OnCE TAP controller and associated
enabling logic are designed to allow concatenation with an existing JTAG controller if present in the
system. Thus, the e200z0h module can be easily integrated with existing JTAG designs or as a stand-alone
controller.
In order to enable full OnCE operation, the
jd_enable_once
input signal must be asserted. In some system
integrations, this is automatic, since the input will be tied asserted. Other integrations may require the
execution of the Enable OnCE command via the TAP and appropriate entry of serial data. Exact
requirements will be documented by the integrated product specification. The
jd_enable_once
input
signal should not change state during a debug session, or undefined activity may occur.
The following figures show the TAP controller state model and the TAP registers implemented by the
OnCE logic.
