Chapter 17 Flash Memory
MPC5602P Microcontroller Reference Manual, Rev. 4
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Freescale Semiconductor
required and always attached to bank0. Additionally, there is a data Flash attached to bank1. The
platform Flash controller interface supports two separate connections, one to each memory bank.
On the MPC5602P device, bank0 and bank1 are internal to the device.
•
Array
—Each memory bank has one Flash array instantiation.
•
Page
—This value defines the number of bits read from the Flash array in a single access. For this
controller and memory, the page size is 128 bits (16 bytes).
The nomenclature “page buffers” and “line buffers” are used interchangeably.
17.2.1.1
Overview
The platform Flash controller supports a 32-bit data bus width at the AHB port and connections to 128-bit
read data interfaces from two memory banks, where each bank contains one instantiation of the Flash
memory array. One Flash bank is connected to the code Flash memory and the other bank is connected to
the data Flash memory. The memory controller capabilities vary between the two banks with each bank’s
functionality optimized with the typical use cases associated with the attached Flash memory. As an
example, the platform Flash controller logic associated with the code Flash bank contains a four-entry
“page” buffer, each entry containing 128 bits of data (1 Flash page) plus an associated controller that
prefetches sequential lines of data from the Flash array into the buffer, while the controller logic associated
with the data Flash bank only supports a 128-bit register that serves as a temporary page holding register
and does not support any prefetching. Prefetch buffer hits from the code Flash bank support 0-wait AHB
data phase responses. AHB read requests that miss the buffers generate the needed Flash array access and
are forwarded to the AHB upon completion, typically incurring two wait states at an operating frequency
of 60 to 64 MHz.
This memory controller is optimized for applications where a cacheless processor core, for example the
Power e200z0h, is connected through the platform to on-chip memories, for example Flash and RAM,
where the processor and platform operate at the same frequency. For these applications, the 2-stage
pipeline AMBA-AHB system bus is effectively mapped directly into stages of the processor’s pipeline and
0 wait state responses for most memory accesses are critical for providing the required level of system
performance.
17.2.1.2
Features
The following list summarizes the key features of the platform Flash controller:
•
Single AHB port interface supports a 32-bit data bus. All AHB aligned and unaligned reads within
the 32-bit container are supported. Only aligned word writes are supported.
•
Array interfaces support a 128-bit read data bus and a 64-bit write data bus for each bank.
•
Interface with code Flash (bank0) provides configurable read buffering and page prefetch support.
Four page read buffers (each 128 bits wide) and a prefetch controller support single-cycle read
responses (0 AHB data phase wait states) for hits in the buffers. The buffers implement a
least-recently-used replacement algorithm to maximize performance.
•
Interface with data Flash (bank1) includes a 128-bit register to temporarily hold a single Flash
page. This logic supports single-cycle read responses (0 AHB data phase wait states) for accesses
that hit in the holding register. There is no support for prefetching associated with bank1.
