Chapter 1 Introduction
MPC5602P Microcontroller Reference Manual, Rev. 4
Freescale Semiconductor
47
1.6.8
System clocks and clock generation
The following list summarizes the system clock and clock generation on the MPC5602P:
•
Lock detect circuitry continuously monitors lock status
•
Loss of clock (LOC) detection for PLL outputs
•
Programmable output clock divider (
1,
2,
4,
8)
•
FlexPWM module and eTimer module running at the same frequency as the e200z0h core
•
Internal 16 MHz RC oscillator for rapid start-up and safe mode: supports frequency trimming by
user application
1.6.9
Frequency-modulated phase-locked loop (FMPLL)
The FMPLL allows the user to generate high speed system clocks from a 4–40 MHz input clock. Further,
the FMPLL supports programmable frequency modulation of the system clock. The PLL multiplication
factor, output clock divider ratio are all software configurable.
The FMPLL has the following major features:
•
Input clock frequency: 4–40 MHz
•
Maximum output frequency: 64 MHz
•
Voltage controlled oscillator (VCO)—frequency 256–512 MHz
•
Reduced frequency divider (RFD) for reduced frequency operation without forcing the FMPLL to
relock
•
Frequency-modulated PLL
— Modulation enabled/disabled through software
— Triangle wave modulation
•
Programmable modulation depth (±0.25% to ±4% deviation from center frequency):
programmable modulation frequency dependent on reference frequency
•
Self-clocked mode (SCM) operation
1.6.10
Main oscillator
The main oscillator provides these features:
•
Input frequency range: 4–40 MHz
•
Crystal input mode or oscillator input mode
•
PLL reference
1.6.11
Internal RC oscillator
This device has an RC ladder phase-shift oscillator. The architecture uses constant current charging of a
capacitor. The voltage at the capacitor is compared by the stable bandgap reference voltage.
The RC oscillator provides these features:
