Chapter 15 Error Correction Status Module (ECSM)
MPC5602P Microcontroller Reference Manual, Rev. 4
Freescale Semiconductor
291
It should be noted that while the EEGR is associated with the RAM, similar capabilities exist for the flash,
that is, the ability to program the non-volatile memory with single- or double-bit errors is supported for
the same two reasons previously identified.
For both types of memories (RAM and flash), the intent is to generate errors during data write cycles, such
that subsequent reads of the corrupted address locations generate ECC events, either single-bit corrections
or double-bit non-correctable errors that are terminated with an error response.
The enabling of these error generation modes requires the same input enable signal (as that used to enable
single-bit correction reporting) be asserted. This signal is tied to 1 at SoC level and hence reporting of
single-bit memory corrections is always enabled.
Address Base + 0x004A
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
FRC
1BI
FR11
BI
0
0
FRC
NCI
FR1
NCI
0
ERRBIT[
6:0
]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 15-11. ECC Error Generation register (EEGR)
Table 15-12. EEGR field descriptions
Field
Description
2
FRC1BI
Force RAM Continuous 1-Bit Data Inversions
0 No RAM continuous 1-bit data inversions generated
1 1-bit data inversions in the RAM continuously generated
The assertion of this bit forces the RAM controller to create 1-bit data inversions, as defined by the bit
position specified in ERRBIT[6:0], continuously on every write operation.
The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position
defined by ERRBIT is inverted to introduce a 1-bit ECC event in the RAM.
After this bit has been enabled to generate another continuous 1-bit data inversion, it must be cleared
before being set again to properly re-enable the error generation logic.
This bit can only be set if the same input enable signal (as that used to enable single-bit correction
reporting) is asserted. This signal is tied to 1 at SoC level and hence reporting of single-bit memory
corrections is always enabled.
3
FR11BI
Force RAM One 1-bit Data Inversion
0 No RAM single 1-bit data inversion generated
1 One 1-bit data inversion in the RAM generated
The assertion of this bit forces the RAM controller to create one 1-bit data inversion, as defined by the bit
position specified in ERRBIT[6:0], on the first write operation after this bit is set.
The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position
defined by ERRBIT is inverted to introduce a 1-bit ECC event in the RAM.
After this bit has been enabled to generate a single 1-bit data inversion, it must be cleared before being
set again to properly re-enable the error generation logic.
This bit can only be set if the same input enable signal (as that used to enable single-bit correction
reporting) is asserted. This signal is tied to 1 at SoC level and hence reporting of single-bit memory
corrections is always enabled.
