Chapter 12 e200z0 and e200z0h Core
MPC5602P Microcontroller Reference Manual, Rev. 4
Freescale Semiconductor
267
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Instruction buffer with 2 entries in e200z0, each holding a single 32-bit instruction, or a pair of
16-bit instructions
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Dedicated PC incrementer supporting instruction prefetches
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Branch unit with dedicated branch address adder supporting single cycle of execution of certain
branches, two cycles for all others
12.2.1.3
Integer unit features
The e200 integer unit supports single cycle execution of most integer instructions:
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32-bit AU for arithmetic and comparison operations
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32-bit LU for logical operations
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32-bit priority encoder for count leading zero’s function
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32-bit single cycle barrel shifter for shifts and rotates
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32-bit mask unit for data masking and insertion
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Divider logic for signed and unsigned divide in 5 to 34 clocks with minimized execution timing
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8 × 32 hardware multiplier array supports 1 to 4 cycle 32 × 32
32 multiply (early out)
12.2.1.4
Load/Store unit features
The e200 load/store unit supports load, store, and the load multiple / store multiple instructions:
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32-bit effective address adder for data memory address calculations
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Pipelined operation supports throughput of one load or store operation per cycle
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32-bit interface to memory (dedicated memory interface on e200z0h)
12.2.1.5
e200z0h system bus features
The features of the e200z0h System Bus interface are as follows:
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Independent Instruction and Data Buses
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AMBA AHB Lite Rev 2.0 Specification with support for ARM v6 AMBA Extensions
— Exclusive Access Monitor
— Byte Lane Strobes
— Cache Allocate Support
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32-bit address bus plus attributes and control on each bus
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32-bit read data bus for Instruction Interface
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Separate uni-directional 32-bit read data bus and 32-bit write data bus for Data Interface
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Overlapped, in-order accesses
12.2.1.6
Nexus features
The Nexus 1 module is compliant with Class 1 of the IEEE-ISTO 5001-2003 standard. The following
features are implemented:
