Chapter 17 Flash Memory
MPC5602P Microcontroller Reference Manual, Rev. 4
Freescale Semiconductor
317
Finally, the buffers are invalidated by hardware on any non-sequential access with a non-zero value on
haddr[28:24] to support wait state emulation.
17.2.15 Bank1 temporary holding register
Recall the bank1 logic within the Flash includes a single 128-bit data register, used for capturing read data.
Since this bank does not support prefetching, the read data for the referenced address is bypassed directly
back to the AHB data bus. The page is also loaded into the temporary data register and subsequent accesses
to this page can hit from this register, if it is enabled (B1_Py_BFE).
The organization of the temporary holding register is described as follows, in a pseudo-code
representation. The hardware structure includes the buffer address and valid bit, along with 128 bits of
page read data and several error flags and is the same as an individual bank0 page buffer.
struct {
// bk1_page_buffer
reg
addr[23:4];// page address
reg
valid;
// valid bit
reg
rdata[127:0];// page read data
reg
xfr_error;
// transfer error indicator from Flash array
reg
multi_ecc_error;// multi-bit ECC error indicator from Flash array
reg
single_ecc_error;// single-bit correctable ECC indicator from Flash array
}
bk1_page_buffer;
For the general case, a temporary holding register is written at the completion of an error-free Flash access
and the valid bit asserted. Subsequent Flash accesses that “hit” the buffer, that is, the current access address
matches the address stored in the temporary holding register, can be serviced in 0 AHB wait states as the
stored read data is routed from the temporary register back to the requesting bus master.
The contents of the holding register are invalidated by the falling edge transition of bk1_fl_done and on
any non-sequential access with a non-zero value on haddr[28:24] (to support wait state emulation) in the
same manner as the bank0 page buffers. Additionally, the B1_Py_BFE register bit can be cleared by
software to invalidate the contents of the holding register.
As noted in
Section 17.2.13, “Flash error response operation
the temporary holding register is
not
marked
as valid if the Flash array access terminated with any type of transfer error. However, the result is that Flash
array accesses that are tagged with a single-bit correctable ECC event are loaded into the temporary
holding register and validated. Accordingly, one special case needing software invalidation relates to
holding register “hits” on Flash data that was tagged with a single-bit ECC event. Depending on the
specific hardware configuration, the reporting of a single-bit ECC event may generate an ECC alert
interrupt. In order to prevent repeated ECC alert interrupts, the page buffers need to be invalidated by
software after the first notification of the single-bit ECC event.
The bank1 temporary holding register effectively operates like a single page buffer.
17.2.16 Read-While-Write functionality
The platform Flash controller supports various programmable responses for read accesses while the Flash
is busy performing a write (program) or erase operation. For all situations, the platform Flash controller
uses the state of the Flash array’s bk
n
_fl_done output to determine if it is busy performing some type of
high-voltage operation, namely, if bk
n
_fl_done = 0, the array is busy.
