Chapter 18 Enhanced Direct Memory Access (eDMA)
MPC5602P Microcontroller Reference Manual, Rev. 4
Freescale Semiconductor
387
18.5.2
Register descriptions
Read operations on reserved bits in a register return undefined data. Do not write operations to reserved
bits. Writing to reserved bits in a register can generate errors. The maximum register bit-width for this
device is 16 bits wide.
18.5.2.1
eDMA Control Register (EDMA_CR)
The 32-bit EDMA_CR defines the basic operating configuration of the eDMA.
The eDMA arbitrates channel service requests in one group of 16 channels.
Arbitration can be configured to use either fixed-priority or round-robin. In fixed-priority arbitration, the
highest priority channel requesting service is selected to execute. The priorities are assigned by the channel
priority registers. In round-robin arbitration mode, the channel priorities are ignored and the channels are
cycled through, from channel 15 down to channel 0, without regard to priority.
Refer to
Section 18.5.2.16, “eDMA Channel n Priority Registers (EDMA_CPRn).
Address: Base + 0x0000
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0
0
0
0
0
0
0
0
0
0
0
0
0
ERCA EDBG
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 18-2. eDMA Control Register (EDMA_CR)
Table 18-2. EDMA_CR field descriptions
Field
Description
0-28
Reserved.
29
ERCA
Enable round-robin channel arbitration.
0 Fixed-priority arbitration is used for channel selection within each group.
1 Round-robin arbitration is used for channel selection within each group.
30
EDBG
Enable debug.
0 The assertion of the system debug control input is ignored.
1 The assertion of the system debug control input causes the eDMA to stall the start of a new
channel. Executing channels are allowed to complete. Channel execution resumes when either
the system debug control input is negated or the EDBG bit is cleared.
31
Reserved.
