NXP Semiconductors SAFE ASSURE Qorivva MPC5601P, Reference Manual

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Chapter 5 Clock Generation Module (MC_CGM)
MPC5602P Microcontroller Reference Manual, Rev. 4
Freescale Semiconductor 107
• contains a set of registers to control peripheral clock selection
• supports multiple clock sources and maps their address spaces to its memory map
• generates an output clock
• guarantees glitch-less clock transitions when changing the system clock selection
• supports 8, 16 and 32-bit wide read/write accesses
5.3 External Signal Description
The MC_CGM delivers an output clock to the PAD[22] pin for off-chip use and/or observation.
5.4 Memory Map and Register Definition
NOTE
Any access to unused registers as well as write accesses to read-only
registers will not change register content, and cause a transfer error.
Table 5-1. MC_CGM Register Description
Address Name Description Size
Access
Location
User Supervisor Test
0xC3FE
_0370
CGM_OC_EN Output Clock Enable word read read/write read/write on page 112
0xC3FE
_0374
CGM_OCDS_SC Output Clock Division
Select byte read read/write read/write on page 113
0xC3FE
_0378
CGM_SC_SS System Clock Select
Status byte read read read on page 114
0xC3FE
_037C
CGM_SC_DC0 System Clock Divider
Configuration 0 byte read read/write read/write on page 114
0xC3FE
_0380
CGM_AC0_SC Aux Clock 0 Select
Control word read read/write read/write on page 115
0xC3FE
_0384
CGM_AC0_DC0 Aux Clock 0 Divider
Configuration 0 byte read read/write read/write on page 116
0xC3FE
_0388
CGM_AC1_SC Aux Clock 1 Select
Control word read read/write read/write on page 116
0xC3FE
_038C
CGM_AC1_DC0 Aux Clock 1 Divider
Configuration 0 byte read read/write read/write on page 117
0xC3FE
_0390
CGM_AC2_SC Aux Clock 2 Select
Control word read read/write read/write on page 118
0xC3FE
_0394
CGM_AC2_DC0 Aux Clock 2 Divider
Configuration 0 byte read read/write read/write on page 119