NXP Semiconductors SAFE ASSURE Qorivva MPC5601P, Reference Manual

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Chapter 5 Clock Generation Module (MC_CGM)
MPC5602P Microcontroller Reference Manual, Rev. 4
112 Freescale Semiconductor
5.5 Register Descriptions
All registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. The bytes are ordered
according to big endian. For example, the CGM_OC_EN register may be accessed as a word at address
0xC3FE_0370, as a half-word at address 0xC3FE_0372, or as a byte at address 0xC3FE_0373.
5.5.1 Output Clock Enable Register (CGM_OC_EN)
This register is used to enable and disable the output clock.
0xC3FE
_038C
CGM_AC1_D
C0 R
DE0
0 0 0
DIV0
0 0 0 0 0 0 0 0
W
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
0xC3FE
_0390
CGM_AC2_S
C R 0 0 0 0
SELCTL
0 0 0 0 0 0 0 0
W
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
0xC3FE
_0394
CGM_AC2_D
C0 R
DE0
0 0 0
DIV0
0 0 0 0 0 0 0 0
W
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
0xC3FE
_0398
…
0xC3FE
_3FFC
reserved
Address 0xC3FE_0370 Access: User read, Supervisor read/write, Test read/write
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 5-2. Output Clock Enable Register (CGM_OC_EN)
Table 5-2. MC_CGM Memory Map (continued)