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Chapter 17 Flash Memory

MPC5602P Microcontroller Reference Manual, Rev. 4

320

Freescale Semiconductor

shows the relationship of haddr[25:24] to the number of additional wait states. These are

applied in addition to those specified by haddr[28:26] and thus extend the total wait state specification
capability.

17.2.18 Timing diagrams

Since the platform Flash controller is typically used in platform configurations with a cacheless core, the
operation of the processor accesses to the platform memories, for example Flash and SRAM, plays a major
role in the overall system performance. Given the core/platform pipeline structure, the platform’s memory
controllers (PFlash, PRAM) are designed to provide a 0 wait state data phase response to maximize
processor performance. The following diagrams illustrate operation of various cycle types and responses
referenced earlier in this chapter including stall-while-read (

) and terminate-while-read

(

) diagrams.

Table 17-5. Extended additional wait state encoding

Memory address

haddr[25:24]

Additional wait states

(added to those specified by

haddr[28:26])

00

0

01

8

10

16

11

24

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Summary of Contents for SAFE ASSURE Qorivva MPC5601P

Page 1: ...MPC5602P Microcontroller Reference Manual Rev 4 Freescale Semiconductor 1 Qorivva MPC5602P Microcontroller Reference Manual Devices Supported MPC5601P MPC5602P MPC5602PRM Rev 4 28 Feb 2012 ...

Page 2: ...MPC5602P Microcontroller Reference Manual Rev 4 2 Freescale Semiconductor ...

Page 3: ...re and hardware developers and applications programmers who want to develop products with the MPC5602P device It is assumed that the reader understands operating systems microprocessor system design basic principles of software and hardware and basic details of the Power Architecture Chapter organization and device specific information This document includes chapters that describe The device as a ...

Page 4: ...MPC5602P Microcontroller Reference Manual Rev 4 4 Freescale Semiconductor ...

Page 5: ...47 1 6 10 Main oscillator 47 1 6 11 Internal RC oscillator 47 1 6 12 Periodic interrupt timer PIT 48 1 6 13 System timer module STM 48 1 6 14 Software watchdog timer SWT 48 1 6 15 Fault collection unit FCU 48 1 6 16 System integration unit Lite SIUL 49 1 6 17 Boot and censorship 49 1 6 17 1 Boot assist module BAM 49 1 6 18 Error correction status module ECSM 50 1 6 19 Peripheral bridge PBRIDGE 50 ...

Page 6: ...tor 1 83 4 2 5 Auxiliary Clock Selector 2 83 4 2 6 Auxiliary clock dividers 83 4 2 7 External clock divider 83 4 3 Alternate module clock domains 84 4 3 1 FlexCAN clock domains 84 4 3 2 SWT clock domains 84 4 3 3 Cross Triggering Unit CTU clock domains 84 4 3 4 Peripherals behind the IPS bus clock sync bridge 84 4 3 4 1 FlexPWM clock domain 84 4 3 4 2 eTimer_0 clock domain 84 4 3 4 3 ADC_0 clock d...

Page 7: ...L_0 CMU_0_LFREFR_A 102 4 9 4 5 Interrupt Status Register CMU_0_ISR 102 4 9 4 6 Measurement Duration Register CMU_0_MDR 103 Chapter 5 Clock Generation Module MC_CGM 5 1 Overview 105 5 2 Features 106 5 3 External Signal Description 107 5 4 Memory Map and Register Definition 107 5 5 Register Descriptions 112 5 5 1 Output Clock Enable Register CGM_OC_EN 112 5 5 2 Output Clock Division Select Register ...

Page 8: ...1 3 Modes of Operation 131 7 2 External Signal Description 132 7 3 Memory Map and Register Definition 132 7 3 1 Memory Map 133 7 3 2 Register Description 140 7 3 2 1 Global Status Register ME_GS 140 7 3 2 2 Mode Control Register ME_MCTL 142 7 3 2 3 Mode Enable Register ME_ME 143 7 3 2 4 Interrupt Status Register ME_IS 144 7 3 2 5 Interrupt Mask Register ME_IM 145 7 3 2 6 Invalid Mode Transition St...

Page 9: ... 4 3 4 Processor Low Power Mode Entry 166 7 4 3 5 Processor and System Memory Clock Disable 166 7 4 3 6 Clock Sources Switch On 166 7 4 3 7 Flash Modules Switch On 167 7 4 3 8 Pad Outputs On 167 7 4 3 9 Peripheral Clocks Enable 167 7 4 3 10 Processor and Memory Clock Enable 167 7 4 3 11 Processor Low Power Mode Exit 167 7 4 3 12 System Clock Switching 167 7 4 3 13 Pad Switch Off 168 7 4 3 14 Clock...

Page 10: ...ription 191 8 4 1 Reset State Machine 191 8 4 1 1 PHASE0 Phase 192 8 4 1 2 PHASE1 Phase 193 8 4 1 3 PHASE2 Phase 193 8 4 1 4 PHASE3 Phase 193 8 4 1 5 IDLE Phase 193 8 4 2 Destructive Resets 194 8 4 3 External Reset 194 8 4 4 Functional Resets 195 8 4 5 Alternate Event Generation 195 8 4 6 Boot Mode Capturing 196 Chapter 9 Interrupt Controller INTC 9 1 Introduction 197 9 2 Features 197 9 3 Block di...

Page 11: ... 7 2 2 Hardware vector mode 223 9 7 3 ISR RTOS and task hierarchy 223 9 7 4 Order of execution 224 9 7 5 Priority ceiling protocol 225 9 7 5 1 Elevating priority 225 9 7 5 2 Ensuring coherency 225 9 7 6 Selecting priorities according to request rates and deadlines 226 9 7 7 Software configurable interrupt requests 226 9 7 7 1 Scheduling a lower priority portion of an ISR 226 9 7 7 2 Scheduling an ...

Page 12: ...errupt Status Flag Register ISR 246 11 5 2 4 Interrupt Request Enable Register IRER 246 11 5 2 5 Interrupt Rising Edge Event Enable Register IREER 247 11 5 2 6 Interrupt Falling Edge Event Enable Register IFEER 247 11 5 2 7 Interrupt Filter Enable Register IFER 248 11 5 2 8 Pad Configuration Registers PCR 0 71 248 11 5 2 9 Pad Selection for Multiplexed Inputs registers PSMI 0_3 32_35 250 11 5 2 10...

Page 13: ...Chapter 13 Peripheral Bridge PBRIDGE 13 1 Introduction 273 13 1 1 Block diagram 273 13 1 2 Overview 273 13 1 3 Modes of operation 274 13 2 Functional description 274 13 2 1 Access support 274 13 2 1 1 Peripheral Write Buffering 274 13 2 1 2 Read cycles 274 13 2 1 3 Write cycles 274 13 2 2 General operation 274 Chapter 14 Crossbar Switch XBAR 14 1 Introduction 275 14 2 Block diagram 275 14 3 Overvi...

Page 14: ...s 287 15 4 2 10 ECC Configuration Register ECR 288 15 4 2 11 ECC Status Register ESR 289 15 4 2 12 ECC Error Generation Register EEGR 290 15 4 2 13 Flash ECC Address Register FEAR 292 15 4 2 14 Flash ECC Master Number Register FEMR 293 15 4 2 15 Flash ECC Attributes FEAT register 293 15 4 2 16 Flash ECC Data Register FEDR 294 15 4 2 17 RAM ECC Address Register REAR 295 15 4 2 18 RAM ECC Syndrome R...

Page 15: ...h error response operation 314 17 2 14 Bank0 page read buffers and prefetch operation 314 17 2 14 1 Instruction data prefetch triggering 316 17 2 14 2 Per master prefetch triggering 316 17 2 14 3 Buffer allocation 316 17 2 14 4 Buffer invalidation 316 17 2 15 Bank1 temporary holding register 317 17 2 16 Read While Write functionality 317 17 2 17 Wait state emulation 319 17 2 18 Timing diagrams 320...

Page 16: ...vate Censorship Password 0 register NVPWD0 364 17 3 7 17 Non Volatile Private Censorship Password 1 register NVPWD1 364 17 3 7 18 Non Volatile System Censoring Information 0 register NVSCI0 365 17 3 7 19 Non Volatile System Censoring Information 1 register NVSCI1 366 17 3 7 20 Non Volatile User Options register NVUSRO 367 17 3 8 Code Flash programming considerations 368 17 3 8 1 Modify operation 3...

Page 17: ... application information 414 18 7 1 eDMA initialization 414 18 7 2 DMA programming errors 416 18 7 3 DMA request assignments 417 18 7 4 DMA arbitration mode considerations 417 18 7 4 1 Fixed channel arbitration 417 18 7 4 2 Fixed group arbitration round robin channel arbitration 417 18 7 5 DMA transfer 418 18 7 5 1 Single request 418 18 7 5 2 Multiple requests 419 18 7 5 3 Modulo feature 420 18 7 ...

Page 18: ... 441 20 6 2 2 Peripheral Chip Selects 1 3 CS1 3 441 20 6 2 3 Peripheral Chip Select 4 CS4 441 20 6 2 4 Peripheral Chip Select 5 Peripheral Chip Select Strobe CS_5 441 20 6 2 5 Serial Input SIN_x 441 20 6 2 6 Serial Output SOUT_x 441 20 6 2 7 Serial Clock SCK_x 442 20 7 Memory map and registers description 442 20 7 1 Memory map 442 20 7 2 Registers description 443 20 7 2 1 DSPI Module Configuration...

Page 19: ...2 20 8 5 4 Modified SPI transfer format MTFE 1 CPHA 1 473 20 8 5 5 Continuous selection format 474 20 8 5 6 Clock polarity switching between DSPI transfers 475 20 8 6 Continuous Serial communications clock 476 20 8 7 Interrupts DMA requests 478 20 8 7 1 End of queue interrupt request EOQF 478 20 8 7 2 Transmit FIFO fill interrupt or DMA request TFFF 478 20 8 7 3 Transfer complete interrupt request...

Page 20: ...ster UARTCR 503 21 7 1 6 UART mode status register UARTSR 504 21 7 1 7 LIN timeout control status register LINTCSR 506 21 7 1 8 LIN output compare register LINOCR 507 21 7 1 9 LIN timeout control register LINTOCR 508 21 7 1 10 LIN fractional baud rate register LINFBRR 508 21 7 1 11 LIN integer baud rate register LINIBRR 509 21 7 1 12 LIN checksum field register LINCFR 510 21 7 1 13 LIN control reg...

Page 21: ...536 22 3 Memory map and registers description 536 22 3 1 FlexCAN memory mapping 536 22 3 2 Message buffer structure 539 22 3 3 Rx FIFO structure 542 22 3 4 Registers description 544 22 3 4 1 Module Configuration Register MCR 544 22 3 4 2 Control Register CTRL 548 22 3 4 3 Free Running Timer TIMER 551 22 3 4 4 Rx Global Mask register RXGMASK 552 22 3 4 5 Rx 14 Mask RX14MASK 552 22 3 4 6 Rx 15 Mask ...

Page 22: ...hapter 23 Analog to Digital Converter ADC 23 1 Overview 579 23 1 1 Device specific features 579 23 1 2 Device specific pin configuration features 580 23 1 3 Device specific implementation 580 23 2 Introduction 580 23 3 Functional description 581 23 3 1 Analog channel conversion 581 23 3 1 1 Normal conversion 581 23 3 1 2 Start of normal conversion 581 23 3 1 3 Normal conversion operating modes 582...

Page 23: ...ld Control Register TRCx x 0 3 602 23 4 5 3 Threshold Register THRHLR 0 3 603 23 4 6 Conversion Timing Registers CTR 0 604 23 4 7 Mask registers 604 23 4 7 1 Introduction 604 23 4 7 2 Normal Conversion Mask Registers NCMR 0 604 23 4 7 3 Injected Conversion Mask Registers JCMR 0 606 23 4 8 Delay registers 607 23 4 8 1 Power Down Exit Delay Register PDEDR 607 23 4 9 Data registers 607 23 4 9 1 Intro...

Page 24: ...24 8 12 FIFO control register FCR 638 24 8 13 FIFO threshold register FTH 639 24 8 14 FIFO status register FST 640 24 8 15 FIFO Right aligned data x x 0 3 FRx 641 24 8 16 FIFO signed Left aligned data x x 0 3 FLx 642 24 8 17 Cross triggering unit error flag register CTUEFR 642 24 8 18 Cross triggering unit interrupt flag register CTUIFR 643 24 8 19 Cross triggering unit interrupt DMA register CTUI...

Page 25: ... DMA Enable register DMAEN 668 25 6 3 15 Output Trigger Control register TCTRL 669 25 6 3 16 Fault Disable Mapping register DISMAP 670 25 6 3 17 Deadtime Count registers DTCNT0 DTCNT1 670 25 6 4 Configuration registers 671 25 6 4 1 Output Enable register OUTEN 671 25 6 4 2 Mask register MASK 672 25 6 4 3 Software Controlled Output Register SWCOUT 673 25 6 4 4 Deadtime Source Select Register DTSRCS...

Page 26: ...d flag 705 25 9 4 Reload errors 705 25 9 5 Initialization 705 25 10Clocks 706 25 11 Interrupts 706 25 12 DMA 706 Chapter 26 eTimer 26 1 Introduction 709 26 2 Features 709 26 3 Module block diagram 711 26 4 Channel block diagram 712 26 5 External signal descriptions 712 26 5 1 ETC 5 0 eTimer input outputs 712 26 6 Memory map and registers 712 26 6 1 Overview 712 26 6 2 Timer channel registers 716 2...

Page 27: ...734 26 7 2 1 STOP mode 734 26 7 2 2 COUNT mode 734 26 7 2 3 EDGE COUNT mode 735 26 7 2 4 GATED COUNT mode 735 26 7 2 5 QUADRATURE COUNT mode 735 26 7 2 6 SIGNED COUNT mode 735 26 7 2 7 TRIGGERED COUNT mode 735 26 7 2 8 ONE SHOT mode 736 26 7 2 9 CASCADE COUNT mode 736 26 7 2 10 PULSE OUTPUT mode 737 26 7 2 11 FIXED FREQUENCY PWM mode 737 26 7 2 12 VARIABLE FREQUENCY PWM mode 737 26 7 2 13 Usage of...

Page 28: ...3 5 3 SWT Time Out register SWT_TO 756 27 3 5 4 SWT Window Register SWT_WN 756 27 3 5 5 SWT Service Register SWT_SR 757 27 3 5 6 SWT Counter Output register SWT_CO 757 27 3 5 7 SWT Service Key Register SWT_SK 758 27 3 6 Functional description 758 Chapter 28 Fault Collection Unit FCU 28 1 Introduction 761 28 1 1 Overview 761 28 1 1 1 General description 761 28 1 2 Features 764 28 1 3 Modes of opera...

Page 29: ...y map 783 29 4 2 Registers description 784 29 4 2 1 NMI Status Flag Register NSR 784 29 4 2 2 NMI Configuration Register NCR 784 29 5 Functional description 785 29 5 1 General 785 29 5 2 Non Maskable Interrupts 786 29 5 2 1 NMI management 786 Chapter 30 Periodic Interrupt Timer PIT 30 1 Introduction 789 30 1 1 Overview 789 30 1 2 Features 789 30 2 Signal description 790 30 3 Memory map and registe...

Page 30: ...STM Channel Compare Register STM_CMPn 803 31 6 Functional description 804 Chapter 32 Cyclic Redundancy Check CRC 32 1 Introduction 805 32 1 1 Glossary 805 32 2 Main features 805 32 2 1 Standard features 805 32 3 Block diagram 805 32 3 1 IPS bus interface 806 32 4 Functional description 806 32 5 Memory map and registers description 808 32 5 1 CRC Configuration Register CRC_CFG 809 32 5 2 CRC Input ...

Page 31: ...baud feature 830 33 6 1 1 Configuration 831 33 6 1 2 Boot from UART with autobaud enabled 833 33 6 1 3 Boot from FlexCAN with autobaud enabled 837 33 6 2 Interrupt 842 33 7 Censorship 842 33 7 0 1 Censorship password registers NVPWD0 and NVPWD1 842 33 7 0 2 Nonvolatile System Censorship Control registers NVSCI0 and NVSCI1 843 33 7 0 3 Censorship configuration 843 Chapter 34 Voltage Regulators and ...

Page 32: ...ACCESS_AUX_TAP_x instructions 863 35 8 4 3 CLAMP instruction 863 35 8 4 4 EXTEST external test instruction 863 35 8 4 5 HIGHZ instruction 864 35 8 4 6 IDCODE instruction 864 35 8 4 7 SAMPLE instruction 864 35 8 4 8 SAMPLE PRELOAD instruction 864 35 8 5 Boundary scan 864 35 9 e200z0 OnCE controller 865 35 9 1 e200z0 OnCE controller block diagram 865 35 9 2 e200z0 OnCE controller functional descript...

Page 33: ...10 7 Interrupt Taken Debug Event 882 36 10 8 Critical Interrupt Taken Debug Event 882 36 10 9 Return Debug Event 882 36 10 10 Critical Return Debug Event 883 36 10 11 External Debug Event 883 36 10 12 Unconditional Debug Event 883 36 11 Debug Registers 883 36 11 1 Debug Address and Value Registers 884 36 11 2 Debug Control and Status Registers 885 36 11 2 1 Debug Control Register 0 DBCR0 885 36 11...

Page 34: ...19 36 12 7 3 Debug Request During Normal Activity 919 36 12 7 4 Debug Request During Waiting Halted or Stopped State 919 36 12 7 5 Software Request During Normal Activity 920 36 12 8 CPU Status and Control Scan Chain Register CPUSCR 920 36 12 8 1 Instruction Register IR 921 36 12 8 2 Control State Register CTL 922 36 12 8 3 Program Counter Register PC 925 36 12 8 4 Write Back Bus Register WBBRlow ...

Page 35: ...rchitecture technology VLE only design with 32 bit general purpose registers GPRs All arithmetic instructions that execute in the core operate on data in the general purpose registers GPRs Instead of the base Power Architecture instruction set support the e200z0h core only implements the VLE variable length encoding APU providing improved code density The MPC5602P has a single level of memory hier...

Page 36: ...ering EHPS Lower end of electric power steering EPS Airbag applications Anti lock braking systems ABS Motor control applications EHPS and EPS systems typically feature sophisticated and advanced electrical motor control periphery with special enhancements in the area of pulse width modulation highly flexible timers and functional safety 1 2 1 Application examples 1 2 1 1 Electric power steering Fi...

Page 37: ...on Sensor Physical Layer Torque Relay Relay Driver Signal Conditioning Circuitry Driver PWM 3 phase Low Voltage Power Stage PMSM Signal Conditioning Circuitry Driver Reverse Bat Protection Fast ADC 1 µs 10 bit Timer Safety Port Core FlexCAN Faults Motor Control PWM 10 ns res DSPI MPC5602P Vcc Vanalog Vref Vcc Vanalog Vref ID System Basis Chip Windowed Watchdog Hi speed CAN Physical Layer CAN Compl...

Page 38: ...r core 32 bit e200z0h Instruction set VLE variable length encoding CPU performance 0 64 MHz FMPLL frequency modulated phase locked loop module 1 INTC interrupt controller channels 120 PIT periodic interrupt timer 1 with four 32 bit timers eDMA enhanced direct memory access channels 16 FlexCAN controller area network 11 2 21 2 SPI Physical Interface Physical Interface Physical Interface Physical In...

Page 39: ...ave 2 1 Master Slave 1 Master only DSPI deserial serial peripheral interface 1 3 CRC cyclic redundancy check unit Yes Junction temperature sensor No JTAG controller Yes Nexus port controller NPC Yes Nexus Class 1 Supply Digital power supply 3 3 V or 5 V single supply with external transistor Analog power supply 3 3 V or 5 V Internal RC oscillator 16 MHz External crystal oscillator 4 40 MHz Package...

Page 40: ... assist module CRC Cyclic redundancy check CTU Cross triggering unit DSPI Deserial serial peripheral interface ECSM Error correction status module eDMA Enhanced direct memory access eTimer Enhanced timer FCU Fault collection unit Flash Flash memory FlexCAN Controller area network FlexPWM Flexible pulse width modulation FMPLL Frequency modulated phase locked loop INTC Interrupt controller JTAG JTAG...

Page 41: ... single input rail 3 0 V 3 6 V or 4 5 V 5 5 V input supply voltage Configurable pins Selectable slew rate for EMI reduction Selectable pull up pull down or no pull on all pins Selectable open drain Support for 3 3 V or 5 V I O levels 1 5 Chip level features On chip modules available within the family include the following features Up to 64 MHz single issue 32 bit CPU core complex e200z0h Compliant...

Page 42: ...n up to 8 4 4 chip selects 1 FlexCAN interface 2 0B Active with 32 message buffers 1 safety port based on FlexCAN with 32 message buffers and up to 8 Mbit s at 64 MHz capability usable as second CAN when not used as safety port One 10 bit analog to digital converter ADC Up to 16 input channels 16 ch on 100 LQFP and 12 ch on 64 LQFP Conversion time 1 µs including sampling time at full precision Pro...

Page 43: ...rd architecture Hardware vectored interrupt support Reservation instructions for implementing read modify write constructs Long cycle time instructions except for guarded loads do not increase interrupt latency Extensive system development support through Nexus debug port Non maskable interrupt support 1 6 2 Crossbar switch XBAR The XBAR multi port crossbar switch supports simultaneous connections...

Page 44: ...eDMA module provides the following features 16 channels support independent 8 16 or 32 bit single value or block transfers Supports variable sized queues and circular queues Source and destination address registers are independently configured to either post increment or to remain constant Each transfer is initiated by a peripheral CPU or eDMA channel request Each eDMA channel can optionally send ...

Page 45: ...urable access timing allowing use in a wide range of system frequencies Multiple mapping support and mapping based block access timing up to 31 additional cycles allowing use for emulation of other memory types Software programmable block program erase restriction control Erase of selected block s Read page sizes Code flash memory 128 bits 4 words Data flash memory 32 bits 1 word ECC with single b...

Page 46: ... software configurable When multiple tasks share a resource coherent accesses to that resource need to be supported The INTC supports the priority ceiling protocol PCP for coherent accesses By providing a modifiable priority mask the priority can be raised temporarily so that all tasks which share the same resource can not preempt each other The INTC provides the following features Unique 9 bit ve...

Page 47: ...tor output clock divider ratio are all software configurable The FMPLL has the following major features Input clock frequency 4 40 MHz Maximum output frequency 64 MHz Voltage controlled oscillator VCO frequency 256 512 MHz Reduced frequency divider RFD for reduced frequency operation without forcing the FMPLL to relock Frequency modulated PLL Modulation enabled disabled through software Triangle w...

Page 48: ...it up counter with 8 bit prescaler Four 32 bit compare channels Independent interrupt source for each channel Counter can be stopped in debug mode 1 6 14 Software watchdog timer SWT The SWT has the following features 32 bit time out register to set the time out period Programmable selection of window mode or regular servicing Programmable selection of reset or interrupt on an initial time out Mast...

Page 49: ...rpose input or output pins ADC channels support alternative configuration as general purpose inputs Direct readback of the pin value is supported on all pins through the SIUL Configurable digital input filter that can be applied to some general purpose input pins for noise elimination Up to 4 internal functions can be multiplexed onto 1 pin 1 6 17 Boot and censorship Different booting modes are av...

Page 50: ...the generation of double bit memory errors are enabled on the MPC5602P The sources of the ECC errors are Flash memory SRAM 1 6 19 Peripheral bridge PBRIDGE The PBRIDGE implements the following features Duplicated periphery Master access privilege level per peripheral per master read access enable write access enable Write buffering for peripherals Checker applied on PBRIDGE output toward periphery...

Page 51: ...ID or message buffer number Internal arbitration to guarantee no inner or outer priority inversion Transmit abort procedure and notification Receive features Individual programmable filters for each mailbox 8 mailboxes configurable as a 6 entry receive FIFO 8 programmable acceptance filters for receive FIFO Programmable clock source System clock Direct oscillator clock to avoid PLL jitter 1 6 21 S...

Page 52: ... slave mode features Autonomous LIN header handling Autonomous LIN response handling Optional discarding of irrelevant LIN responses using ID filter UART mode Full duplex operation Standard non return to zero NRZ mark space format Data buffers with 4 byte receive 4 byte transmit Configurable word length 8 bit or 9 bit words Error detection and flagging Parity Noise and Framing errors Interrupt dri...

Page 53: ...t AC motors PMAC both brushless BLDC and brush DC motors BDC switched SRM and variable reluctance motors VRM and stepper motors The FlexPWM block implements the following features 16 bit resolution for center edge aligned and asymmetrical PWMs Clock frequency same as that used for e200z0h core PWM outputs can operate as complementary pairs or independent channels Can accept signed numbers for PWM ...

Page 54: ...ing features Clock frequency same as that used for the e200z0h core Individual channel capability Input capture trigger Output compare Double buffer to capture rising edge and falling edge Separate prescaler for each counter Selectable clock source 0 100 pulse measurement Rotation direction flag quad decoder mode Maximum count rate External event counting max count rate peripheral clock 2 Internal...

Page 55: ...eration Motor Control mode or Regular mode Regular mode features Register based interface with the CPU control register status register and 1 result register per channel ADC state machine managing 3 request flows regular command hardware injected command and software injected command Selectable priority between software and hardware injected commands DMA compatible interface CTU controlled mode fe...

Page 56: ...opment support interface for this device The NDI block interfaces to the host processor and internal busses to provide development support as per the IEEE ISTO 5001 2003 Nexus Class 1 standard The development support provided includes access to the MCU s internal memory map and access to the processor s internal registers The NDI provides the following features Configured via the IEEE 1149 1 All N...

Page 57: ...at controls the operation of the data registers instruction register and associated circuitry 1 6 31 On chip voltage regulator VREG The on chip voltage regulator module provides the following features Uses external NPN negative positive negative transistor Regulates external 3 3 V 5 0 V down to 1 2 V for the core logic Low voltage detection on the internal 1 2 V and I O voltage 3 3 V 1 7 Developer...

Page 58: ...Chapter 1 Introduction MPC5602P Microcontroller Reference Manual Rev 4 58 Freescale Semiconductor 64 pin LQFP 0 5 mm pitch 10 mm 10 mm outline 100 pin LQFP 0 5 mm pitch 14 mm 14 mm outline ...

Page 59: ..._FFFF 4080 Reserved 0x0080_0000 0x0080_FFFF 64 Data Flash Array 0 0x0081_0000 0x00C0_1FFF 4040 Reserved 0x00C0_2000 0x00C0_3FFF 8 Data Flash Array 0 Test Sector 0x00C0_4000 0x00FF_FFFF 4080 Reserved 0x0100_0000 0x1FFF_FFFF 507904 Flash Emulation Mapping 0x2000_0000 0x3FFF_FFFF 524288 Reserved 0x4000_0000 0x4000_4FFF 20 SRAM 0x4000_5000 0xC3F8_0000 1048536 Reserved On chip peripherals 0xC3F8_0000 0...

Page 60: ... 16 LINFlex_0 0xFFE4_4000 0xFFE4_7FFF 16 LINFlex_1 0xFFE5_0000 0xFFE6_7FFF 128 Reserved 0xFFE6_8000 0xFFE6_BFFF 16 Cyclic Redundancy Check CRC 0xFFE6_C000 0xFFE6_FFFF 16 Fault Collection Unit FCU 0xFFE7_0000 0xFFE7_FFFF 64 Reserved 0xFFE8_0000 0xFFEF_FFFF 512 Mirrored range 0xC3F8_0000 0xC3FF_FFFF 0xFFF0_0000 0xFFF3_7FFF 224 Reserved 0xFFF3_8000 0xFFF3_BFFF 16 Software Watchdog SWT_0 0xFFF3_C000 0...

Page 61: ...0 0 0xFFFD_FFF F 16 DMA Multiplexer DMA_MUX 0xFFFE_0000 0xFFFE_7FFF 32 Reserved 0xFFFE_8000 0xFFFE_BFF F 16 Safety Port FlexCAN 0xFFFE_C00 0 0xFFFF_BFFF 64 Reserved 0xFFFF_C000 0xFFFF_FFFF 16 Boot Assist Module BAM 1 This address space contains also VREG registers See Chapter 34 Voltage Regulators and Power Supplies Table 2 1 Memory map continued Start address End address Size KB Region name ...

Page 62: ...Chapter 2 MPC5602P Memory Map MPC5602P Microcontroller Reference Manual Rev 4 62 Freescale Semiconductor ...

Page 63: ...0 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NMI A 6 D 1 A 7 C 4 A 8 C 5 A 5 C 7 C 3 N C N C VDD_HV_IO1 VSS_HV_IO1 D 9 VDD_HV_OSC VSS_HV_OSC XTAL EXTAL RESET D 8 D 5 D 6 VSS_LV_COR0 VDD_LV_COR0 A 4 VPP_TEST D 14 C 14 C 13 D 12 N C N C D 13 VSS_LV_COR1 VDD_LV_COR1 A 3 VDD_HV_IO2 VSS_HV_IO2 TDO TCK TMS TDI A...

Page 64: ...for the MPC5602P devices 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 NMI A 6 A 7 A 8 A 5 VDD_HV_IO1 VSS_HV_IO1 D 9 VDD_HV_OSC VSS_HV_OSC XTAL EXTAL RESET D 8 VSS_LV_COR0 VDD_LV_COR0 A 4 VPP_TEST D 14 D 12 D 13 VSS_LV_COR1 VDD_LV_COR1 A 3 VDD_HV_IO2 VSS_HV_IO2 T...

Page 65: ...62 VDD_HV_IO3 Input output supply voltage and code Flash memory supply voltage 55 87 VSS_HV_IO3 Input output ground and code Flash memory HV ground 56 88 VDD_HV_OSC Crystal oscillator amplifier supply voltage 9 16 VSS_HV_OSC Crystal oscillator amplifier ground 10 17 Power supply pins 1 2 V Pins available on 64 pin and 100 pin packages VDD_LV_COR0 1 2 V supply pins for core logic and PLL Decoupling...

Page 66: ...channels with controlled current to reduce electromagnetic emission Fast pads provide maximum speed They are used for improved NEXUS debugging capability Table 3 2 System pins Symbol Description Direction Pad speed1 1 SRC values refer to the value assigned to the Slew Rate Control bits of the pad configuration register Pin SRC 0 SRC 1 64 pin 100 pin Dedicated pins NMI Non maskable Interrupt Input ...

Page 67: ... O I O I O O I Slow Medium 51 A 1 PCR 1 ALT0 ALT1 ALT2 ALT3 GPIO 1 ETC 1 SOUT F 1 EIRQ 1 SIUL eTimer_0 DSPI_2 FCU_0 SIUL I O I O O O I Slow Medium 52 A 2 PCR 2 ALT0 ALT1 ALT2 ALT3 GPIO 2 ETC 2 A 3 SIN ABS 0 EIRQ 2 SIUL eTimer_0 FlexPWM_0 DSPI_2 MC_RGM SIUL I O I O O I I I Slow Medium 57 A 3 PCR 3 ALT0 ALT1 ALT2 ALT3 GPIO 3 ETC 3 CS0 B 3 ABS 1 EIRQ 3 SIUL eTimer_0 DSPI_2 FlexPWM_0 MC_RGM SIUL I O I...

Page 68: ...M_0 SIUL I O I O O O I Slow Medium 52 81 A 11 PCR 11 ALT0 ALT1 ALT2 ALT3 GPIO 11 SCK A 0 A 2 EIRQ 10 SIUL DSPI_2 FlexPWM_0 FlexPWM_0 SIUL I O I O O O I Slow Medium 53 82 A 12 PCR 12 ALT0 ALT1 ALT2 ALT3 GPIO 12 SOUT A 2 B 2 EIRQ 11 SIUL DSPI_2 FlexPWM_0 FlexPWM_0 SIUL I O O O O I Slow Medium 54 83 A 13 PCR 13 ALT0 ALT1 ALT2 ALT3 GPIO 13 B 2 SIN FAULT 0 EIRQ 12 SIUL FlexPWM_0 DSPI_2 FlexPWM_0 SIUL I...

Page 69: ...m 50 77 B 2 PCR 18 ALT0 ALT1 ALT2 ALT3 GPIO 18 TXD DEBUG 2 EIRQ 17 SIUL LIN_0 SSCM SIUL I O O I Slow Medium 51 79 B 3 PCR 19 ALT0 ALT1 ALT2 ALT3 GPIO 19 DEBUG 3 RXD SIUL SSCM LIN_0 I O I Slow Medium 80 B 6 PCR 22 ALT0 ALT1 ALT2 ALT3 GPIO 22 CLKOUT CS2 EIRQ 18 SIUL Control DSPI_2 SIUL I O O O I Slow Medium 62 96 B 7 PCR 23 ALT0 ALT1 ALT2 ALT3 GPIO 23 AN 0 RXD SIUL ADC_0 LIN_0 Input only 20 29 B 8 P...

Page 70: ...ALT0 ALT1 ALT2 ALT3 GPIO 28 AN 14 SIUL ADC_0 Input only 27 38 B 13 PCR 29 ALT0 ALT1 ALT2 ALT3 GPIO 29 AN 6 emu AN 0 RXD SIUL ADC_0 emu ADC_16 LIN_1 Input only 30 42 B 14 PCR 30 ALT0 ALT1 ALT2 ALT3 GPIO 30 AN 7 emu AN 1 ETC 4 EIRQ 19 SIUL ADC_0 emu ADC_16 eTimer_0 SIUL Input only 44 B 15 PCR 31 ALT0 ALT1 ALT2 ALT3 GPIO 31 AN 8 emu AN 2 EIRQ 20 SIUL ADC_0 emu ADC_16 SIUL Input only 43 Table 3 3 Pin ...

Page 71: ... I O O O I Slow Medium 10 C 4 PCR 36 ALT0 ALT1 ALT2 ALT3 GPIO 36 CS0 X 1 DEBUG 4 EIRQ 22 SIUL DSPI_0 FlexPWM_0 SSCM SIUL I O I O O I Slow Medium 5 C 5 PCR 37 ALT0 ALT1 ALT2 ALT3 GPIO 37 SCK DEBUG 5 EIRQ 23 SIUL DSPI_0 SSCM SIUL I O I O I Slow Medium 7 C 6 PCR 38 ALT0 ALT1 ALT2 ALT3 GPIO 38 SOUT B 1 DEBUG 6 EIRQ 24 SIUL DSPI_0 FlexPWM_0 SSCM SIUL I O O O I Slow Medium 98 C 7 PCR 39 ALT0 ALT1 ALT2 A...

Page 72: ...2 I O I O O Slow Medium 33 55 C 12 PCR 44 ALT0 ALT1 ALT2 ALT3 GPIO 44 ETC 5 CS3 SIUL eTimer_0 DSPI_2 I O I O O Slow Medium 34 56 C 13 PCR 45 ALT0 ALT1 ALT2 ALT3 GPIO 45 EXT_IN EXT_SYNC SIUL CTU_0 FlexPWM_0 I O I I Slow Medium 71 C 14 PCR 46 ALT0 ALT1 ALT2 ALT3 GPIO 46 EXT_TGR SIUL CTU_0 I O O Slow Medium 72 C 15 PCR 47 ALT0 ALT1 ALT2 ALT3 GPIO 47 A 1 EXT_IN EXT_SYNC SIUL FlexPWM_0 CTU_0 FlexPWM_0 ...

Page 73: ...m 22 D 6 PCR 54 ALT0 ALT1 ALT2 ALT3 GPIO 54 CS2 FAULT 1 SIUL DSPI_0 FlexPWM_0 I O O I Slow Medium 23 D 7 PCR 55 ALT0 ALT1 ALT2 ALT3 GPIO 55 CS3 F 1 CS4 SIUL DSPI_1 FCU_0 DSPI_0 I O O O O Slow Medium 17 26 D 8 PCR 56 ALT0 ALT1 ALT2 ALT3 GPIO 56 CS2 CS5 SIUL DSPI_1 DSPI_0 I O O O Slow Medium 14 21 D 9 PCR 57 ALT0 ALT1 ALT2 ALT3 GPIO 57 X 0 TXD SIUL FlexPWM_0 LIN_1 I O O O Slow Medium 8 15 D 10 PCR 5...

Page 74: ...LT2 ALT3 GPIO 63 AN 10 emu AN 4 SIUL ADC_0 emu ADC_16 Input only 41 Port E 16 bit E 1 PCR 65 ALT0 ALT1 ALT2 ALT3 GPIO 65 AN 4 SIUL ADC_0 Input only 18 27 E 2 PCR 66 ALT0 ALT1 ALT2 ALT3 GPIO 66 AN 5 SIUL ADC_0 Input only 23 32 E 3 PCR 67 ALT0 ALT1 ALT2 ALT3 GPIO 67 AN 6 SIUL ADC_0 Input only 30 42 E 4 PCR 68 ALT0 ALT1 ALT2 ALT3 GPIO 68 AN 7 SIUL ADC_0 Input only 44 E 5 PCR 69 ALT0 ALT1 ALT2 ALT3 GP...

Page 75: ...e one of the input functions the PCR IBE bit must be written to 1 regardless of the values selected in the PCR PA bitfields For this reason the value corresponding to an input only function is reported as 3 Module included on the MCU 4 Multiple inputs are routed to all respective modules internally The input of some modules must be configured by setting the values of the PSMIO PADSELx bitfields in...

Page 76: ..._2 CTU PWM_EVEN_2 OUT_TRIG1 sub module 2 PWM PWMX2 CTU PWM_REAL_2 PWM OUT_TRIG0_3 CTU PWM_ODD_3 OUT_TRIG0 sub module 3 PWM OUT_TRIG1_3 CTU PWM_EVEN_3 OUT_TRIG1 sub module 3 PWM PWMX3 CTU PWM_REAL_3 External pins PWMA0 PWMB0 PWMA1 PWMB1 PWMA2 PWMB2 PWMA3 PWMB3 Master reload FAULT0 FAULT1 OUT_TRIG0_0 OUT_TRIG0_1 OUT_TRIG0_2 OUT_TRIG0_3 OUT_TRIG1_0 OUT_TRIG1_1 OUT_TRIG1_2 OUT_TRIG1_3 PWMX0 PWMX1 PWMX...

Page 77: ...ADC_0 through CTU ADC IP Interface CTU TRIGGER_1 Virtual ADC_1 through CTU ADC IP Interface CTU ADC_CMD_0 ADC_0 through CTU ADC IP Interface 16 bit signal CTU ADC_CMD_1 Virtual ADC_1 through CTU ADC IP Interface 16 bit signal CTU EXT_TGR SIU lite ADC_0 EOC CTU NEXT_CMD_0 End Of Conversion should be used as next command request signal Virtual ADC_1 EOC CTU NEXT_CMD_1 through CTU ADC IP Interface En...

Page 78: ...8 Freescale Semiconductor SIU lite PWM EXT_SYNC The same GPIO pin as used for CTU EXT_IN and the PWM EXT_SYNC SIU lite PWM FAULT0 SIU lite PWM FAULT1 DSPI_1 SCK eTimer_0 AUX_2 Table 3 4 CTU ADC FlexPWM eTimer connections continued Source module Signal Target module Signal Comment ...

Page 79: ...llator High Frequency RC Oscillator IRC see Section 4 6 IRC 16 MHz internal RC oscillator RC_CTL FMPLL FMPLL_0 see Section 4 8 Frequency Modulated Phase Locked Loop FMPLL CMU CMU_0 see Section 4 9 Clock Monitor Unit CMU Periodic Interrupt Timer PIT see Chapter 30 Periodic Interrupt Timer PIT System Timer Module STM_0 see Chapter 31 System Timer Module STM Software Watchdog Timer SWT_0 see Section ...

Page 80: ...AUX Clock Selector 1 0 2 4 5 8 System Clock Selector 0 RC Oscillator IRC Oscillator XOSC40 N C IRC_CLK 16 MHz SYS_CLK 64 MHz 50 IRC_CLK 16 MHz XOSC_CLK 8 MHz 50 Clockout 30 32 MHz 1 2 4 8 Clock Out Selector 0 1 2 3 1 2 3 16 1 2 3 16 0 2 4 5 8 AUX Clock Selector 2 XOSC_CLK 8 MHz 50 FMPLL_0_PCS_CLK FMPLL_0_CLK NOTE FlexRay protocol clock does not support IRC as a clock source FMPLL_0_CLK XOSC_CLK IR...

Page 81: ..._CLK eTimer_0 FlexPWM ADC_0 Module Clock DMA Support CTU SYS_CLK MC_CLK DSPI_0 DSPI_1 DSPI_2 CTU Trigger Output CTU Sync Event Input Legend BIU IPS SYS_CLK BIU MC_CLK Module Clock BIU MC_CLK Module Clock BIU MC_CLK Protocol Clock Module Clock BIU Module Clock BIU SYS_CLK Module Clock BIU SYS_CLK Module Clock BIU SYS_CLK SP_CLK IPS MC_CLK IPS MC_CLK IPS MC_CLK IPS SP_CLK NOTE MC_CLK and SP_CLK are ...

Page 82: ...S_CLK from clock signals SYS_CLK SYS_CLK SYS_CLK SYS_CLK SYS_CLK SYS_CLK SYS_CLK IRCOSC_CLK SYS_CLK IRCOSC_CLK XOSC_CLK SYS_CLK IPS SYS_CLK IPS SYS_CLK LINFlex_0 Module clock BIU LINFlex_1 Module clock BIU DMA Mux Module clock BIU eDMA2 Module clock BIU INTC Module clock BIU SWT Module clock Protocol clock BIU FlexCAN Module clock Protocol clock BIU FCU Module clock Protocol clock BIU STM Module c...

Page 83: ...register in MC_CGM CGM_AC1_SC has been implemented through which user can select any clock source from the given auxiliary clock sources As there is no auxiliary clock all the auxiliary clock sources have been tied to 0 4 2 5 Auxiliary Clock Selector 2 There is no Auxiliary Clock present on MPC5602P device but to maintain the software compatibility corresponding register in MC_CGM CGM_AC2_SC has b...

Page 84: ... two clock domains in the FlexCAN modules Refer to Chapter 22 FlexCAN for more information on the FlexCAN modules 4 3 2 SWT clock domains The SWT module has two distinct clock domains The first clock domain Module Clock is always supplied from the SYS_CLK This clock domain includes the register interface The source for the second clock domain Protocol Clock is always the IRC generated by the inter...

Page 85: ... and the HALT modes These two modes allow to put the device into a power saving mode with the configuration options defined in the ME module The following constraints are applied on MPC5602P to guarantee that in all modes of operation a resume from STOP or HALT mode is always possible without the need to reset STOP and HALT mode SIUL clock is not gateable SIUL filter for external interrupt capable...

Page 86: ...eset the test flash memory value is not visible at RC_CTL RCTRIM and this field shows a value of zero Therefore be aware that the RC_CTL RCTRIM field does not reflect the current trim value until you have written to it Pay particular attention to this feature when you initiate a read modify write operation on RC_CTL because a RCTRIM value of zero may be unintentionally written back and this may al...

Page 87: ...ock available status After system reset the oscillator is put to power down state and software has to switch on when required Whenever the crystal oscillator is switched on from off state OSCCNT counter starts and when it reaches the value EOCV 7 0 512 oscillator clock is made available to the system Also an interrupt pending bit I_OSC of OSC_CTL register is set An interrupt will be generated if t...

Page 88: ...set this bit System reset is needed to reset this bit 0 Oscillator output is used as root clock 1 EXTAL is used as root clock EOCV 7 0 End of Count Value These bits specify the end of count value to be used for comparison by the oscillator stabilization counter OSCCNT after reset or whenever it is switched on from the off state This counting period ensures that external oscillator clock signal is ...

Page 89: ... 4 6 Figure 4 6 FMPLL block diagram 4 8 3 Features The FMPLL has the following major features Input clock frequency 4 40 MHz Voltage controlled oscillator VCO range from 256 MHz to 512 MHz Reduced frequency divider RFD for reduced frequency operation without forcing the FMPLL to relock Frequency modulated PLL Modulation enabled disabled through software Triangle wave modulation Programmable modula...

Page 90: ...BASE1 FMPLL_0 0xC3FE_00A0 1 FMPLL_x are mapped through the ME_CGM Register Slot Register Access Reset value Location 0x0000 CR Control Register R W 0x0080_0000 on page 90 0x0004 MR Modulation register R W 0x0080_0000 on page 92 0x0004 0x000F Reserved Address Base 0x0000 FMPLL_0 0xC3FE_00A0 Access Supervisor read write User read only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 IDF 3 0 ODF 1 0 0 NDI...

Page 91: ...0000 0011111 Reserved 0100000 Divide by 32 0100001 Divide by 33 0100010 Divide by 34 1011111 Divide by 95 1100000 Divide by 96 1100001 1111111 Reserved en_pll_sw This bit is used to enable progressive clock switching After the PLL locks the PLL output initially is divided by 8 and then progressively decreases until it reaches divide by 1 Note The PLL output should not be used if a non changing clo...

Page 92: ...4 8 Modulation Register MR Table 4 7 MR field descriptions Field Description STRB_BYPASS Strobe bypass The STRB_BYPASS signal bypasses the STRB signal used inside the PLL to latch the correct values for control bits INC_STEP MOD_PERIOD and SPRD_SEL 0 STRB latches the PLL modulation control bits 1 STRB is bypassed In this case the control bits need to be static The control bits must be changed only...

Page 93: ...in turn voltage regulator response is improved This feature can be enabled by programming bit en_pll_sw in the CR Then when the PLL is selected as the system clock the output clock progressively increases its frequency as shown in Table 4 8 FM_EN Frequency modulation enable The FM_EN bit enables the frequency modulation 0 Frequency Modulation disabled 1 Frequency Modulation enabled INC_STEP Increm...

Page 94: ...n parameters are latched in the PLL only when the strobe signal goes high The strobe signal is automatically generated in the FMPLL when the modulation is enabled SSCG_EN goes high if the PLL is locked s_lock 1 or when the modulation has been enabled SSCG_EN 1 and PLL enters in lock state s_lock goes high If STRB_BYPASS is high the strobe signal is bypassed In this case control bits MOD_PERIOD 12 ...

Page 95: ...rror in modulation depth 2 00278 2 0 0 00278 Eqn 4 7 If we choose MODPERIOD 41 INCSTEP Round 215 1 2 64 100 5 41 Round 204 878 205 Eqn 4 8 MODPERIOD INCSTEP 41 205 8405 which is less than 215 Eqn 4 9 md quantized 41 205 100 5 215 1 64 2 00397 peak Eqn 4 10 Error in modulation depth 2 00397 2 0 0 00397 Eqn 4 11 The above calculations show that the quantization error in the modulation depth depends ...

Page 96: ..._SEL can be modified only when PLL is in power down mode Use progressive clock switching 4 9 Clock Monitor Unit CMU 4 9 1 Overview The Clock Monitor Unit CMU serves three purposes PLL clock monitoring detects if PLL leaves an upper or lower frequency boundary XOSC clock monitoring monitor the XOSC clock which must be greater than the IRCOSC clock divided by a division factor given by CMU_CSR RCDIV...

Page 97: ... from the low frequency internal RC oscillator CK_PLL clock coming from the PLL fXOSC frequency of external crystal oscillator clock fRC frequency of low frequency internal RC oscillator fPLL frequency of FMPLL clock 4 9 3 1 Crystal clock monitor If fXOSC is smaller than fRC divided by 2RCDIV bits of CMU_0_CSR and the CK_XOSC is ON and stable as signaled by the ME then An event pending bit OLRI in...

Page 98: ...e CMU_LFREFR and the CK_PLL is ON and the PLL locked as signaled by the ME then An event pending bit FLLI_0 in the CMU_0_ISR is set A failure event FLL is signaled to the RGM and FCU which in turn can generate either an interrupt a reset or a SAFE mode request NOTE It is possible for either the XOSC or PLL monitors to produce a false event when the XOSC or PLL frequency is too close to RC 2RCDIV f...

Page 99: ...C The measure starts when bit SFM Start Frequency Measure in the CMU_CSR is set to 1 The measurement duration is given by the CMU_MDR in numbers of IRC clock cycles with a width of 20 bits Bit SFM is reset to 0 by hardware once the frequency measurement is done and the count is loaded in the CMU_FDR The frequency fRC can be derived from the value loaded in the CMU_FDR as follows fRC fOSC MD n Eqn ...

Page 100: ...Field Description SFM Start frequency measure The software can only set this bit to start a clock frequency measure It is reset by hardware when the measure is ready in the CMU_FDR 0 Frequency measurement completed or not yet started 1 Frequency measurement not completed RCDIV 1 0 RC clock division factor These bits specify the RC clock division factor The output clock is CK_IRC divided by the fac...

Page 101: ...cription FD 19 0 Measured frequency bits This register displays the measured frequency fRC with respect to fOSC The measured value is given by the following formula fRC fOSC MD n where n is the value in CMU_FDR Address Base 0x0008 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 2...

Page 102: ...ese bits determine the low reference value for the FMPLL_0 The reference value is given by LFREF_A 11 0 16 fRC 4 Address Base 0x0010 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 FLCI _0 FHHI _0 FLLI _0 OLRI W w1c w1c w1c w1c Reset 0 0 0...

Page 103: ...nding OLRI Oscillator frequency less than RC frequency event This bit is set by hardware when the frequency of CK_XOSC is less than CK_IRC 2RCDIV frequency and CK_XOSC is ON and stable as signaled by the ME It can be cleared by software by writing 1 0 No OLR event 1 OLR event pending Address Base 0x0018 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 MD 19 16...

Page 104: ...Chapter 4 Clock Description MPC5602P Microcontroller Reference Manual Rev 4 104 Freescale Semiconductor ...

Page 105: ...system clock The MC_ME controls the system clock selection see the MC_ME chapter for more details Peripheral clock selection is controlled by MC_CGM control registers A set of MC_CGM registers controls the clock dividers which are used for divided system and peripheral clock generation The memory spaces of system and peripheral clock sources which have addressable memory spaces are accessed throug...

Page 106: ...disables the system clock supply from system clock sources according to MC_ME control contains a set of registers to control clock dividers for divided clock generation Output Clock Selector Divider Registers Platform Interface core MC_CGM Figure 5 1 MC_CGMBlock Diagram MC_ME Auxiliary Clock Selector Divider System Clock Multiplexer Divider XOSC0 PLL0 16 MHz_IRC Mapped Modules Interface mapped per...

Page 107: ... Location User Supervisor Test 0xC3FE _0370 CGM_OC_EN Output Clock Enable word read read write read write on page 112 0xC3FE _0374 CGM_OCDS_SC Output Clock Division Select byte read read write read write on page 113 0xC3FE _0378 CGM_SC_SS System Clock Select Status byte read read read on page 114 0xC3FE _037C CGM_SC_DC0 System Clock Divider Configuration 0 byte read read write read write on page 1...

Page 108: ...ap 0xC3FE _0000 0xC3FE _001C XOSC registers 0xC3FE _0020 0xC3FE _003C reserved 0xC3FE _0040 0xC3FE _005C reserved 0xC3FE _0060 0xC3FE _007C IRCOSC registers 0xC3FE _0080 0xC3FE _009C reserved 0xC3FE _00A0 0xC3FE _00BC PLL0 registers 0xC3FE _00C0 0xC3FE _00DC reserved 0xC3FE _00E0 0xC3FE _00FC reserved 0xC3FE _0100 0xC3FE _011C CMU0 registers ...

Page 109: ...FE _013C reserved 0xC3FE _0140 0xC3FE _015C reserved 0xC3FE _0160 0xC3FE _017C reserved 0xC3FE _0180 0xC3FE _019C reserved 0xC3FE _01A0 0xC3FE _01BC reserved 0xC3FE _01C0 0xC3FE _01DC reserved 0xC3FE _01E0 0xC3FE _01FC reserved 0xC3FE _0200 0xC3FE _021C reserved 0xC3FE _0220 0xC3FE _023C reserved Table 5 2 MC_CGM Memory Map continued ...

Page 110: ...FE _025C reserved 0xC3FE _0260 0xC3FD _C27C reserved 0xC3FE _0280 0xC3FE _029C reserved 0xC3FE _02A0 0xC3FE _02BC reserved 0xC3FE _02C0 0xC3FE _02DC reserved 0xC3FE _02E0 0xC3FE _02FC reserved 0xC3FE _0300 0xC3FE _031C reserved 0xC3FE _0320 0xC3FE _033C reserved 0xC3FE _0340 0xC3FE _035C reserved Table 5 2 MC_CGM Memory Map continued ...

Page 111: ...0 0 0 0 0 0 0 W 0xC3FE _0378 CGM_SC_SS R 0 0 0 0 SELSTAT 0 0 0 0 0 0 0 0 W R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W 0xC3FE _037C CGM_SC_DC 0 R DE0 0 0 0 DIV0 0 0 0 0 0 0 0 0 W R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W 0xC3FE _0380 CGM_AC0_S C R 0 0 0 0 SELCTL 0 0 0 0 0 0 0 0 W R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W 0xC3FE _0384 CGM_AC0_D C0 R DE0 0 0 0 DIV0 0 0 0 0 0 0 0 0 W R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W ...

Page 112: ...r is used to enable and disable the output clock 0xC3FE _038C CGM_AC1_D C0 R DE0 0 0 0 DIV0 0 0 0 0 0 0 0 0 W R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W 0xC3FE _0390 CGM_AC2_S C R 0 0 0 0 SELCTL 0 0 0 0 0 0 0 0 W R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W 0xC3FE _0394 CGM_AC2_D C0 R DE0 0 0 0 DIV0 0 0 0 0 0 0 0 0 W R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W 0xC3FE _0398 0xC3FE _3FFC reserved Address 0xC3FE_0370 Access...

Page 113: ... 0 0 0 0 0 0 0 0 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 3 Output Clock Division Select Register CGM_OCDS_SC Table 5 4 Output Clock Division Select Register CGM_OCDS_SC Field Descriptions Field Description SELDIV Output Clock Division Select 00 output selected Output Clock without division 01 output selected Output Clock divided by 2 10 output selected ...

Page 114: ...System Clock Select Status Register CGM_SC_SS Field Descriptions Field Description SELSTAT System Clock Source Selection Status This value indicates the current source for the system clock 0000 16 MHz int RC osc 0001 reserved 0010 4 MHz crystal osc 0011 reserved 0100 system PLL 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 rese...

Page 115: ...k If the DE0 is set to 0 Divider 0 is disabled any write access to the DIV0 field is ignored and the divided system clock 0 remains disabled Address 0xC3FE_0380 Access User read Supervisor read write Test read write R 0 0 0 0 SELCTL 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 6 Auxiliary Clock 0 Select C...

Page 116: ...set 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 7 Auxiliary Clock 0 Divider Configuration Register CGM_AC0_DC0 Table 5 8 Auxiliary Clock 0 Divider Configuration Register CGM_AC0_DC0 Field Descriptions Field Description DE0 Divider 0 Enable 0 Disable auxiliary clock 0 divider 0 1 Enable auxiliary clock 0 divider 0 DIV0 Divider 0 Division Value The resultant unused will have a period DIV0 1 times that ...

Page 117: ... 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved Address 0xC3FE_038C Access User read Supervisor read write Test read write R DE0 0 0 0 DIV0 0 0 0 0 0 0 0 0 W Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 9 Auxiliary Clock 1 Divider Configuration Register CGM_AC1_DC0 Table 5 10 Auxiliary Clock 1 Divide...

Page 118: ...SELCTL 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 10 Auxiliary Clock 2 Select Control Register CGM_AC2_SC Table 5 11 Auxiliary Clock 2 Select Control Register CGM_AC2_SC Field Descriptions Field Description SELCTL Auxiliary Clock 2 Source Selection Control This value selects the current source for auxil...

Page 119: ...MHz int RC osc as the system clock and to ignore the system clock select Address 0xC3FE_0394 Access User read Supervisor read write Test read write R DE0 0 0 0 DIV0 0 0 0 0 0 0 0 0 W Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 11 Auxiliary Clock 2 Divider Configuration Register CGM_AC2_DC0 Table 5 12 Auxiliary Clock 2 Div...

Page 120: ...e divided system clock 0 controlled by the CGM_SC_DC0 register 5 8 Auxiliary Clock Generation Figure 5 13 shows the block diagram of the auxiliary clock generation logic See Section 5 5 5 Auxiliary Clock 0 Select Control Register CGM_AC0_SC Section 5 5 7 Auxiliary Clock 1 Select Control Register CGM_AC1_SC and Section 5 5 9 Auxiliary Clock 2 Select Control Register CGM_AC2_SC for auxiliary clock s...

Page 121: ...P Microcontroller Reference Manual Rev 4 Freescale Semiconductor 121 Figure 5 13 MC_CGM Auxiliary Clock 0 Generation Overview CGM_AC0_DC0 Register clock divider unused unused no clock 2 no clock 4 no clock 5 no clock 8 CGM_AC0_SC Register no clock 0 ...

Page 122: ... Module MC_CGM MPC5602P Microcontroller Reference Manual Rev 4 122 Freescale Semiconductor Figure 5 14 MC_CGM Auxiliary Clock 1 Generation Overview CGM_AC1_DC0 Register clock divider unused unused CGM_AC1_SC Register no clock 0 ...

Page 123: ... the CGM_AC0_DC0 register unused controlled by the CGM_AC1_DC0 register unused controlled by the CGM_AC2_DC0 register 5 9 Dividers Functional Description Dividers are used for the generation of divided system and peripheral clocks The MC_CGM has the following control registers for built in dividers Section 5 5 4 System Clock Divider Configuration Register CGM_SC_DC0 Section 5 5 6 Auxiliary Clock 0...

Page 124: ... Clock Division Selection Figure 5 16 MC_CGM Output Clock Multiplexer and PAD 22 Generation The MC_CGM provides the following output signals for the output clock generation PAD 22 see Figure 5 16 This signal is generated by using one of the 3 stage ripple counter outputs or the selected signal without division The non divided signal is not guaranteed to be 50 duty cycle by the MC_CGM the MC_CGM al...

Page 125: ... Power Control Unit MC_PCU 6 1 Introduction 6 1 1 Overview The power control unit MC_PCU acts as a bridge for mapping the PMU peripheral to the MC_PCU address space Figure 6 1 depicts the MC_PCU block diagram Registers Platform Interface MC_PCU Figure 6 1 MC_PCU Block Diagram Mapped Module Interface mapped peripheral core ...

Page 126: ...inition 6 3 1 Memory Map NOTE Any access to unused registers as well as write accesses to read only registers will not change register content cause a transfer error Table 6 1 MC_PCU Register Description Address Name Description Size Access Location User Supervisor Test 0xC3FE _8040 PCU_PSTAT Power Domain Status Register word read read read on page 127 Table 6 2 MC_PCU Memory Map 0xC3FE _80004 0xC...

Page 127: ...omain Status Register PCU_PSTAT This register reflects the power status of all available power domains 0xC3FE _8080 0xC3FE _80FC PMU registers 0xC3FE _8100 0xC3FE _BFFC reserved Address 0xC3FE_8040 Access User read Supervisor read Test read R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PD0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Figure 6 ...

Page 128: ...Chapter 6 Power Control Unit MC_PCU MPC5602P Microcontroller Reference Manual Rev 4 128 Freescale Semiconductor ...

Page 129: ...onductor 129 Chapter 7 Mode Entry Module MC_ME 7 1 Introduction 7 1 1 Overview The MC_ME controls the SoC mode and mode transition sequences in all functional states It also contains configuration control and status registers accessible for the application Figure 7 1 depicts the MC_ME Block Diagram ...

Page 130: ...PC5602P Microcontroller Reference Manual Rev 4 130 Freescale Semiconductor Registers Platform Interface core MC_ME Figure 7 1 MC_ME Block Diagram MC_RGM XOSC0 PLL0 16 MHz_IRC MC_CGM peripherals Flashes VREG Device Mode State Machine WKPU ...

Page 131: ...monitoring of the system The user modes are modes such as RUN0 3 HALT0 and STOP0 which can be configured to meet the application requirements in terms of energy management and available processing power The modes DRUN SAFE TEST and RUN0 3 are the device software running modes Table 7 1 describes the MC_ME modes Table 7 1 MC_ME Mode Descriptions Name Description Entry Exit RESET This is a chip wide...

Page 132: ...ch other software request from DRUN or other RUN0 3 interrupt event from HALT0 interrupt or wakeup event from STOP0 system reset assertion SAFE via software or hardware failure other RUN0 3 modes HALT0 STOP0 via software HALT0 This is a reduced activity low power mode during which the clock to the core is disabled It can be configured to switch off analog peripherals like clock sources flash main ...

Page 133: ... Configuration word read read read on page 150 0xC3FD _C024 ME_TEST_MC TEST Mode Configuration word read read write read write on page 150 0xC3FD _C028 ME_SAFE_MC SAFE Mode Configuration word read read write read write on page 151 0xC3FD _C02C ME_DRUN_MC DRUN Mode Configuration word read read write read write on page 151 0xC3FD _C030 ME_RUN0_MC RUN0 Mode Configuration word read read write read wri...

Page 134: ...e read write on page 157 0xC3FD _C0C4 ME_PCTL4 DSPI_0 Control byte read read write read write on page 158 0xC3FD _C0C5 ME_PCTL5 DSPI_1 Control byte read read write read write on page 158 0xC3FD _C0C6 ME_PCTL6 DSPI_2 Control byte read read write read write on page 158 0xC3FD _C0D0 ME_PCTL16 FlexCAN_0 Control byte read read write read write on page 158 0xC3FD _C0DA ME_PCTL26 SafetyPort Control byte ...

Page 135: ... 3 MC_ME Memory Map 0xC3FD _C000 ME_GS R S_CURRENT_MODE S_MTRANS 1 0 0 S_PDO 0 0 S_MVR S_DFLA S_CFLA W R 0 0 0 0 0 0 0 0 0 S_PLL0 S_XOSC0 S_16 MHz_IRC S_SYSCLK W 0xC3FD _C004 ME_MCTL R TARGET_MODE 0 0 0 0 0 0 0 0 0 0 0 0 W R 1 0 1 0 0 1 0 1 0 0 0 0 1 1 1 1 W KEY 0xC3FD _C008 ME_ME R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R 0 0 0 0 0 STOP0 0 HALT0 RUN3 RUN2 RUN1 RUN0 DRUN SAFE TEST RESET W 0xC3FD _C00C ...

Page 136: ... 0 0 0 0 0 0 S_MTI S_MRI S_DMA S_NMA S_SEA W w1c w1c w1c w1c w1c 0xC3FD _C018 ME_DMTS R PREVIOUS_MODE 0 0 0 0 MPH_BUSY 0 0 PMC_PROG CORE_DBG 0 0 SMR W R 0 VREG_CSRC_SC CSRC_CSRC_SC 16 MHz_IRC_SC SCSRC_SC SYSCLK_SW DFLASH_SC CFLASH_SC CDP_PRPH_0_143 0 0 0 0 CDP_PRPH_64_95 CDP_PRPH_32_63 CDP_PRPH_0_31 W 0xC3FD _C01C reserved 0xC3FD _C020 ME_RESET_ MC R 0 0 0 0 0 0 0 0 PDO 0 0 MVRON DFLAON CFLAON W R...

Page 137: ...0xC3FD _C028 ME_SAFE_M C R 0 0 0 0 0 0 0 0 PDO 0 0 MVRON DFLAON CFLAON W R 0 0 0 0 0 0 0 0 0 PLL0ON XOSC0ON 16 MHz_IRCON SYSCLK W 0xC3FD _C02C ME_DRUN_M C R 0 0 0 0 0 0 0 0 PDO 0 0 MVRON DFLAON CFLAON W R 0 0 0 0 0 0 0 0 0 PLL0ON XOSC0ON 16 MHz_IRCON SYSCLK W 0xC3FD _C030 0xC3FD _C03C ME_RUN0 3 _MC R 0 0 0 0 0 0 0 0 PDO 0 0 MVRON DFLAON CFLAON W R 0 0 0 0 0 0 0 0 0 PLL0ON XOSC0ON 16 MHz_IRCON SYSC...

Page 138: ... 0 0 PLL0ON XOSC0ON 16 MHz_IRCON SYSCLK W 0xC3FD _C044 reserved 0xC3FD _C048 ME_STOP0_ MC R 0 0 0 0 0 0 0 0 PDO 0 0 MVRON DFLAON CFLAON W R 0 0 0 0 0 0 0 0 0 PLL0ON XOSC0ON 16 MHz_IRCON SYSCLK W 0xC3FD _C04C 0xC3FD _C05C reserved 0xC3FD _C060 ME_PS0 R 0 0 0 0 0 S_SafetyPort 0 0 0 0 0 0 0 0 0 S_FlexCAN_0 W R 0 0 0 0 0 0 0 0 0 S_DSPI_2 S_DSPI_1 S_DSPI_0 0 0 0 0 W Table 7 3 MC_ME Memory Map continued...

Page 139: ... _C068 ME_PS2 R 0 0 0 S_PIT 0 0 0 0 0 0 0 0 0 0 0 0 W R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W 0xC3FD _C06C reserved 0xC3FD _C070 reserved 0xC3FD _C074 0xC3FD _C07C reserved 0xC3FD _C080 0xC3FD _C09C ME_RUN_PC 0 7 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R 0 0 0 0 0 0 0 0 RUN3 RUN2 RUN1 RUN0 DRUN SAFE TEST RESET W 0xC3FD _C0A0 0xC3FD _C0BC ME_LP_PC0 7 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R 0 0 0 0 0 STOP0 0 ...

Page 140: ...yte at address 0xC3FD_C083 7 3 2 1 Global Status Register ME_GS This register contains global mode status 0xC3FD _C0C0 0xC3FD _C14C ME_PCTL0 143 R 0 DBG_F LP_CFG RUN_CFG 0 DBG_F LP_CFG RUN_CFG W R 0 DBG_F LP_CFG RUN_CFG 0 DBG_F LP_CFG RUN_CFG W 0xC3FD _C150 0xC3FD _FFFC reserved Address 0xC3FD_C000 Access User read Supervisor read Test read R S_CURRENT_MODE S_MTRANS 1 0 0 S_PDO 0 0 S_MVR S_DFLA S_...

Page 141: ...er is enabled 1 In SAFE TEST modes outputs of pads are forced to high impedance state and the pads power sequence driver is disabled The inputs are level unchanged In STOP0 mode only the pad power sequence driver is disabled but the state of the output remains functional S_MVR Main voltage regulator status 0 Main voltage regulator is not ready 1 Main voltage regulator is ready for use S_DFLA Data ...

Page 142: ...al RC oscillator is not stable 1 16 MHz internal RC oscillator is providing a stable clock S_SYSCLK System clock switch status These bits specify the system clock currently used by the system 0000 16 MHz int RC osc 0001 reserved 0010 4 MHz crystal osc 0011 reserved 0100 system PLL 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 r...

Page 143: ...E on hardware request Also while exiting from the HALT0 and STOP0 modes on hardware exit events these are updated with the appropriate RUN0 3 mode value 0000 RESET 0001 TEST 0010 SAFE 0011 DRUN 0100 RUN0 0101 RUN1 0110 RUN2 0111 RUN3 1000 HALT0 1001 reserved 1010 STOP0 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved KEY Control key These bits enable write access to this regis...

Page 144: ...RUN1 mode enable 0 RUN1 mode is disabled 1 RUN1 mode is enabled RUN0 RUN0 mode enable 0 RUN0 mode is disabled 1 RUN0 mode is enabled DRUN DRUN mode enable 0 DRUN mode is disabled 1 DRUN mode is enabled SAFE SAFE mode enable 0 SAFE mode is disabled 1 SAFE mode is enabled TEST TEST mode enable 0 TEST mode is disabled 1 TEST mode is enabled RESET RESET mode enable 0 RESET mode is disabled 1 RESET mod...

Page 145: ...ters SAFE mode on hardware requests generated in the system It is cleared by writing a 1 to this bit 0 No SAFE mode interrupt occurred 1 SAFE mode interrupt is pending I_MTC Mode transition complete interrupt This bit is set whenever the mode transition process completes S_MTRANS transits from 1 to 0 It is cleared by writing a 1 to this bit This mode transition interrupt bit will not be set while ...

Page 146: ...S Field Descriptions Field Description S_MTI Mode Transition Illegal status This bit is set whenever a new mode is requested while some other mode transition process is active S_MTRANS is 1 Please refer to Section 7 4 5 Mode Transition Interrupts for the exceptions to this behavior It is cleared by writing a 1 to this bit 0 Mode transition requested is not illegal 1 Mode transition requested is il...

Page 147: ...requested is an existing mode 1 Target mode requested is a non existing mode S_SEA SAFE Event Active status This bit is set whenever the device is in SAFE mode SAFE event bit is pending and a new mode requested other than RESET SAFE modes It is cleared by writing a 1 to this bit 0 No new mode requested other than RESET SAFE while SAFE event is pending 1 New mode requested other than RESET SAFE whi...

Page 148: ...t in debug mode 1 The processor is in debug mode SMR SAFE mode request from MC_RGM is active indicator This bit is set if a hardware SAFE mode request has been triggered It is cleared when the hardware SAFE mode request has been cleared 0 A SAFE mode request is not active 1 A SAFE mode request is active VREG_CSR C_SC Main VREG dependent Clock Source State Change during mode transition indicator Th...

Page 149: ...DP_PRPH _64_95 Clock Disable Process Pending status for Peripherals 64 95 This bit is set when any peripheral appearing in ME_PS2 has been requested to have its clock disabled It is cleared when all these peripherals which have been requested to have their clocks disabled have entered the state in which their clocks may be disabled 0 No peripheral clock disabling is pending 1 Clock disabling is pe...

Page 150: ...lowed to this register Address 0xC3FD_C020 Access User read Supervisor read write Test read write R 0 0 0 0 0 0 0 0 PDO 0 0 MVRON DFLAON CFLAON W Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 R 0 0 0 0 0 0 0 0 0 PLL0ON XOSC0ON 16 MHz_IRCON SYSCLK W Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Figure 7 9 RESET Mode Configuration Register ME_RESET_MC Address 0xC3FD_C024 Access User read Supervisor read write Test ...

Page 151: ...yte write accesses are not allowed to this register Address 0xC3FD_C028 Access User read Supervisor read write Test read write R 0 0 0 0 0 0 0 0 PDO 0 0 MVRON DFLAON CFLAON W Reset 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1 R 0 0 0 0 0 0 0 0 0 PLL0ON XOSC0ON 16 MHz_IRCON SYSCLK W Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Figure 7 11 SAFE Mode Configuration Register ME_SAFE_MC Address 0xC3FD_C02C Access User read...

Page 152: ...write accesses are not allowed to this register Address 0xC3FD_C030 0xC3FD_C03C Access User read Supervisor read write Test read write R 0 0 0 0 0 0 0 0 PDO 0 0 MVRON DFLAON CFLAON W Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 R 0 0 0 0 0 0 0 0 0 PLL0ON XOSC0ON 16 MHz_IRCON SYSCLK W Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Figure 7 13 RUN0 3 Mode Configuration Registers ME_RUN0 3_MC Address 0xC3FD_C040 Acc...

Page 153: ...RCON SYSCLK W Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Figure 7 15 STOP0 Mode Configuration Register ME_STOP0_MC Table 7 11 Mode Configuration Registers ME_ mode _MC Field Descriptions Field Description PDO I O output power down control This bit controls the output power down of I Os 0 No automatic safe gating of I Os used and pads power sequence driver is enabled 1 In SAFE TEST modes outputs of pads...

Page 154: ... switched off 1 4 MHz crystal oscillator is switched on 16 MHz_IRCON 16 MHz internal RC oscillator control 0 16 MHz internal RC oscillator is switched off 1 16 MHz internal RC oscillator is switched on SYSCLK System clock switch control These bits specify the system clock to be used by the system 0000 16 MHz int RC osc 0001 reserved 0010 4 MHz crystal osc 0011 reserved 0100 system PLL 0101 reserve...

Page 155: ...FD_C060 Access User read Supervisor read Test read R 0 0 0 0 0 S_SafetyPort 0 0 0 0 0 0 0 0 0 S_FlexCAN_0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R 0 0 0 0 0 0 0 0 0 S_DSPI_2 S_DSPI_1 S_DSPI_0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 7 16 Peripheral Status Register 0 ME_PS0 Address 0xC3FD_C064 Access User read Supervisor read Test read R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 S_LIN_FLEX_1 S_LIN...

Page 156: ... Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 7 18 Peripheral Status Register 2 ME_PS2 Table 7 12 Peripheral Status Registers 0 4 ME_PS0 4 Field Descriptions Field Description S_ periph Peripheral status These bits specify the current status of the peripherals in the system If no peripheral is mapped on a particular position i e the corresponding MODS bit is 0 the corresponding bit is always read ...

Page 157: ...gated 1 Peripheral is active RUN0 Peripheral control during RUN0 0 Peripheral is frozen with clock gated 1 Peripheral is active DRUN Peripheral control during DRUN 0 Peripheral is frozen with clock gated 1 Peripheral is active SAFE Peripheral control during SAFE 0 Peripheral is frozen with clock gated 1 Peripheral is active TEST Peripheral control during TEST 0 Peripheral is frozen with clock gate...

Page 158: ...clock gated 1 Peripheral is active Address 0xC3FD_C0C0 0xC3FD_C14F Access User read Supervisor read write Test read write R 0 DBG_F LP_CFG RUN_CFG W Reset 0 0 0 0 0 0 0 0 Figure 7 21 Peripheral Control Registers ME_PCTL0 143 Table 7 15 Peripheral Control Registers ME_PCTL0 143 Field Descriptions Field Description DBG_F Peripheral control in debug mode This bit controls the state of the peripheral ...

Page 159: ...d mode requests please refer to Section 7 4 5 Mode Transition Interrupts Any modification of the mode configuration register of the currently selected mode will not be taken into account immediately but on the next request to enter this mode This means that transition requests such as RUN0 3 Æ RUN0 3 DRUN Æ DRUN SAFE Æ SAFE and TEST Æ TEST are considered valid mode transition requests As soon as t...

Page 160: ...RGET_MODE bit field of the ME_MCTL register is written with 0000 from any mode due to a system reset by the MC_RGM because of some non recoverable hardware failure in the system see the MC_RGM chapter for details Transition to this mode is instantaneous and the system remains in this mode until the reset sequence is finished The mode configuration information for this mode is provided by the ME_RE...

Page 161: ... on the following events from DRUN RUN0 3 or TEST mode when the TARGET_MODE bit field of the ME_MCTL register is written with 0010 from any mode except RESET due to a SAFE mode request generated by the MC_RGM because of some potentially recoverable hardware failure in the system see the MC_RGM chapter for details As soon as any of the above events has occurred a SAFE mode transition request is gen...

Page 162: ...11 and in this case the only way to exit this mode is via a device reset This mode is intended to be used by software to execute software test routines NOTE Software must ensure that the code executes from RAM before changing to this mode if the flashes are configured to be in the low power or power down state in this mode 7 4 2 5 RUN0 3 Modes The device enters one of these modes on the following ...

Page 163: ... to wait until it is required to do something and then to react quickly i e within a few system clock cycles of an interrupt event 7 4 2 7 STOP0 Mode The device enters this mode on the following events from one of the RUN0 3 modes when the TARGET_MODE bit field of the ME_MCTL register is written with 1010 As soon as any of the above events has occurred a STOP0 mode transition request is generated ...

Page 164: ...de requests Refer to Section 7 4 5 Mode Transition Interrupts for details In the case of mode transitions occurring because of hardware events such as a reset a SAFE mode request or interrupt requests and wakeup events to exit from low power modes the TARGET_MODE bit field of the ME_MCTL register is automatically updated with the appropriate target mode The mode change process start is indicated b...

Page 165: ...those peripherals that are to be powered down are configured in the MC_ME to be frozen Each peripheral acknowledges its stop mode request after closing its internal activity The MC_ME then disables the corresponding clock s to this peripheral In the case of a SAFE mode transition request the MC_ME does not wait for the peripherals to acknowledge the stop requests The SAFE mode clock gating configu...

Page 166: ...e halted or stopped state the MC_ME disables the processor and system memory clocks to achieve further power saving The clocks to the processor and system memory are unaffected while transitioning between software running modes such as DRUN RUN0 3 and SAFE WARNING Clocks to the whole device including the processor and system memory can be disabled in TEST mode 7 4 3 6 Clock Sources Switch On On co...

Page 167: ...ce modes the peripheral configuration registers ME_RUN_PC0 7 ME_LP_PC0 7 and the peripheral control registers ME_PCTL0 143 the MC_ME enables the clocks for selected modules as required This step is executed only after the process is completed 7 4 3 10 Processor and Memory Clock Enable If the mode transition is from any of the low power modes HALT0 or STOP0 to RUN0 3 the clocks to the processor and...

Page 168: ... Clock Sources Switch On process has completed if the target system clock source is one of the following the 16 MHz internal RC oscillator the system PLL the Peripheral Clocks Disable process has completed in order not to change the system clock frequency before peripherals close their internal activities An overview of system clock source selection possibilities for each mode is shown in Table 7 ...

Page 169: ...f at this step the 16 MHz internal RC oscillator This step is executed only after the System Clock Switching process has completed in order not to lose the current system clock during mode transition the Clock Sources with no Dependencies Switch Off process has completed in order to for example prevent unwanted lock transitions 7 4 3 16 Flash Switch Off Based on the CFLAON and DFLAON bit fields of...

Page 170: ...tus by reading the S_MTRANS bit of the ME_GS register The mode transition latency can differ from one mode to another depending on the resources availability before the new mode request and the target mode s requirements If a mode transition is taking longer to complete than is expected the ME_DMTS register can indicate which process is still in progress ...

Page 171: ...itch On System Clock Switching FLASH Switch On Pad Processor Low Power Processor PAD Peripheral Clocks Enable FLASH Switch Off S_MTRANS 1 ANALOG ON DIGITAL CONTROL ANALOG OFF Current Mode Update Start S_MTRANS 0 Outputs On Outputs Off Entry Processor Low Power Exit Clock Disable Memory Processor Clock Enable Memory Figure 7 23 MC_ME Transition Diagram Clock Sources Without Dependencies Switch Off ...

Page 172: ...ed Configuration 10 for the DFLAON bit field is reserved If the DFLAON bit field is set to 11 the CFLAON field must also be set to 11 System clock configurations marked as reserved may not be selected Configuration 1111 for the SYSCLK bit field is allowed only for theTEST mode and only in this case may all system clock sources be turned off WARNING If the system clock is stopped during TEST mode t...

Page 173: ...hile a mode transition is in progress the S_MTRANS bit of the ME_GS register is 1 the mode transition illegal status bit S_MTI of the ME_IMTS register is set This condition is detected only when the proper key mechanism is followed while writing the ME_MCTL register Otherwise the write operation is ignored NOTE As the causes of invalid mode transitions may overlap at the same time the priority imp...

Page 174: ...e low power modes 7 4 6 Peripheral Clock Gating During all device modes each peripheral can be associated with a particular clock gating policy determined by two groups of peripheral configuration registers The run peripheral configuration registers ME_RUN_PC0 7 are chosen only during the software running modes DRUN TEST SAFE and RUN0 3 All configurations are programmable by software according to ...

Page 175: ... MPC5602P Microcontroller Reference Manual Rev 4 Freescale Semiconductor 175 7 4 7 Application Example Figure 7 24 shows an example application flow for requesting a mode change and then waiting until the mode transition has completed ...

Page 176: ...e config for target mode okay write ME_ target mode _MC ME_RUN_PC0 7 ME_LP_PC0 7 and ME_PCTL0 143 registers N Y write ME_MCTL with target mode and key write ME_MCTL with target mode and inverted key start timer S_MTRANS cleared Y timer expired N Y N write ME_MCTL with current or SAFE mode and key write ME_MCTL with current or SAFE mode and inverted key stop timer mode change DONE ...

Page 177: ...e different reset sources and manages the reset sequence of the device It provides a register interface and the reset sequencer Various registers are available to monitor and control the device reset sequence The reset sequencer is a state machine which controls the different phases PHASE0 PHASE1 PHASE2 PHASE3 and IDLE of the reset sequence and controls the reset signals generated in the system Fi...

Page 178: ...equence configuration PAD 4 2 RESET_B Registers Platform Interface core MC_RGM Figure 8 1 MC_RGM Block Diagram MC_ME power on 1 2V low voltage detected software watchdog timer 2 7V low voltage detected VREG 2 7V low voltage detected flash 2 7V low voltage detected I O JTAG initiated reset core reset software reset checkstop reset PLL0 fail oscillator frequency lower than reference CMU0 clock frequ...

Page 179: ...eset event occurs a partial reset sequence is applied to the device starting from PHASE1 In this case most digital modules are reset normally while analog modules or specific digital modules e g debug modules flash modules state is preserved Functional resets are external reset JTAG initiated reset core reset software reset checkstop reset PLL0 fail oscillator frequency lower than reference CMU0 c...

Page 180: ...t change register content and cause a transfer error Table 8 1 MC_RGM Register Description Address Name Description Size Access Location User Supervisor Test 0xC3FE _4000 RGM_FES Functional Event Status half word read read write1 read write1 on page 182 0xC3FE _4002 RGM_DES Destructive Event Status half word read read write1 1 individual bits cleared on writing 1 read write1 on page 184 0xC3FE _40...

Page 181: ...D27_FLASH F_LVD27_VREG 0 F_SWT 0 F_LVD12 W w1c 0xC3FE _4004 RGM_ FERD RGM_ DERD R D_EXR 0 0 0 0 0 D_PLL1 D_FLASH D_LVD45 D_CMU0_FHL D_CMU0_OLR D_PLL0 D_CHKSTOP D_SOFT D_CORE D_JTAG W R 0 0 0 0 0 0 0 0 0 D_LVD27_IO D_LVD27_FLASH D_LVD27_VREG 0 D_SWT 0 D_LVD12 W 0xC3FE _4008 0xC3FE _400C reserved 0xC3FE _4010 RGM_ FEAR R 0 0 0 0 0 0 AR_PLL1 0 AR_LVD45 AR_CMU0_FHL AR_CMU0_OLR AR_PLL0 0 0 AR_CORE AR_J...

Page 182: ... RGM_ FESS R SS_EXR 0 0 0 0 0 SS_PLL1 SS_FLASH SS_LVD45 SS_CMU0_FHL SS_CMU0_OLR SS_PLL0 SS_CHKSTOP SS_SOFT SS_CORE SS_JTAG W R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W 0xC3FE _401C RGM_ FBRE R BE_EXR 0 0 0 0 0 BE_PLL1 BE_FLASH BE_LVD45 BE_CMU0_FHL BE_CMU0_OLR BE_PLL0 BE_CHKSTOP BE_SOFT BE_CORE BE_JTAG W R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W 0xC3FE _4020 0xC3FE _7FFC reserved Address 0xC3FE_4000 Access User...

Page 183: ...lock frequency higher lower than reference 0 No CMU0 clock frequency higher lower than reference event has occurred since either the last clear or the last destructive reset assertion 1 A CMU0 clock frequency higher lower than reference event has occurred F_CMU0_OLR Flag for oscillator frequency lower than reference 0 No oscillator frequency lower than reference event has occurred since either the...

Page 184: ...I O 0 No 2 7V low voltage detected I O event has occurred since either the last clear or the last power on reset assertion 1 A 2 7V low voltage detected I O event has occurred F_LVD27_FLASH Flag for 2 7V low voltage detected flash 0 No 2 7V low voltage detected flash event has occurred since either the last clear or the last power on reset assertion 1 A 2 7V low voltage detected flash event has oc...

Page 185: ...r on reset Address 0xC3FE_4004 Access User read Supervisor read write Test read write R D_EXR 0 0 0 0 0 D_PLL1 D_FLASH D_LVD45 D_CMU0_FHL D_CMU0_OLR D_PLL0 D_CHKSTOP D_SOFT D_CORE D_JTAG W POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 8 4 Functional Event Reset Disable Register RGM_FERD Table 8 5 Functional Event Reset Disable Register RGM_FERD Field Descriptions Field Description D_EXR Disable Exter...

Page 186: ...est depending on the value of RGM_FEAR AR_PLL0 D_CHKSTOP Disable checkstop resetl 0 A checkstop reset event triggers a reset sequence D_SOFT Disable software reset 0 A software reset event triggers a reset sequence D_CORE Disable core reset 0 A core reset event triggers a reset sequence 1 A core reset event generates either a SAFE mode or an interrupt request depending on the value of RGM_FEAR AR_...

Page 187: ...ers a reset sequence D_LVD12 Disable 1 2V low voltage detected 0 A 1 2V low voltage detected event triggers a reset sequence Address 0xC3FE_4010 Access User read Supervisor read write Test read write R 0 0 0 0 0 0 AR_PLL1 0 AR_LVD45 AR_CMU0_FHL AR_CMU0_OLR AR_PLL0 0 0 AR_CORE AR_JTAG W POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 8 6 Functional Event Alternate Request Register RGM_FEAR Table 8 7 Fun...

Page 188: ... if the reset is disabled AR_PLL0 Alternate Request for PLL0 fail 0 Generate a SAFE mode request on a PLL0 fail event if the reset is disabled 1 Generate an interrupt request on a PLL0 fail event if the reset is disabled AR_CORE Alternate Request for core reset 0 Generate a SAFE mode request on a core reset event if the reset is disabled 1 Generate an interrupt request on a core reset event if the...

Page 189: ...ce event will start from PHASE1 1 The reset sequence triggered by a CMU0 clock frequency higher lower than reference event will start from PHASE3 skipping PHASE1 and PHASE2 SS_CMU0_OLR Short Sequence for oscillator frequency lower than reference 0 The reset sequence triggered by a oscillator frequency lower than reference event will start from PHASE1 1 The reset sequence triggered by a oscillator ...

Page 190: ...de or data flash fatal error event if the reset is enabled 1 RESET_B is not asserted on a code or data flash fatal error event BE_LVD45 Bidirectional Reset Enable for 4 5V low voltage detected 0 RESET_B is asserted on a 4 5V low voltage detected event if the reset is enabled 1 RESET_B is not asserted on a 4 5V low voltage detected event BE_CMU0_FHL Bidirectional Reset Enable for CMU0 clock frequen...

Page 191: ...1 RESET_B is not asserted on a core reset event BE_JTAG Bidirectional Reset Enable for JTAG initiated reset 0 RESET_B is asserted on a JTAG initiated reset event if the reset is enabled 1 RESET_B is not asserted on a JTAG initiated reset event Table 8 10 MC_RGM Reset Implications Source What Gets Reset External Reset Assertion1 1 external reset assertion means that the RESET_B pin is asserted by t...

Page 192: ...need to be done in PHASE0 are completed Figure 8 9 MC_RGM State Machine PHASE0 PHASE1 PHASE2 PHASE3 IDLE duration 3 16 MHz internal RC oscillator clock cycles 16 MHz IRC stable VREG voltage okay done duration 350 16 MHz internal RC oscillator clock cycles duration 16 MHz internal RC oscillator clock cycles code and data flash initialization done duration 40 16 MHz internal RC oscillator clock cycl...

Page 193: ... 4 1 3 PHASE2 Phase This phase is entered on exit from PHASE1 The reset state machine exits PHASE2 and enters PHASE3 on verification of the following all processes that need to be done in PHASE2 are completed code and data flash initialization a minimum of 8 16 MHz internal RC oscillator clock cycles have elapsed since entering PHASE2 8 4 1 4 PHASE3 Phase This phase is a entered either on exit fro...

Page 194: ...estructive reset will trigger a reset sequence starting from the beginning of PHASE0 8 4 3 External Reset The MC_RGM manages the external reset coming from RESET_B The detection of a falling edge on RESET_B will start the reset sequence from the beginning of PHASE1 The status flag associated with the external reset falling edge event RGM_FES F_EXR bit is set when the external reset is asserted and...

Page 195: ...unctional reset is set the associated functional reset will trigger a reset sequence starting directly from the beginning of PHASE3 skipping PHASE1 and PHASE2 This can be useful especially in case a functional reset should not reset the flash module See the MC_ME chapter for details on the STANDBY0 and DRUN modes 8 4 5 Alternate Event Generation The MC_RGM provides alternative events to be generat...

Page 196: ...l RC oscillator clock cycles before the rising edge of RESET_B The result of the sampling is then provided to the system For each bit a value of 1 is produced only if each of the oldest three of the five samples have the value 1 otherwise a value of 0 is produced NOTE In order to ensure that the boot mode is correctly captured the application needs to apply the valid boot mode value to the device ...

Page 197: ...priority ceiling protocol for coherent accesses By providing a modifiable priority mask the priority can be raised temporarily so that tasks sharing the resource will not preempt each other Multiple processors can assert interrupt requests to each other through software configurable interrupt requests These software configurable interrupt requests can also be used to separate the work involved in ...

Page 198: ...e Manual Rev 4 198 Freescale Semiconductor Table 9 1 Interrupt sources available Interrupt sources 128 Number available Software 8 ECSM 3 eDMA2x 17 SWT 1 STM 4 SIUL 4 MC_ME 4 MC_RGM 1 XOSC 1 PIT 4 ADC 3 FlexCAN 8 eTimer 8 FlexPWM 10 CTU 15 Safety Port 8 DSPI 15 LINFlex 6 ...

Page 199: ...d with the interrupt request to the processor The INTC will use software vector Peripheral B Hardware Vector Enable Software Set Clear Interrupt Registers Flag Bits Peripheral Interrupt Requests Module Configuration Register Highest Priority 4 Priority Comparator Slave Interface for Reads Writes 1 Push Update Acknowledge 1 1 1 Update Interrupt Vector 1 Interrupt Request to Processor Memory Mapped ...

Page 200: ...to the associated processor asserts the interrupt vector signal is updated The value of that interrupt vector is the unique vector associated with the preempting peripheral or software configurable interrupt request The vector value matches the value of the INTVEC field in the INTC_IACKR field in the INTC_IACKR depending on which processor was assigned to handle a given interrupt source The proces...

Page 201: ...hat the access does not cross a 32 bit boundary In software vector mode the side effects of a read of INTC_IACKR are the same regardless of the size of the read In either software or hardware vector mode the size of a write to either INTC_SSCIR0_3 INTC_SSCIR4_7 or INTC_EOIR does not affect the operation of the write Table 9 2 INTC memory map Offset from INTC_BASE 0xFFF4_8000 Register Location 0x00...

Page 202: ...nfiguration Register INTC_MCR Table 9 3 INTC_MCR field descriptions Field Description 26 VTES Vector table entry size Controls the number of 0s to the right of INTVEC in Section 9 5 2 3 INTC Interrupt Acknowledge Register INTC_IACKR If the contents of INTC_IACKR are used as an address of an entry in a vector table as in software vector mode then the number of right most 0s will determine the size ...

Page 203: ...to the INTC_CPR s PRI field The masking priority can be raised or lowered by writing to the PRI field supporting the PCP Refer to Section 9 7 5 Priority ceiling protocol Address Base 0x0008 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 P...

Page 204: ...ad write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R VTBA most significant 16 bits W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R VTBA least significant 5 bits INTVEC1 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 When the VTES bit in INTC_MCR is asserted INTVEC is shifted to the left one bit Bit 29 is read as a 0 VTBA is narrowed to 20 bits in width Figure 9...

Page 205: ...s of all 0s to the INTC_EOIR Reading the INTC_EOIR has no effect on the LIFO 9 5 2 5 INTC Software Set Clear Interrupt Registers INTC_SSCIR0_3 INTC_SSCIR4_7 Address Base 0x0018 Access Write only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0...

Page 206: ...er read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 CLR 4 0 0 0 0 0 0 0 CLR 5 W SET4 SET5 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 CLR 6 0 0 0 0 0 0 0 CLR 7 W SET6 SET7 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 9 7 INTC Software Set Clear Interrupt Register 4 7 INTC_SSCIR 4 7 Table 9 6 INTC_SSCIR 0 7 field descriptions...

Page 207: ...onal description Table 9 8 INTC Priority Select Register address offsets INTC_PSRx_x Offset Address INTC_PSRx_x Offset Address INTC_PSR0_3 0x0040 INTC_PSR112_115 0x00B0 INTC_PSR4_7 0x0044 INTC_PSR116_119 0x00B4 INTC_PSR8_11 0x0048 INTC_PSR120_123 0x00B8 INTC_PSR12_15 0x004C INTC_PSR124_127 0x00BC INTC_PSR16_19 0x0050 INTC_PSR128_131 0x00C0 INTC_PSR20_23 0x0054 INTC_PSR132_135 0x00C4 INTC_PSR24_27 ...

Page 208: ...0090 INTC_PSR192_195 0x0100 INTC_PSR84_87 0x0094 INTC_PSR196_199 0x0104 INTC_PSR88_91 0x0098 INTC_PSR200_203 0x0108 INTC_PSR92_95 0x009C INTC_PSR204_207 0x010C INTC_PSR96_99 0x00A0 INTC_PSR208_211 0x0110 INTC_PSR100_103 0x00A4 INTC_PSR212_215 0x0114 INTC_PSR104_107 0x00A8 INTC_PSR216_219 0x0118 INTC_PSR108_111 0x00AC INTC_PSR220_221 0x011C Table 9 8 INTC Priority Select Register address offsets co...

Page 209: ...d to that peripheral or software settable interrupt request Also the PRI value in the INTC_CPR will be updated with the corresponding PRIn value in INTC_PSRn Furthermore clearing the peripheral interrupt request s enable bit in the peripheral or alternatively setting its mask bit has the same consequences as clearing its flag bit Setting its enable bit or clearing its mask bit while its flag bit i...

Page 210: ... Channel 2 DMA2x 14 0x0838 Channel 3 DMA2x 15 0x083C Channel 4 DMA2x 16 0x0840 Channel 5 DMA2x 17 0x0844 Channel 6 DMA2x 18 0x0848 Channel 7 DMA2x 19 0x084C Channel 8 DMA2x 20 0x0850 Channel 9 DMA2x 21 0x0854 Channel 10 DMA2x 22 0x0858 Channel 11 DMA2x 23 0x085C Channel 12 DMA2x 24 0x0860 Channel 13 DMA2x 25 0x0864 Channel 14 DMA2x 26 0x0868 Channel 15 DMA2x 27 0x086C Reserved SWT 28 0x0870 Timeou...

Page 211: ...IUL 44 0x08B0 SIU External IRQ_3 SIUL 45 0x08B4 Reserved 46 0x08B8 Reserved 47 0x08BC Reserved 48 0x08C0 Reserved 49 0x08C4 Reserved 50 0x08C8 Reserved MC_ME 51 0x08CC Safe Mode Interrupt Mode Entry module MC_ME 52 0x08D0 Mode Transition Interrupt Mode Entry module MC_ME 53 0x08D4 Invalid Mode Interrupt Mode Entry module MC_ME 54 0x08D8 Invalid Mode Configuration Mode Entry module MC_ME 55 0x08DC ...

Page 212: ...CAN_0 67 0x090C FLEXCAN_ESR_WAK FlexCAN_0 68 0x0910 FLEXCAN_BUF_00_03 FlexCAN_0 69 0x0914 FLEXCAN_BUF_04_07 FlexCAN_0 70 0x0918 FLEXCAN_BUF_08_11 FlexCAN_0 71 0x091C FLEXCAN_BUF_12_15 FlexCAN_0 72 0x0920 FLEXCAN_BUF_16_31 FlexCAN_0 73 0x0924 Reserved DSPI0 74 0x0928 DSPI_SR TFUF DSPI_SR RFOF DSPI_0 75 0x092C DSPI_SR EOQF DSPI_0 76 0x0930 DSPI_SR TFFF DSPI_0 77 0x0934 DSPI_SR TCF DSPI_0 78 0x0938 D...

Page 213: ...1 0x096C FLEXCAN_BUF_12_15 FlexCAN_1 92 0x0970 FLEXCAN_BUF_16_31 FlexCAN_1 93 0x0974 Reserved DSPI1 94 0x0978 DSPI_SR TFUF DSPI_SR RFOF DSPI_1 95 0x097C DSPI_SR EOQF DSPI_1 96 0x0980 DSPI_SR TFFF DSPI_1 97 0x0984 DSPI_SR TCF DSPI_1 98 0x0988 DSPI_SR RFDF DSPI_1 LINFlex1 99 0x098C LINFlex_RXI LINFlex_1 100 0x0990 LINFlex_TXI LINFlex_1 101 0x0994 LINFlex_ERR LINFlex_1 102 0x0998 Reserved 103 0x099C ...

Page 214: ...DF DSPI_2 119 0x09DC Reserved 120 0x09E0 Reserved 121 0x09E4 Reserved 122 0x09E8 Reserved 123 0x09EC Reserved 124 0x09F0 Reserved 125 0x09F4 Reserved 126 0x09F8 Reserved PIT 127 0x09FC PITimer Channel 3 PIT 128 0x0A00 Reserved 129 0x0A04 Reserved 130 0x0A08 Reserved 131 0x0A0C Reserved 132 0x0A10 Reserved 133 0x0A14 Reserved 134 0x0A18 Reserved 135 0x0A1C Reserved 136 0x0A20 Reserved 137 0x0A24 Re...

Page 215: ...erved 152 0x0A60 Reserved 153 0x0A64 Reserved 154 0x0A68 Reserved 155 0x0A6C Reserved 156 0x0A70 Reserved eTimer 157 0x0A74 TC0IR eTimer_0 158 0x0A78 TC1IR eTimer_0 159 0x0A7C TC2IR eTimer_0 160 0x0A80 TC3IR eTimer_0 161 0x0A84 TC4IR eTimer_0 162 0x0A88 TC5IR eTimer_0 163 0x0A8C Reserved 164 0x0A90 Reserved 165 0x0A94 WTIF eTimer_0 166 0x0A98 Reserved 167 0x0A9C RCF eTimer_0 168 0x0AA0 Reserved 16...

Page 216: ... 0x0AD8 RF1 FlexPWM_0 183 0x0ADC COF1 FlexPWM_0 184 0x0AE0 Reserved 185 0x0AE4 RF2 FlexPWM_0 186 0x0AE8 COF2 FlexPWM_0 187 0x0AEC Reserved 188 0x0AF0 RF3 FlexPWM_0 189 0x0AF4 COF3 FlexPWM_0 190 0x0AF8 Reserved 191 0x0AFC FFLAG FlexPWM_0 192 0x0B00 REF FlexPWM_0 CTU 193 0x0B04 MRS_I CTU_0 194 0x0B08 T0_I CTU_0 195 0x0B0C T1_I CTU_0 196 0x0B10 T2_I CTU_0 197 0x0B14 T3_I CTU_0 198 0x0B18 T4_I CTU_0 1...

Page 217: ...e clocks External interrupts are handled by the SIU see Section 11 6 4 External interrupts 202 0x0B28 FIFO1_I CTU_0 203 0x0B2C FIFO2_I CTU_0 204 0x0B30 FIFO3_I CTU_0 205 0x0B34 FIFO4_I CTU_0 206 0x0B38 ADC_I CTU_0 207 0x0B3C ERR_I CTU_0 SafetyPort 208 0x0B40 FLEXCAN_ESR ERR_INT SafetyPort FlexCAN 209 0x0B44 FLEXCAN_ESR_BOFF FLEXCAN_Transmit_Warning FLEXCAN_Receive_Warning SafetyPort FlexCAN 210 0x...

Page 218: ...y 9 6 2 1 Current priority and preemption The priority arbitrator selector encoder and comparator subblocks shown in Figure 9 1 compare the priority of the asserted interrupt requests to the current priority If the priority of any asserted peripheral or software configurable interrupt request is higher than the current priority for a given processor then the interrupt request to the processor is a...

Page 219: ...iority does not need to be loaded from the context stack and stored into the INTC_CPR The PRI value in the INTC_CPR is pushed onto the LIFO when the INTC_IACKR is read in software vector mode or the interrupt acknowledge signal from the processor is asserted in hardware vector mode The priority is popped into PRI in the INTC_CPR whenever the INTC_EOIR is written Although the INTC supports 16 prior...

Page 220: ...r MSYNC instruction between the access to clear the flag bit and the write to the INTC_EOIR When returning from the preemption the INTC does not search for the peripheral or software settable interrupt request whose ISR was preempted Depending on how much the ISR progressed that interrupt request may no longer even be asserted When PRI in INTC_CPR is lowered to the priority of the preempted ISR th...

Page 221: ... interrupt vector to the processor matches the value of the INTVEC field in the INTC_IACKR The rest of the handshaking is described in Section 9 4 1 2 Hardware vector mode The handshaking near the end of the interrupt exception handler that is the writing to the INTC_EOIR is the same as in software vector mode Refer to Section 9 6 3 1 2 End of interrupt exception handler Figure 9 11 Hardware vecto...

Page 222: ...request to processor lwz r3 0x0 r3 load address of ISR from vector table wrteei 1 enable processor recognition of interrupts code to save rest of context required by e500 EABI mtlr r3 move INTC_IACKR contents into link register blrl branch to ISR link register updated with epilog address epilog code to restore most of context required by e500 EABI Popping the LIFO after the restoration of most of ...

Page 223: ... by e500 EABI Popping the LIFO after the restoration of most of the context and the disabling of processor recognition of interrupts eases the calculation of the maximum stack depth at the cost of postponing the servicing of the next interrupt request mbar ensure store to clear flag bit has completed lis r3 INTC_EOIR ha form adjusted upper half of INTC_EOIR address li r4 0x0 form 0 to write to INT...

Page 224: ...ss of the unique vectors associated with each of their peripheral or software configurable interrupt requests However if multiple peripheral or software configurable interrupt requests are asserted more than one has the highest priority and that priority is high enough to cause preemption the INTC selects the one with the lowest unique vector regardless of the order in time that they asserted Howe...

Page 225: ...priority ISR completes and execution returns to the lower priority ISR Using the PCP instead of disabling processor recognition of all interrupts eliminates the time when accessing a shared resource that all higher priority interrupts are blocked For example while ISR3 cannot preempt ISR1 while it is accessing the shared resource all of the ISRs with a priority higher than 3 can preempt ISR1 9 7 5...

Page 226: ...rom the time of the request for the ISR to the next request for it For example ISR1 executes every 100 µs ISR2 executes every 200 µs and ISR3 executes every 300 µs ISR1 has a higher priority than ISR2 which has a higher priority than ISR3 however if ISR3 has a deadline of 150 µs then it has a higher priority than ISR2 The INTC has 16 priorities which may be less than the number of ISRs In this cas...

Page 227: ...e ISRs on the other processors One application is that one processor wants to command another processor to perform a piece of work and the initiating processor does not need to use the results of that work If the initiating processor is concerned that the processor executing the software configurable ISR has not completed the work before asking it to again execute the ISR it can check if the corre...

Page 228: ...uests for these other flag bits must be selected properly Their PRIx values in INTC Priority Select Registers INTC_PSR0_3 INTC_PSR220_221 must be selected to be at or lower than the priority of the ISR that cleared their flag bits Otherwise those flag bits can cause the interrupt request to the processor to assert Furthermore the clearing of these other flag bits also has the same timing relations...

Page 229: ... in Figure 10 1 provides central device functionality Figure 10 1 SSCM block diagram 10 1 2 Features The SSCM includes these features System configuration and status Memory sizes status Device mode and security status Determine boot vector Search Code Flash for bootable sector DMA status Debug status port enable and selection Bus System Status and Configuration Module Interface Password Comparator...

Page 230: ...egister is accessible by a 16 bit read write to address Base 0x0002 but performing a 16 bit access to Base 0x0003 is illegal 10 2 2 Register description Each description includes a standard register diagram Details of register bit and field function follow the register diagrams in bit order The numbering convention of the registers is MSB 0 however the numbering of the internal fields is LSB 0 for...

Page 231: ...0 2 STATUS allowed register accesses Access type Access width 8 bit 16 bit 32 bit1 1 All 32 bit accesses must be aligned to 32 bit addresses i e 0x0 0x4 0x8 or 0xC Read Allowed Allowed Allowed Write Not allowed Not allowed Not allowed Table 10 3 STATUS field descriptions Field Description NXEN Nexus enabled PUB Public Serial Access Status This bit indicates whether serial boot mode with public pas...

Page 232: ...t identifies whether or not the on chip CFlash is accessible in the system memory map The Flash may not be accessible due to security limitations 1 CFlash accessible 0 CFlash not accessible Note This is a status bit only and writing to this bit does not enable the CFlash if it has been disabled due to specific mode of operation DVLD DFlash Valid This bit identifies whether or not the on chip DFlas...

Page 233: ...ions Field Description PAE Peripheral Bus Abort Enable This bit enables bus aborts on any access to a peripheral slot that is not used on the device This feature is intended to aid in debugging when developing application code 1 Illegal accesses to non existing peripherals produce a Prefetch or Data Abort exception 0 Illegal accesses to non existing peripherals do not produce a Prefetch or Data Ab...

Page 234: ...de 5 selected 110 Mode 6 selected 111 Mode 7 selected Table 10 9 describes the functionality of the Debug Status Port in each mode Table 10 9 Debug Status Port modes Pin 1 1 All signals are active high unless otherwise noted Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 0 STATUS 0 STATUS 8 MEMCONFIG 0 MEMCONFIG 8 Reserved Reserved Reserved 1 STATUS 1 STATUS 9 MEMCONFIG 1 MEMCONFIG 9 Reserved Re...

Page 235: ...ence Manual Rev 4 Freescale Semiconductor 235 Table 10 10 DEBUGPORT allowed register accesses Access type Access width 8 bit 16 bit 32 bit1 1 All 32 bit accesses must be aligned to 32 bit addresses i e 0x0 0x4 0x8 or 0xC Read Allowed Allowed Not allowed Write Allowed Allowed Not allowed ...

Page 236: ...egister High Word PWCMPH register Address Base 0x0010 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W PWD_LO 31 16 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W PWD_LO 15 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 10 8 Password Comparison Register Low Word PWCMPL registe...

Page 237: ...scription The primary purpose of the SSCM is to provide information about the current state and configuration of the system that may be useful for configuring application software and for debug of the system 10 4 Initialization application information 10 4 1 Reset The reset state of each individual bit is shown in Section 10 2 2 Register description ...

Page 238: ...Chapter 10 System Status and Configuration Module SSCM MPC5602P Microcontroller Reference Manual Rev 4 238 Freescale Semiconductor ...

Page 239: ...he MCU pad configuration ports general purpose input and output GPIO signals and external interrupts with trigger event configuration Figure 11 1 is a block diagram of the SIUL and its interfaces to other system components The module provides dedicated general purpose pads that can be configured as either inputs or outputs When configured as an output you can write to an internal register to contr...

Page 240: ...unction on up to 64 I O pins Dedicated input and output registers for each GPIO pin External interrupts 4 system interrupt vectors for up to 25 interrupt sources 25 programmable digital glitch filters Independent interrupt mask Edge detection IPS BUS Data Pad Input IO Interrupt Interrupt Controller IPS Master Configuration Glitch Filter Pad Configuration IOMUXC Pad Config PCRs GPIO Functionality 6...

Page 241: ...s the alternate pad function Table 11 1 lists the external pins used by the SIUL 11 4 1 Detailed signal descriptions 11 4 1 1 General purpose I O pins GPIO 0 66 The GPIO pins provide general purpose input and output function The GPIO pins are generally multiplexed with other I O pin functions Each GPIO input and output is separately controlled by an input GPDIn_n or output GPDOn_n register See Sec...

Page 242: ...n page 246 0x001C 0x0027 Reserved 0x0028 Interrupt Rising Edge Event Enable Register IREER on page 247 0x002C Interrupt Falling Edge Event Enable Register IFEER on page 247 0x0030 Interrupt Filter Enable Register IFER on page 248 0x0034 0x003F Reserved 0x0040 0x00CE Pad Configuration Registers PCR 0 71 on page 248 0x00D0 0x04FF Reserved 0x0500 0x0520 Pad Selection for Multiplexed Inputs registers ...

Page 243: ...This register contains the part number and the package ID of the device 0x0C9C 0x0FFF Reserved 0x1000 0x1060 Interrupt Filter Maximum Counter registers 0 24 IFMC 0 24 on page 257 0x1064 0x107C Reserved 0x1080 Interrupt Filter Clock Prescaler Register IFCPR on page 257 0x1084 0x3FFF Reserved Always reads 1 1 Always reads 0 0 R W bit BIT Read only bit BIT Write only bit Write 1 to clear BIT Self cle...

Page 244: ...01_0110_0000_0011 384 KB For the full part number this field needs to be combined with MIDR2 PARTNUM 23 16 CSP Always reads back 0 PKG 4 0 Package Settings Can by read by software to determine the package type that is used for the particular device 00001 64 pin LQFP 01001 100 pin LQFP MAJOR_MASK 3 0 Major Mask Revision Counter starting at 0x0 Incremented each time a resynthesis is done MINOR_MASK ...

Page 245: ... device sales type 0 0 0 0 Figure 11 4 MCU ID Register 2 MIDR2 Table 11 4 MIDR2 field descriptions Field Description SF Manufacturer 0 Freescale 1 Reserved FLASH_SIZE_1 3 0 Coarse granularity for Flash memory size Needs to be combined with FLASH_SIZE_2 to calculate the actual memory size 0011 128 KB 0100 256 KB Other values are reserved FLASH_SIZE_2 3 0 Fine granularity for Flash memory size Needs...

Page 246: ...SR Table 11 5 ISR field descriptions Field Description EIFn External Interrupt Status Flag n This flag can be cleared only by writing a 1 Writing a 0 has no effect If enabled IRERn EIFn causes an interrupt request 0 No interrupt event has occurred on the pad 1 An interrupt event as defined by IREERn and IFEERn has occurred Address Base 0x0018 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 ...

Page 247: ... 22 23 24 25 26 27 28 29 30 31 R IREE 15 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 11 7 Interrupt Rising Edge Event Enable Register IREER Table 11 7 IREER field descriptions Field Description IREEn Enable rising edge events to cause the EIFn bit to be set 0 Rising edge event disabled 1 Rising edge event enabled Address Base 0x002C Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15...

Page 248: ...O pads Each PCR controls the characteristics of a single pad NOTE 16 32 bit access is supported for the PCR 0 71 registers Address Base 0x0030 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R IFE 24 16 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R IFE 15 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 11 9 Interrupt Filter Enable Register ...

Page 249: ...ds of the number of actual alternate functions provided for each pad Please see the MPC5602P Datasheet MPC5602P OBE Output Buffer Enable This bit enables the output buffer of the pad in case the pad is in GPIO mode 0 Output buffer of the pad disabled when PA 00 1 Output buffer of the pad enabled when PA 00 IBE Input Buffer Enable This bit enables the input buffer of the pad 0 Input buffer of the p...

Page 250: ...heral inputs Thus it is possible to define different pads to be possible inputs for a certain peripheral function Table 11 11 PCR n reset value exceptions Field Description PCR 2 PCR 3 PCR 4 These registers correspond to the ABS 0 ABS 1 and FAB boot pins respectively Their default state is input pull enabled Their reset value is 0x0102 PCR 20 This register corresponds to the TDO pin Its default st...

Page 251: ... 0 PADSEL3 3 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 11 11 Pad Selection for Multiplexed Inputs registers PSMI 0_3 32_35 Table 11 13 PSMI 0_3 32_35 field descriptions Field Description PADSEL0 3 PADSEL32 35 Pad Selection Bits Each PADSEL field selects the pad currently used for a certain input function See Table 11 14 Pad selection Table 11 14 Pad selection Register PADSEL Module Port PAD...

Page 252: ...SEL0 flexpwm0 FAULT0 0000 A 9 60 94 0001 A 13 61 95 PADSEL1 flexpwm0 FAULT1 0000 C 10 78 0001 D 6 23 PADSEL2 PADSEL3 PSMI20_23 PADSEL0 PADSEL1 PADSEL2 PADSEL3 PSMI24_27 PADSEL0 PADSEL1 PADSEL2 PADSEL3 PSMI28_312 PADSEL0 PADSEL1 PADSEL2 PADSEL3 LINflex0 RXD Receive Data Input Line 0000 B 3 80 0001 B 7 20 29 PSMI32_353 PADSEL0 LINflex1 RXD Receive Data Input Line 0000 B 13 30 42 0001 D 12 45 70 Tabl...

Page 253: ...crocontroller Reference Manual Rev 4 Freescale Semiconductor 253 1 Values not listed are reserved 2 Writing to PADSELx 3 1 has no effect a write to these three bits will return 0 3 Writing to PADSELx 3 2 has no effect a write to these two bits will return 0 ...

Page 254: ...PDO 3 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 11 12 Port GPIO Pad Data Output registers 0_3 68_71 GPDO 0_3 68_71 Table 11 15 GPDO 0_3 68_71 field descriptions Field Description PDO n Pad Data Out This bit stores the data to be driven out on the external GPIO pad controlled by this register 0 Logic low value is driven on the corresponding GPIO pad when the pad is configured as an output 1 Lo...

Page 255: ...esponding GPIO pad is logic low 1 The value of the data in signal for the corresponding GPIO pad is logic high Address Base 0x0C00 PGPDO0 Base 0x0C04 PGPDO1 Base 0x0C05 PGPDO2 Base 0x0C0C PGPDO3 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R PPDO x 15 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R PPDO x 1 15 0 W Reset 0 0 0 0 0 0 0 0 0 ...

Page 256: ... 0 0 0 0 0 0 0 Figure 11 15 Parallel GPIO Pad Data In register 0 3 PGPDI 0 3 Table 11 18 PGPDI 0 3 field descriptions Field Description PPDI x Parallel Pad Data In Read the current pad value Accesses to this register location are coherent with accesses to the bit wise GPIO Pad Data Input registers 0_3 68_71 GPDI 0_3 68_71 The x and bit index define which PPDI register bit is equivalent to which PD...

Page 257: ... driven on the pad in output mode Accesses to this register location are coherent with accesses to the bit wise GPIO Pad Data Output registers 0_3 68_71 GPDO 0_3 68_71 The x and bit index define which MPPDO register bit is equivalent to which PDO register bit according to the following equation MPPDO x y PDO x 16 y Address Base 0x1000 IFMC0 Base 0x1060 IFMC24 25 registers Access User read write 0 ...

Page 258: ...0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 IFCP 3 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 11 18 Interrupt Filter Clock Prescaler Register IFCPR Table 11 21 IFCPR field descriptions Field Description IFCP 3 0 Interrupt Filter Clock Prescaler setting Prescaled Filter Clock Period TIRC IFCP 1 TIRC is the internal osci...

Page 259: ...ches Safe mode behavior configuration 11 6 3 General purpose input and output pads GPIO The SIUL allows each pad to be configured as either a General Purpose Input Output pad GPIO and as one or more alternate functions input or output the function of which is normally determined by the peripheral that uses the pad The SIUL manages up to 64 GPIO pads organized as ports that can be accessed for data...

Page 260: ...non GPIO this write will not be reflected by the pad value until reconfigured to GPIO The allocation of what input function is connected to the pin is defined by the PSMI registers see Section 11 5 2 9 Pad Selection for Multiplexed Inputs registers PSMI 0_3 32_35 11 6 4 External interrupts The SIUL supports 25 external interrupts EIRQ 0 24 The signal description chapter of this reference manual pr...

Page 261: ...active rising edge an active falling edge or both edges being active A setting of having both edge events disabled is reserved and should not be configured The active EIRQ edge is controlled through the configuration of the registers IREER and IFEER Each external interrupt supports an individual flag that is held in the ISR see Section 11 5 2 3 Interrupt Status Flag Register ISR This register is a...

Page 262: ...Chapter 11 System Integration Unit Lite SIUL MPC5602P Microcontroller Reference Manual Rev 4 262 Freescale Semiconductor ...

Page 263: ... VLE only design with 32 bit general purpose registers GPRs Implementing only the VLE variable length encoding APU provides improved code density All arithmetic instructions that execute in the core operate on data in the GPRs 12 2 Features The following is a list of some of the key features of the e200z0 and e200z0h cores 32 bit Power Architecture technology VLE only programmer s model Single iss...

Page 264: ...te certain taken branches in the e200z0 Prefetched instructions are placed into an instruction buffer with 4 entries 2 entries in e200z0 each capable of holding a single 32 bit instruction or a pair of 16 bit instructions Conditional branches that are not taken execute in a single clock Branches with successful target prefetching have an effective execution time of one clock on e200z0h All other t...

Page 265: ... 265 Figure 12 1 e200z0 block diagram CPU CONTROL LOGIC INSTRUCTION UNIT BRANCH UNIT PC UNIT INSTRUCTION BUFFER GPR CR SPR MULTIPLY UNIT OnCE NEXUS CONTROL LOGIC INTERFACE CONTROL DATA MTSPR MFSPR INTEGER EXECUTION UNIT EXTERNAL SPR CTR XER LR DATA ADDRESS BUS INTERFACE UNIT CONTROL 32 32 N LOAD STORE UNIT ...

Page 266: ... many as two 16 bit VLE instructions per clock Instruction buffer with 4 entries in e200z0h each holding a single 32 bit instruction or a pair of 16 bit instructions CPU CONTROL LOGIC DATA NEXUS DEBUG UNIT ADDRESS LOAD STORE UNIT INSTRUCTION UNIT BRANCH UNIT PC UNIT INSTRUCTION BUFFER GPR CR SPR MULTIPLY UNIT DATA BUS INTERFACE UNIT CONTROL 32 32 N OnCE NEXUS CONTROL LOGIC INTERFACE CONTROL DATA M...

Page 267: ... 8 32 hardware multiplier array supports 1 to 4 cycle 32 32 32 multiply early out 12 2 1 4 Load Store unit features The e200 load store unit supports load store and the load multiple store multiple instructions 32 bit effective address adder for data memory address calculations Pipelined operation supports throughput of one load or store operation per cycle 32 bit interface to memory dedicated mem...

Page 268: ...200z0h cores It includes an overview of registers defined by the Power Architecture technology highlighting differences in how these registers are implemented in the e200 core and provides a detailed description of e200 specific registers Full descriptions of the architecture defined register set are provided in Power Architecture Specification The Power Architecture defines register to register o...

Page 269: ...SPR 313 SPR 314 SPR 315 Data Address Compare DAC1 DAC2 SPR 316 SPR 317 1 These e200 specific registers may not be supported by other Power Architecture processors 2 Optional registers defined by the Power Architecture technology Processor Version Hardware Implementation Dependent1 HID0 HID1 SPR 1008 SPR 1009 SPR 9 General Purpose Registers Count Register CTR SPR 8 Link Register LR Condition Regist...

Page 270: ...315 Data Address Compare DAC1 DAC2 SPR 316 SPR 317 1 These e200 specific registers may not be supported by other Power Architecture processors 2 Optional registers defined by the Power Architecture technology Processor Version Hardware Implementation Dependent1 HID0 HID1 SPR 1008 SPR 1009 SPR 9 General Purpose Registers Count Register CTR SPR 8 Link Register LR Condition Register CR GPR0 GPR1 GPR3...

Page 271: ... MSR PR 0 an illegal instruction exception is generated For the mtspr instruction if the SPR specified is read only and not privileged an illegal instruction exception is generated If the SPR specified is read only and privileged and the core is in user mode MSR PR 1 a privileged instruction exception is generated If the SPR specified is read only and privileged and the core is in supervisor mode ...

Page 272: ...Chapter 12 e200z0 and e200z0h Core MPC5602P Microcontroller Reference Manual Rev 4 272 Freescale Semiconductor ...

Page 273: ...width peripherals Accesses that fall within the address space of the PBRIDGE are decoded to provide individual module selects for peripheral devices on the slave bus interface As shown in Figure 13 1 the asynchronous bridge is a dedicated module that resynchronizes signals synchronous to the system clock SYS_CLK to the ones synchronous to the motor control clock MC_PLL_CLK The PBRIDGE has the foll...

Page 274: ...Bridge when the requested access size is 32 bits or smaller and is not misaligned across a 32 bit boundary 13 2 1 3 Write cycles Three clock write accesses are possible with the Peripheral Bridge when the requested access size is 32 bits or smaller Misaligned writes that cross a 32 bit boundary are not supported 13 2 2 General operation Slave peripherals are modules that contain readable writable ...

Page 275: ...56xx products except that it cannot be configured by software and that it has a hard wired configuration 14 2 Block diagram Figure 14 1 shows a block diagram of the crossbar switch Figure 14 1 XBAR block diagram Table 14 1 gives the crossbar switch port for each master and slave the assigned and fixed ID number for each master and shows the master ID numbers as they relate to the master port numbe...

Page 276: ...ns Requesting masters are granted access based on a fixed priority 14 4 Features 3 Master ports e200z0 core complex Instruction port e200z0 core complex Load Store Data port eDMA 3 Slave ports Flash memory code and data Internal SRAM Peripheral bridge 32 bit internal address 32 bit internal data paths Fully concurrent transfers between independent master and slave ports Fixed priority scheme and f...

Page 277: ... priority level and the responding slave s access time Because the XBAR appears to be just another slave to the master device the master device has no indication that it owns the slave port it is targeting While the master does not have control of the slave port it is targeting it is wait stated A master is given control of a targeted slave port only after a previous access to a different slave po...

Page 278: ...r priority master is also waiting for the slave port A master access is responded to with an error if the access decodes to a location not occupied by a slave port This is the only time the XBAR directly responds with an error response All other error responses received by the master are the result of error responses on the slave ports being passed through the XBAR 14 6 4 Slave ports The goal of t...

Page 279: ...priority master is granted control at the termination of any currently pending access assuming the pending transfer is not part of a burst transfer A new requesting master must wait until the end of the fixed length burst transfer before it is granted control of the slave port But if the new requesting master s priority level is lower than that of the master that currently has control of the slave...

Page 280: ...Chapter 14 Crossbar Switch XBAR MPC5602P Microcontroller Reference Manual Rev 4 280 Freescale Semiconductor ...

Page 281: ... the platform device configuration and revision Reset status register MRSR Registers for capturing information on platform memory errors if error correcting codes ECC are implemented Registers to specify the generation of single and double bit memory data inversions for test purposes if error correcting codes are implemented Access address information for faulted memory accesses for certain proces...

Page 282: ...E Reserved 0x000F MRSR Miscellaneous Reset Status register on page 285 8 0x0010 0x001E Reserved 0x001F MIR Miscellaneous Interrupt register on page 286 8 0x0020 0x0023 Reserved 0x0024 MUDCR Miscellaneous User Defined Control Register on page 287 32 0x0028 0x0042 Reserved 0x0043 ECR ECC Configuration register on page 288 8 0x0044 0x0046 Reserved 0x0047 ESR ECC Status register on page 289 8 0x0048 0...

Page 283: ...his register is defined by a module input signal it can only be read from the IPS programming model Any attempted write is ignored 15 4 2 2 Revision REV register The REV is a 16 bit read only register specifying a revision number The state of this register is defined by an input signal it can only be read from the IPS programming model Any attempted write is ignored 0x0066 REMR RAM ECC Master regi...

Page 284: ...read from the IPS programming model Any attempted write is ignored Address Base 0x0002 Access User read only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R REV 15 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 15 2 Revision REV register Table 15 3 REV field descriptions Name Description 0 15 REV 15 0 Revision The REV 15 0 field is specified by an input signal to define a software visible revision numbe...

Page 285: ...e MRSR can only be read from the IPS programming model Any attempted write is ignored Table 15 5 ASC field descriptions Field Description DP64 64 bit Datapath 0 Datapath width is 32 bits 1 Datapath width is 64 bits ASC 7 0 XBAR Slave Configuration 0 Bus slave connection to XBAR output port n is not present 1 Bus slave connection to XBAR output port n is present Address Base 0x0008 Access User read...

Page 286: ...nput reset Address Base 0x001F Access User read write 0 1 2 3 4 5 6 7 R FB0AI FB0SI FB1AI FB1SI 0 0 0 0 W 1 1 1 1 x x x x Reset 0 0 0 0 0 0 0 0 Figure 15 7 Miscellaneous Interrupt Register MIR Table 15 8 MIR field descriptions Field Description 0 FB0AI Flash Bank 0 Abort Interrupt 0 A flash bank 0 abort has not occurred 1 A flash bank 0 abort has occurred The interrupt request is negated by writin...

Page 287: ...T Flash ECC Data Register FEDR RAM ECC Address Register REAR RAM ECC Syndrome Register RESR RAM ECC Master Number Register REMR RAM ECC Attributes Register REAT RAM ECC Data Register REDR Address Base 0x0024 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R MUDC R 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R...

Page 288: ...capability is viewed as important for error logging and failure analysis Address Base 0x0043 Access User read write 0 1 2 3 4 5 6 7 R 0 0 ER1BR EF1BR 0 0 ERNCR EFNCR W Reset 0 0 0 0 0 0 0 0 Figure 15 9 ECC Configuration register ECR Table 15 10 ECR field descriptions Field Description 2 ER1BR Enable RAM 1 bit Reporting This bit can only be set if the input enable signal is asserted This signal is ...

Page 289: ...rted at any given time This preserves the association between the ESR and the corresponding address and attribute registers which are loaded on each occurrence of an properly enabled ECC event If there is a pending ECC interrupt and another properly enabled ECC event occurs the ECSM hardware automatically handles the ESR reporting clearing the previous data and loading the new state and thus guara...

Page 290: ... to this bit Writing a 0 has no effect 0 No reportable single bit RAM correction detected 1 Reportable single bit RAM correction detected 3 F1BC Flash 1 bit Correction This bit can only be set if ECR EF1BR is asserted The occurrence of a properly enabled single bit flash correction generates a ECSM ECC interrupt request The address attributes and data are also captured in the FEAR FEMR FEAT and FE...

Page 291: ...oller to create 1 bit data inversions as defined by the bit position specified in ERRBIT 6 0 continuously on every write operation The normal ECC generation takes place in the RAM controller but then the polarity of the bit position defined by ERRBIT is inverted to introduce a 1 bit ECC event in the RAM After this bit has been enabled to generate another continuous 1 bit data inversion it must be ...

Page 292: ...ble Data Inversions 0 No RAM single 2 bit data inversions generated 1 One 2 bit data inversion in the RAM generated The assertion of this bit forces the RAM controller to create one 2 bit data inversion as defined by the bit position specified in ERRBIT 6 0 and the overall odd parity bit on the first write operation after this bit is set The normal ECC generation takes place in the RAM controller ...

Page 293: ...es FEAT register The FEAT is an 8 bit register for capturing the XBAR bus master attributes of the last properly enabled ECC event in the flash memory Depending on the state of the ECC Configuration Register an ECC event Address Base 0x0050 Access User read only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R FEAR 31 16 W Reset 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R FEAR 15 0 W Reset Figure 15 ...

Page 294: ...and FEDR registers and the appropriate flag F1BC or FNCE in the ECC Status Register to be asserted The data captured on a multi bit non correctable ECC error is undefined This register can only be read from the IPS programming model any attempted write is ignored Address Base 0x0057 Access User read only 0 1 2 3 4 5 6 7 R WRITE SIZE 2 0 PROTECTION 3 0 W Reset 0 0 0 0 Figure 15 14 Flash ECC Attribu...

Page 295: ...Access User read only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R FEDR 31 16 W Reset 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R FEDR 15 0 W Reset Figure 15 15 Flash ECC Data register FEDR Table 15 16 FEDR field descriptions Name Description 0 31 FEDR 31 0 Flash ECC Data Register This 32 bit register contains the data associated with the faulting access of the last properly enabled flash ECC eve...

Page 296: ...1 implies no error condition but this value is not readable when the PRESR is read for the no error case Address Base 0x0065 Access User read only 0 1 2 3 4 5 6 7 R RESR 7 0 W Reset Figure 15 17 RAM ECC Syndrome Register RESR Table 15 18 RESR field descriptions Name Description 0 7 RESR 7 0 RAM ECC Syndrome Register This 8 bit syndrome field includes 6 bits of Hamming decoded parity plus an odd pa...

Page 297: ...x28 DATA ODD BANK 17 0x2A DATA ODD BANK 16 0x2C DATA ODD BANK 15 0x58 DATA ODD BANK 14 0x30 DATA ODD BANK 13 0x32 DATA ODD BANK 12 0x34 DATA ODD BANK 11 0x64 DATA ODD BANK 10 0x38 DATA ODD BANK 9 0x62 DATA ODD BANK 8 0x70 DATA ODD BANK 7 0x60 DATA ODD BANK 6 0x40 ECC ODD 6 0x42 DATA ODD BANK 5 0x44 DATA ODD BANK 4 0x46 DATA ODD BANK 3 0x48 DATA ODD BANK 2 0x4A DATA ODD BANK 1 0x4C DATA ODD BANK 0 ...

Page 298: ...properly enabled ECC event in the RAM memory Depending on the state of the ECC Configuration Register an ECC event in the RAM causes the address attributes and data associated with the access to be loaded into the REAR RESR REMR REAT and REDR registers and the appropriate flag R1BC or RNCE in the ECC Status Register to be asserted This register can only be read from the IPS programming model any a...

Page 299: ...rror is undefined This register can only be read from the IPS programming model any attempted write is ignored 1 3 SIZE 2 0 AMBA AHB HSIZE 2 0 000 8 bit AMBA AHB access 001 16 bit AMBA AHB access 010 32 bit AMBA AHB access 1xx Reserved 4 PROTECTION 3 AMBA AHB HPROT 3 Protection 0 Type 0 I Fetch 1 Data 5 PROTECTION 2 AMBA AHB HPROT 2 Protection 1 Mode 0 User mode 1 Supervisor mode 6 PROTECTION 1 AM...

Page 300: ... for each of the five targeted slave modules A block diagram of the ECSM_reg_protection module is shown in Figure 15 21 Figure 15 21 Spp_Ips_Reg_Protection block diagram Attempted accesses to reserved addresses result in an error termination while attempted writes to read only registers are ignored and do not terminate with an error Unless noted otherwise writes to the programming model must match...

Page 301: ...le ECSM MPC5602P Microcontroller Reference Manual Rev 4 Freescale Semiconductor 301 writes etc Attempted writes of a different size than the register width produce an error termination of the bus cycle and no change to the targeted register ...

Page 302: ...Chapter 15 Error Correction Status Module ECSM MPC5602P Microcontroller Reference Manual Rev 4 302 Freescale Semiconductor ...

Page 303: ...ble 16 2 shows the SRAM memory map 16 4 Register descriptions The SRAM has no registers Registers associated with the ECC are located in the ECSM See Section 15 4 2 9 ECC registers 16 5 SRAM ECC mechanism The SRAM ECC detects the following conditions and produces the following results Detects and corrects all 1 bit errors Detects and flags all 2 bit errors as non correctable errors Detects 39 bit ...

Page 304: ...s appended to the 32 bits from the data bus and the 39 bit value is then written to SRAM 16 5 1 Access timing The system bus is a two stage pipelined bus that makes the timing of any access dependent on the access during the previous clock Table 16 3 lists the various combinations of read and write operations to SRAM and the number of wait states used for the each operation The table columns conta...

Page 305: ...ed by executing 32 bit write operations prior any read accesses This is also true for implicit read accesses caused by any write accesses smaller than 32 bits as discussed in Section 16 5 SRAM ECC mechanism 16 7 Initialization and application information To use the SRAM the ECC must check all bits that require initialization after power on All writes must specify an even number of registers perfor...

Page 306: ...Chapter 16 Internal Static RAM SRAM MPC5602P Microcontroller Reference Manual Rev 4 306 Freescale Semiconductor ...

Page 307: ...ogram and data It intelligently converts the protocols between the system bus and the dedicated Flash array interfaces Several important terms are used to describe the platform Flash controller module and its connections These terms are defined here Port This term describes the AMBA AHB connection s into the platform Flash controller From an architectural and programming model viewpoint the defini...

Page 308: ...t any prefetching Prefetch buffer hits from the code Flash bank support 0 wait AHB data phase responses AHB read requests that miss the buffers generate the needed Flash array access and are forwarded to the AHB upon completion typically incurring two wait states at an operating frequency of 60 to 64 MHz This memory controller is optimized for applications where a cacheless processor core for exam...

Page 309: ... AHB crossbar or memory protection unit slave port and connections with as many as two banks code and data of Flash memory each containing one instantiation of the Flash array Additionally the operating configuration for the platform Flash controller is defined by the contents of certain code Flash array0 registers that are inputs to the module 17 2 4 Memory map and registers description Two memor...

Page 310: ...PR NOTE Flash memory configuration registers should be written only with 32 bit write operations to avoid any issues associated with register incoherency caused by bit fields spanning smaller size 8 16 bit boundaries For additional information on the address based read access timing for emulation of other memory types see Section 17 2 17 Wait state emulation Table 17 1 Flash related regions in the...

Page 311: ...s is shown in Table 17 2 17 2 5 Functional description The platform Flash controller interfaces between the AHB Lite 2 v6 system bus and the Flash memory arrays The platform Flash controller generates read and write enables the Flash array address write size and write data as inputs to the Flash array The platform Flash controller captures read data from the Flash array interface and drives it ont...

Page 312: ...of other memories that have different access time characteristics The added wait state specifications are provided by bit 28 to bit 24 of Flash address haddr 28 24 see Table 17 4 and Table 17 5 These wait states are applied in addition to the normal wait states incurred for Flash accesses Refer to Section 17 2 17 Wait state emulation for more details Prefetching of next sequential page is blocked ...

Page 313: ...3 0 driving write data on bkn_fl_wdata 63 0 and asserting bkn_fl_wr_en Again the controller drives the address and control information for the required setup time before the rising edge of hclk and provides the required amount of hold time The platform Flash controller then waits for the appropriate number of write wait states before terminating the write operation On the cycle following the progr...

Page 314: ...r_err to terminate a requested access with an error This may occur due to an uncorrectable ECC error or because of improper sequencing during program erase operations When an error response is received the platform Flash controller does not update or validate a bank0 page read buffer nor the bank1 temporary holding register An error response may be signaled on read or write operations For more inf...

Page 315: ...ta that has been provided to satisfy an AHB burst type read 3 Valid the buffer contains valid data that has been provided to satisfy an AHB single type read 4 Prefetched the buffer contains valid data that has been prefetched to satisfy a potential future AHB access 5 Busy AHB the buffer is currently being used to satisfy an AHB burst read 6 Busy Fill the buffer has been allocated to receive data ...

Page 316: ...tition two configurations are supported In one configuration buffers 0 and 1 are allocated for instruction fetches and buffers 2 and 3 for data accesses In the second configuration buffers 0 1 and 2 are allocated for instruction fetches and buffer 3 reserved for data accesses 17 2 14 4 Buffer invalidation The page read buffers may be invalidated under hardware or software control Any falling edge ...

Page 317: ...iced in 0 AHB wait states as the stored read data is routed from the temporary register back to the requesting bus master The contents of the holding register are invalidated by the falling edge transition of bk1_fl_done and on any non sequential access with a non zero value on haddr 28 24 to support wait state emulation in the same manner as the bank0 page buffers Additionally the B1_Py_BFE regis...

Page 318: ...valid it is forwarded to the AHB bus and hready_out negated to terminate the system bus transfer BKn_RWWC 0b110 This setting is similar to the basic stall while write capability provided when BKn_RWWC 0b111 with the added ability to generate a notification interrupt if a read arrives while the array is busy with a program erase operation There are two notification interrupts one for each bank BKn_...

Page 319: ...cycles are not affected In addition no page read buffer prefetches are initiated and buffer hits are ignored Table 17 4 and Table 17 5 show the relationship of haddr 28 24 to the number of additional primary wait states These wait states are applied to the initial access of a burst fetch or to single beat read accesses on the AHB system bus Note that the wait state specification consists of two co...

Page 320: ...ocessor accesses to the platform memories for example Flash and SRAM plays a major role in the overall system performance Given the core platform pipeline structure the platform s memory controllers PFlash PRAM are designed to provide a 0 wait state data phase response to maximize processor performance The following diagrams illustrate operation of various cycle types and responses referenced earl...

Page 321: ... seq seq addr y addr y 4 addr y 12 C y C y 4 okay okay okay okay okay okay okay okay y C y C y 4 Read no buffering no prefetch APC 0 RWSC 0 PFLM 0 1 2 3 4 5 6 7 8 addr y seq addr y 8 y 4 y 8 C y 8 C y 12 y 12 addr y 4 addr y 8 C y 8 C y 12 hclk htrans haddr hprot hwrite hrdata hwdata hready_out hresp bkn_fl_addr bkn_fl_rd_en bkn_fl_wr_en bkn_fl_rdata addr 12 ...

Page 322: ...ed nonseq seq seq addr y addr y 4 addr y 12 C y C y 4 okay okay okay okay okay okay okay okay y C y Burst Read buffer miss no prefetch APC 2 RWSC 2 PFLM 0 1 2 3 4 5 6 7 8 addr y seq addr y 8 y 4 addr y 4 C y 4 y 8 addr y 8 hclk htrans haddr hprot hwrite hrdata hwdata hready_out hresp bkn_fl_addr bkn_fl_rd_en bkn_fl_wr_en bkn_fl_rdata bkn_fl_xfr_err addr y ...

Page 323: ...fering enabled nonseq seq seq addr y addr y 4 addr y 12 C y C y 4 C y 8 C y 12 okay okay okay okay okay okay okay okay Y C y Burst Read buffer miss no prefetch APC 2 RWSC 2 PFLM 0 1 2 3 4 5 6 7 8 addr y seq addr y 8 hclk htrans haddr hprot hwrite hrdata hwdata hready_out hresp bkn_fl_addr bkn_fl_wr_en bkn_fl_wr_en bkn_fl_rdata bkn_fl_xfr_err ...

Page 324: ... y addr y 4 addr y 12 C y C y 4 C y 8 C y 12 okay okay okay okay okay okay okay okay y C y Burst Read buffer miss prefetch APC 2 RWSC 2 PFLM 2 1 2 3 4 5 6 7 8 addr y seq addr y 8 y 16 C y 16 seq seq addr y 16 C y 16 y 32 addr y 16 addr y 32 hclk htrans haddr hprot hwrite hrdata hwdata hready_out hresp bkn_fl_addr bkn_fl_rd_en bkn_fl_wr_en bkn_fl_rdata bkn_fl_xfr_err addr y 20 ...

Page 325: ...at throughout cycles 2 9 the AHB bus pipeline is stalled with a read to address y in the AHB data phase and a read to address y 4 in the address phase Depending on the state of the least significant bit of the BKn_RWWC control field the hardware may also signal a stall notification interrupt if BKn_RWWC 110 The stall notification interrupt is shown as the optional assertion of ECSM s MIR FBnSI Fla...

Page 326: ...me cycle in Figure 17 6 because of the terminate operation In cycle 6 the platform Flash controller module retries the read to address y that was interrupted by the negation of bkn_done in cycle 3 Note that throughout cycles 2 9 the AHB bus pipeline is stalled with a read to address y in the AHB data phase and a read to address y 4 in the address phase Depending on the state of the least significa...

Page 327: ...e BIU connects the Flash module to a system bus The MPC5602P provides two Flash modules one 256 KB code Flash module and one 64 KB data module 17 3 2 Main features High read parallelism 128 bits Error Correction Code SEC DED to enhance data retention Double word program 64 bits Sector erase Single bank architecture Read While Modify not available within an individual module Read While Modify can b...

Page 328: ...storage No Read While Modify operations are possible The Modify operations are managed by an embedded Flash Program Erase Controller FPEC Commands to the FPEC are given through a User Registers Interface The read data bus is 128 bits wide while the Flash registers are on a separate 32 bit wide bus The high voltages needed for Program Erase operations are internally generated Figure 17 9 shows the ...

Page 329: ...in a page differ from the other addresses in the page only by address bits 3 2 The Flash page read architecture supports both cache and burst mode at the BIU level for high speed read application The Flash module supports fault tolerance through Error Correction Code ECC and or error detection The ECC implemented within the Flash module will correct single bit failures and detect double bit failur...

Page 330: ... can be performed by reading from one module while writing to another The code Flash Bank 0 is divided in 8 sectors including a reserved sector named TestFlash in which One Time Programmable OTP user data are stored and a Shadow Sector in which user erasable configuration values can be stored see Table 17 6 The data Flash Bank 1 is divided in five sectors including a reserved sector named TestFlas...

Page 331: ...ectorization Bank Sector Addresses Size KB Address space B1 B1F0 0x0080_0000 to 0x0080_3FFF 16 Low Address Space B1 B1F1 0x0080_4000 to 0x0080_7FFF 16 Low Address Space B1 B1F2 0x0080_8000 to 0x0080_BFFF 16 Low Address Space B1 B1F3 0x0080_C000 to 0x0080_FFFF 16 Low Address Space B1 Reserved 0x0081_0000 to 0x00C0_1FFF 4040 Reserved B1 B1TF 0x00C0_2000 to 0x00C0_3FFF 8 Test Address Space B1 Reserve...

Page 332: ...e enabled by the BIU When the Shadow space is enabled all the operations are mapped to the Shadow block User mode program and erase of the shadow block are enabled only when MCR PEAS is set The Shadow block may be locked unlocked against program or erase by using the LML TSLK and SLL STSLK bitfields Program of the Shadow block has similar restriction as the array in terms of how ECC is calculated ...

Page 333: ...fter reset is deasserted read register access may be done although it should be noted that registers that require updating from shadow information or other inputs may not read updated values until MCR DONE transitions MCR DONE may be polled to determine if the Flash module has transitioned out of reset Notice that the registers cannot be written until MCR DONE is high 17 3 5 2 User mode In User mo...

Page 334: ...ddressing is done to blocks that do not exist in non 2n array sizes Interlock writes attempted to invalid locations will result in an interlock occurring but attempts to program these blocks will not occur since they are forced to be locked Erase will occur to selected and unlocked blocks even if the interlock write is to an invalid location Simultaneous read cycles on the code Flash block and rea...

Page 335: ...rites to the Flash are possible When enabled the Flash module returns to its previous state in all cases unless in the process of executing an erase high voltage operation at the time of entering Power down mode If the Flash module is put into Power down mode during an erase operation the MCR ESUS bit is set to 1 The user may resume the erase operation when the Flash module exits Power down mode b...

Page 336: ...349 0x0014 Reserved 0x0018 Address Register ADR on page 349 0x001C Platform Flash Configuration Register 0 PFCR0 1 1 This register is not implemented on the data Flash block on page 351 0x0020 Platform Flash Configuration Register 1 PFCR1 1 on page 354 0x0024 Platform Flash Access Protection Register PFAPR 1 on page 356 0x0028 Reserved 0x003C User Test Register 0 UT0 on page 357 0x0040 User Test R...

Page 337: ...I117 BI116 BI115 BI114 BI113 BI112 BI111 BI110 BI109 BI108 BI107 BI106 BI105 BI104 BI103 BI102 BI101 BI100 0x24 PFAPR BI231 BI230 BI229 BI228 BI227 BI226 BI225 BI224 BI223 BI222 BI221 BI220 BI219 BI218 BI217 BI216 BI215 BI214 BI213 BI212 BI211 BI210 BI209 BI208 BI207 BI206 BI205 BI204 BI203 BI202 BI201 BI200 0x28 Reserved 0x3C UT0 UTE 0 0 0 0 0 0 0 DSI7 DSI6 DSI5 DSI4 DSI3 DSI2 DSI1 DSI0 0 0 0 0 0...

Page 338: ...K7 SLK6 SLK5 SLK4 SLK3 SLK2 SLK1 SLK0 0x10 LMS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSL15 LSL14 LSL13 LSL12 LSL11 LSL10 LSL9 LSL8 LSL7 LSL6 LSL5 LSL4 LSL3 LSL2 LSL1 LSL0 0x14 Reserved 0x18 ADR 0 0 0 0 0 0 0 0 0 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 0 0 0 0x1C 0x3B Reserved 0x3C UT0 UTE 0 0 0 0 0 0 0 DSI7 DSI6 DSI5 DSI4 DSI3 DSI2 DSI1 DSI0 0 0 0 0 0...

Page 339: ...ed with all 1s and the Flash initialization ends by clearing the MCR PEG bit 17 3 7 1 Module Configuration Register MCR The Module Configuration Register enables and monitors all the modify operations of each Flash module Identical MCRs are provided in the code Flash and the data Flash blocks 0x50 0x5B Reserved Address Base 0x0000 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R EDC ...

Page 340: ...7 Array space SIZE 2 0 The value of SIZE field depends on the size of the Flash module 000 128 KB 001 256 KB the value for the MPC5602P device in the code Flash module 010 512 KB 011 Reserved 1024 KB 100 Reserved 1536 KB 101 Reserved 2048 KB 110 64 KB the value for the device in the data Flash module 111 Reserved Note The value for this bitfield is different between the code and data Flash modules...

Page 341: ...e user If RWE is not set or remains 0 this indicates that all previous RWW reads from the last reset or clearing of RWE were correct Since this bit is an error flag it must be cleared to 0 by writing 1 to the register location A write of 0 will have no effect 0 Reads are occurring normally 1 A RWW Error occurred during a previous read Note If stall terminate while write is used the software should...

Page 342: ...l PGM ERS makes a 1 to 0 transition or EHV makes a 0 to 1 transition The value in PEG is not valid after a 0 to 1 transition of DONE caused by ESUS being set to logic 1 If program or erase are attempted on blocks that are locked the response is PEG 1 indicating that the operation was successful and the content of the block were properly protected from the program or erase operation If a program op...

Page 343: ...E 1 and EHV 1 and PGM 0 A 1 to 0 transition of ESUS with EHV 1 starts the sequence that clears DONE and returns the Module to Erase The Flash module cannot exit Erase Suspend and clear DONE while EHV is low ESUS is cleared on reset 0 Erase sequence is not suspended 1 Erase sequence is suspended EHV 31 Enable High Voltage The EHV bit enables the Flash module for a high voltage program Erase operati...

Page 344: ...LML register has a related Non Volatile Low Mid Address Space Block Locking register NVLML located in TestFlash that contains the default reset value for LML The NVLML register is read during the reset phase of the Flash module and loaded into the LML The reset value is 0x00XX_XXXX initially determined by the NVLML value from test sector Table 17 14 MCR bits set clear priority levels Priority leve...

Page 345: ...word 0xA1A11111 must be written to the LML register 0 Low Address Locks are disabled TSLK and LLK 15 0 cannot be written 1 Low Address Locks are enabled TSLK and LLK 15 0 can be written 1 10 Reserved Read Only A write to these bits has no effect A read of these bits always outputs 0 TSLK 11 Test Shadow Address Space Block Lock This bit locks the block of Test and Shadow Address Space from program ...

Page 346: ...rmation A value of 1 in a bit of the LLK bitfield signifies that the corresponding block is locked for program and Erase A value of 0 in a bit of the LLK bitfield signifies that the corresponding block is available to receive program and Erase pulses The LLK bitfield is not writable once an interlock write is completed until MCR DONE is set at the completion of the requested operation Likewise the...

Page 347: ...2 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 STS LK 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 x 0 0 x x 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R SLK 15 SLK 14 SLK 13 SLK 12 SLK 11 SLK 10 SLK 9 SLK 8 SLK 7 SLK 6 SLK 5 SLK 4 SLK 3 SLK 2 SLK 1 SLK 0 W Reset x x x x x x x x x x x x x x x x Figure 17 14 Non Volatile Secondary Low Mid Address Space Block Locking register NVSLL Table 17 16 SLL and NVSLL field...

Page 348: ...locks of Low Address Space from program and Erase For code Flash SLK 5 0 are related to sectors B0F 5 0 respectively See Table 17 6 for more information For data Flash SLK 3 0 are related to sectors B1F 3 0 respectively See Table 17 7 for more information A value of 1 in a bit of the SLK register signifies that the corresponding block is locked for program and Erase A value of 0 in a bit of the SL...

Page 349: ... has no effect A read of these bits always outputs 0 14 15 Reserved LSL 15 0 16 31 Low Address Space Block Select 15 0 A value of 1 in the select register signifies that the block is selected for erase A value of 0 in the select register signifies that the block is not selected for erase The reset value for the select register is 0 or unselected For code Flash LSL 5 0 are related to sectors B0F 5 ...

Page 350: ...R PEG cleared ADR also provides the first address at which a ECC single error correction occurs MCR EDC set The ECC double error detection takes the highest priority followed by the RWW error the FPEC error and the ECC single error correction When accessed ADR will provide the address related to the first event occurred with the highest priority The priorities between these four possible events is...

Page 351: ...0_RWWC B0_P0_BCFG B0_P0_DPFE B0_P0_IPFE B0_P0_PFLM B0_P0_BFE W Reset 1 0 0 0 0 0 0 0 1 1 1 0 1 1 0 1 Figure 17 17 Platform Flash Configuration Register 0 PFCR0 Table 17 20 PFCR0 field descriptions Field Description 0 4 BK0_APC Bank0 Address Pipelining Control This field controls the number of cycles between Flash array access requests This field must be set to a value appropriate to the operating ...

Page 352: ...APC RWSC 0 23 MHz 45 MHz APC RWSC 1 45 MHz 68 MHz APC RWSC 2 68 MHz 90 MHz APC RWSC 3 This field is set to 0b00010 by hardware reset 00000 No additional wait states are added 00001 1 additional wait state is added 00010 2 additional wait states are added 111111 31 additional wait states are added 15 16 24 BK0_RWWC Bank0 Read While Write Control This 3 bit field defines the controller response to F...

Page 353: ...is triggered by a data read access 1 If page buffers are enabled B0_P0_BFE 1 prefetching is triggered by any data read access 28 B0_P0_IPFE Bank0 Port 0 Instruction Prefetch Enable This field enables or disables prefetching initiated by an instruction fetch read access This field is set by hardware reset 0 No prefetching is triggered by an instruction fetch read access 1 If page buffers are enable...

Page 354: ... 0 0 0 B1_P1_BFE BK1_RWWC 0 0 0 0 0 0 B1_P0_BFE W Reset 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 Figure 17 18 Platform Flash Configuration Register 1 PFCR1 Table 17 21 PFCR1 field descriptions Field Description 0 4 BK1_APC Bank1 Address Pipelining Control This field controls the number of cycles between Flash array access requests This field must be set to a value appropriate to the operating frequency of ...

Page 355: ...SC 0 23 MHz 45 MHz APC RWSC 1 45 MHz 68 MHz APC RWSC 2 68 MHz 90 MHz APC RWSC 3 This field is set to 0b00010 by hardware reset 00000 No additional wait states are added 00001 1 additional wait state is added 00010 2 additional wait states are added 111111 31 additional wait states are added 15 16 24 BK1_RWWC Bank1 Read While Write Control This 3 bit field defines the controller response to Flash r...

Page 356: ...a Flash block 23 B1_P1_BFE Bank1 Port 1 Buffer Enable This bit enables or disables read hits from the 128 bit holding register It is also used to invalidate the contents of the holding register This bit is set by hardware reset enabling the use of the holding register 0 The holding register is disabled from satisfying read requests 1 The holding register is enabled to satisfy read requests on hits...

Page 357: ...x 0 1 2 7 These bits control whether prefetching may be triggered based on the master number of the requesting AHB master This field is further qualified by the PFCR0 B0_Px_DPFE B0_Px_IPFE Bx_Py_BFE bits 0 Prefetching may be triggered by this master 1 No prefetching may be triggered by this master 16 31 MxAP Master x Access Protection x 0 1 2 7 These fields control whether read and write accesses ...

Page 358: ...bits always outputs 0 25 Reserved Read Write This bit can be written and its value can be read back but there is no function associated This bit is not accessible whenever MCR DONE or UT0 AID are low Reads return indeterminate data and writes have no effect MRE 26 Margin Read Enable MRE enables margin reads to be done This bit combined with MRV enables regular user mode reads to be replaced by mar...

Page 359: ...prietary sequence 1 Array Integrity or Margin Mode sequence is sequential AIE 31 Array Integrity Enable AIE set to 1 starts the Array Integrity Check done on all selected and unlocked blocks The pattern is selected by AIS and the MISR UMISR0 4 can be checked after the operation is complete to determine if a correct signature is obtained AIE can be set only if MCR ERS MCR PGM and MCR EHV are all lo...

Page 360: ... Array Input 31 0 These bits represent the input of the even word of ECC logic used in the ECC Logic Check The DAI 31 0 bits correspond to the 32 array bits representing Word 0 within the double word 0 The array bit is forced at 0 1 The array bit is forced at 1 Address Base 0x0044 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R DAI 63 DAI 62 DAI 61 DAI 60 DAI 59 DAI 58 DAI 57 DAI 56...

Page 361: ...tiple Input Signature Register 0 UMISR0 Table 17 26 UMSIR0 field descriptions Field Description MS 031 000 0 31 Multiple input Signature 031 000 These bits represent the MISR value obtained by accumulating the bits 31 0 of all the pages read from the Flash memory The MS can be seeded to any value by writing the UMISR0 register Address Base 0x004C Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12...

Page 362: ...R3 is not accessible whenever MCR DONE or UT0 AID are low Reads return indeterminate data Writes have no effect NOTE This register is not implemented on the data Flash block Address Base 0x0050 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R MS 095 MS 094 MS 093 MS 092 MS 091 MS 090 MS 089 MS 088 MS 087 MS 086 MS 085 MS 084 MS 083 MS 082 MS 081 MS 080 W Reset 0 0 0 0 0 0 0 0 0 0 0 0...

Page 363: ...MS 115 MS 114 MS 113 MS 112 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R MS 111 MS 110 MS 109 MS 108 MS 107 MS 106 MS 105 MS 104 MS 103 MS 102 MS 101 MS 100 MS 099 MS 098 MS 097 MS 096 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 17 26 User Multiple Input Signature Register 3 UMISR3 Table 17 29 UMISR3 field descriptions Field Description MS 127 096 0 ...

Page 364: ...ue obtained accumulating MS 135 128 8 ECC bits for the even double word MS138 Single ECC error detection for even double word MS139 Double ECC error detection for even double word MS 151 144 8 ECC bits for the odd double word MS154 Single ECC error detection for odd double word MS155 Double ECC error detection for odd double word The MS can be seeded to any value by writing the UMISR4 register Add...

Page 365: ...D 52 PWD 51 PWD 50 PWD 49 PWD 48 W Reset 1 1 0 0 1 0 1 0 1 1 1 1 1 1 1 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R PWD 47 PWD 46 PWD 45 PWD 44 PWD 43 PWD 42 PWD 41 PWD 40 PWD 39 PWD 38 PWD 37 PWD 36 PWD 35 PWD 34 PWD 33 PWD 32 W Reset 1 0 1 1 1 1 1 0 1 1 1 1 1 1 1 Figure 17 29 Non Volatile Private Censorship Password 1 register NVPWD1 Table 17 32 NVPWD1 field descriptions Field Description...

Page 366: ...f the Censorship Control Word CCW If CW 15 0 0x55AA and NVSCI1 NVSCI0 the Censored mode is disabled If CW 15 0 0x55AA or NVSCI1 NVSCI0 the Censored mode is enabled Address 0x20_3DE4 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R SC 31 SC 30 SC 29 SC 28 SC 27 SC 26 SC 25 SC 24 SC 23 SC 22 SC 21 SC 20 SC 19 SC 18 SC 17 SC 16 W Reset 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 16 17 18 19 20 21 2...

Page 367: ...5 6 7 8 9 10 11 12 13 14 15 R WAT CH DOG _EN UO30 PAD3 V5V UO28 UO27 UO26 UO25 UO24 UO23 UO22 UO21 UO20 UO19 UO18 UO17 UO16 W Reset x x x x x x x x x x x x x x x x 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R UO15 UO14 UO13 UO12 UO11 UO10 UO9 UO8 UO7 UO6 UO5 UO4 UO3 UO2 UO1 UO0 W Reset x x x x x x x x x x x x x x x x Figure 17 32 Non Volatile User Options register NVUSRO Table 17 35 NVUSRO fi...

Page 368: ... modify operation is started through a sequence of three steps 1 The first instruction selects the desired operation by setting its corresponding selection bit in MCR MCR PGM or MCR ERS or UT0 UT0 MRE or UT0 EIE 2 The second step defines the operands the address and the data for programming or the sectors for erase or margin read 3 The third instruction starts the modify operation by setting MCR E...

Page 369: ...peration should completely fill selected ECC segments within the double word Programming changes the value stored in an array bit from logic 1 to logic 0 only Programming cannot change a stored logic 0 to a logic 1 Addresses in locked disabled blocks cannot be programmed The user may program the values in any or all of 2 words of a double word with a single program sequence Double word bound words...

Page 370: ...step 8 of the program sequence A terminated program results in MCR PEG being cleared indicating a failed operation MCR DONE must be checked to know when the terminating command has completed The data space being operated on before the termination will contain indeterminate data This may be recovered by repeating the same program instruction or executing an erase of the affected blocks Example 17 1...

Page 371: ...erminate the erase sequence by clearing MCR ERS before setting MCR EHV An erase operation may be terminated by clearing MCR EHV assuming MCR DONE is low MCR EHV is high and MCR ESUS is low An erase termination forces the Module to step 8 of the erase sequence A terminated erase results in MCR PEG being cleared indicating a failed operation MCR DONE must be checked to know when the terminating comm...

Page 372: ...pend The Erase sequence is resumed by writing a logic 0 to MCR ESUS MCR EHV must be set to 1 before MCR ESUS can be cleared to resume the operation The Module continues the erase sequence from one of a set of predefined points This may extend the time required for the erase operation Example 17 4 Sector Erase Resume MCR 0x00000005 Reset ESUS in MCR Erase Resume 17 3 8 1 3 User Test mode User Test ...

Page 373: ... Check consists of the following sequence of events 1 Set UT0 UTE by writing the related password in UT0 2 Select the block s to be checked by writing 1s to the LMS register Note that Lock and Select are independent If a block is selected and locked no Array Integrity Check will occur 3 Set eventually UT0 AIS bit for a sequential addressing only 4 Write a logic 1 to the UT0 AIE bit to start the Ar...

Page 374: ... reads Repeated Margin reads will result in degradation of the Flash array and will shorten the expected lifetime experienced at normal read levels For these reasons Margin reads are allowed only at the factory Margin reads are forbidden for use by user applications In any case the charge losses detected through the Margin mode cannot be considered failures of the device and no failure analysis wi...

Page 375: ...ent data2 UMISR2 Read UMISR2 content data3 UMISR3 Read UMISR3 content data4 UMISR4 Read UMISR4 content UT0 0x80000034 Reset AIE in UT0 Operation End UT0 0x00000000 Reset UTE MRE MRV AIS in UT0 Deselect Op 17 3 8 1 3 3 ECC logic check ECC logic can be checked by forcing the input of ECC logic The 64 bits of data and the 8 bits of ECC syndrome can be individually forced and they will drive simultane...

Page 376: ...bits Each double word of 64 bits has an associated 8 ECC bits that are programmed in such a way to guarantee a Single Error Correction and a Double Error Detection SEC DED ECC circuitry provides correction of single bit faults and is used to achieve automotive reliability targets Some units will experience single bit corrections throughout the life of the product with no impact on product reliabil...

Page 377: ...e All the non volatile modify protection registers can be programmed through a normal double word program operation at the related locations in TestFlash The non volatile modify protection registers cannot be erased The non volatile modify protection registers are physically located in TestFlash Their bits can be programmed to 0 only once after which they cannot be restored to 1 The volatile modif...

Page 378: ...atile Flash cells located in the Shadow Sector This information is read once during the Flash initialization phase following the exit from Reset and they are stored in Volatile registers that act as actuators The reset state of all the volatile censored mode registers is the protected state All the non volatile censored mode registers can be programmed through a normal double word program operatio...

Page 379: ...p management Censored mode Public access NVSCI0 NVSCI1 Enabled Enabled 0xFFFF_FFFF 0xFFFF_FFFF Disabled Enabled 0xFFFF_55AA 0xFFFF_55AA Enabled Disabled 0x55AA_FFFF 0x55AA_FFFF Disabled Disabled 0x55AA_55AA 0x55AA_55AA Enabled Disabled 0x55AA_0000 0x55AA_0000 Disabled Enabled 0x0000_55AA 0x0000_55AA Enabled Enabled 0x0000_0000 0x0000_0000 ...

Page 380: ...Chapter 17 Flash Memory MPC5602P Microcontroller Reference Manual Rev 4 380 Freescale Semiconductor ...

Page 381: ...oller hardware microarchitecture includes a DMA engine that performs source and destination address calculations and the actual data movement operations along with SRAM based local memory containing the transfer control descriptors TCD for the channels Figure 18 1 is a block diagram of the eDMA module Figure 18 1 eDMA block diagram Slave Interface eDMA eDMA done System Bus Data path Control Addres...

Page 382: ...rt two deep nested transfer operations 32 byte TCD per channel stored in local memory An inner data transfer loop defined by a minor byte transfer count An outer data transfer loop defined by a major iteration count Channel activation via one of three methods Explicit software initiation Initiation via a channel to channel linking mechanism for continual transfers Peripheral paced hardware request...

Page 383: ...n The source and destination can be a memory block or an I O block capable of operation with the eDMA 18 4 2 Debug mode If enabled by EDMA_CR EDBG and the CPU enters debug mode the eDMA does not grant a service request when the debug input signal is asserted If the signal asserts during a data block transfer as described by a minor loop in the current active channel s TCD the eDMA continues the op...

Page 384: ...ge 387 0x0008 Reserved 0x000C EDMA_ERQL eDMA Enable Request Register on page 390 0x0010 Reserved 0x0014 EDMA_EEIRL eDMA Enable Error Interrupt Register on page 391 0x0018 EDMA_SERQR eDMA Set Enable Request Register on page 392 0x0019 EDMA_CERQR eDMA Clear Enable Request Register on page 392 0x001A EDMA_SEEI eDMA Set Enable Error Interrupt Register on page 393 0x001B EDMA_CEEI eDMA Clear Enable Err...

Page 385: ...99 0x0105 EDMA_CPR5 eDMA Channel 5 Priority Register on page 399 0x0106 EDMA_CPR6 eDMA Channel 6 Priority Register on page 399 0x0107 EDMA_CPR7 eDMA Channel 7 Priority Register on page 399 0x0108 EDMA_CPR8 eDMA Channel 8 Priority Register on page 399 0x0109 EDMA_CPR9 eDMA Channel 9 Priority Register on page 399 0x010A EDMA_CPR10 eDMA Channel 10 Priority Register on page 399 0x010B EDMA_CPR11 eDMA ...

Page 386: ... 400 0x10C0 TCD06 Transfer Control Descriptor 6 on page 400 0x10E0 TCD07 Transfer Control Descriptor 7 on page 400 0x1100 TCD08 Transfer Control Descriptor 8 on page 400 0x1120 TCD09 Transfer Control Descriptor 9 on page 400 0x1140 TCD10 Transfer Control Descriptor 10 on page 400 0x1160 TCD11 Transfer Control Descriptor 11 on page 400 0x1180 TCD12 Transfer Control Descriptor 12 on page 400 0x11A0 ...

Page 387: ... are cycled through from channel 15 down to channel 0 without regard to priority Refer to Section 18 5 2 16 eDMA Channel n Priority Registers EDMA_CPRn Address Base 0x0000 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 ERCA EDBG 0 W Res...

Page 388: ...not equal the TCD BITER E_LINK bit All configuration error conditions except scatter gather and minor loop link error are reported as the channel is activated and assert an error interrupt request if enabled When properly enabled a scatter gather configuration error is reported when the scatter gather operation begins at major loop completion A minor loop channel link configuration error is report...

Page 389: ...ll channel priorities within a group are unique 18 23 ERRCHN 0 5 Error channel number Channel number of the last recorded error excluding GPE and CPE errors Note Do not rely on the number in the ERRCHN field for group and channel priority errors Group and channel priority errors need to be resolved by inspection The application code must interrogate the priority registers to find groups or channel...

Page 390: ...tected in the TCD NBYTES or TCD CITER fields indicating the following conditions exist TCD NBYTES is not a multiple of TCD SSIZE and TCD DSIZE or TCD CITER is equal to zero or TCD CITER E_LINK is not equal to TCD BITER E_LINK 29 SGE Scatter gather configuration error 0 No scatter gather configuration error 1 The last recorded error was a configuration error detected in the TCD DLAST_SGA field indi...

Page 391: ...t the error interrupt enable for a single channel can easily be modified without the need to perform a read modify write sequence to the EDMA_EEIRL Both the DMA error indicator and this error interrupt enable flag must be asserted before an error interrupt request for a given channel is asserted Table 18 4 EDMA_ERQRL field descriptions Field Description 16 31 ERQn Enable DMA hardware service reque...

Page 392: ...e EDMA_ERQRL to disable the DMA request for a given channel The data value on a register write causes the corresponding bit in the EDMA_ERQRL to be cleared Setting bit 1 CERQn provides a global clear function forcing the entire contents of the EDMA_ERQRL to be zeroed disabling all DMA request inputs Reads of this register return all zeroes Address Base 0x0018 Access User write only 0 1 2 3 4 5 6 7...

Page 393: ...interrupt for a given channel The data value on a register write causes the corresponding bit in the EDMA_EEIRL to be cleared Setting bit 1 CEEIn provides a global clear function forcing the entire contents of the EDMA_EEIRL to be zeroed disabling error interrupts for all channels Reads of this register return all zeroes Table 18 7 EDMA_CERQR field descriptions Field Description 0 Reserved 1 7 CER...

Page 394: ... zeroes Address Base 0x001B Access User write only 0 1 2 3 4 5 6 7 R 0 0 0 0 0 0 0 0 W CEEI 0 6 Reset 0 0 0 0 0 0 0 0 Figure 18 9 eDMA Set Enable Error Interrupt Register EDMA_SEEIR Table 18 9 EDMA_CEEIR field descriptions Field Description 0 Reserved 1 7 CEEI 0 6 Clear enable error interrupt 0 15 Clear corresponding bit in EDMA_EEIRL 16 63 Reserved 64 127 Clear all bits in EDMA_EEIRL Note Bit 2 C...

Page 395: ...a register write causes the START bit in the corresponding transfer control descriptor to be set Setting bit 1 SSBn provides a global set function forcing all START bits to be set Reads of this register return all zeroes Address Base 0x001D Access User write only 0 1 2 3 4 5 6 7 R 0 0 0 0 0 0 0 0 W CERR 0 6 Reset 0 0 0 0 0 0 0 0 Figure 18 11 eDMA Clear Error Register EDMA_CERR Table 18 11 EDMA_CER...

Page 396: ...g the execution of the interrupt service routine associated with any given channel it is software s responsibility to clear the appropriate bit negating the interrupt request Typically a write to the EDMA_CIRQR in the interrupt service routine is used for this purpose The state of any given channel s interrupt request is directly affected by writes to this register it is also affected by writes to...

Page 397: ...ected The contents of this register can also be polled and a non zero value indicates the presence of a channel error regardless of the state of the EDMA_EEIR The EDMA_ESR VLD bit is a logical OR of all bits in this register and it provides a single bit indication of any errors The state of any given channel s error indicators is affected by writes to this register it is also affected by writes to...

Page 398: ... ERR 02 ERR 01 ERR 00 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 18 15 eDMA Error Low Register EDMA_ERL Table 18 15 EDMA_ERL field descriptions Field Description 16 31 ERRn eDMA Error n 0 An error in channel n has not occurred 1 An error in channel n has occurred Address Base 0x0034 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0...

Page 399: ...pting channel has completed all of its minor loop data transfers the preempted channel is restored and resumes execution After the restored channel completes one read write sequence it is again eligible for preemption If any higher priority channel is requesting service the restored channel is suspended and the higher priority channel is serviced Nested preemption attempting to preempt a preemptin...

Page 400: ...rce address SADDR Word 0 0x1000 32 n 32 5 Source address modulo SMOD Word 1 0x1000 32 n 37 3 Source data transfer size SSIZE 0x1000 32 n 40 5 Destination address modulo DMOD 0x1000 32 n 45 3 Destination data transfer size DSIZE 0x1000 32 n 48 16 Signed Source Address Offset SOFF 0x1000 32 n 64 32 Inner minor byte count NBYTES Word 2 0x1000 32 n 96 32 Last Source Address Adjustment SLAST Word 3 0x1...

Page 401: ...x1000 32 n 242 6 Link Channel Number MAJOR LINKCH 0x1000 32 n 248 1 Channel Done DONE 0x1000 32 n 249 1 Channel Active ACTIVE 0x1000 32 n 250 1 Channel to channel Linking on Major Loop Complete MAJOR E_LINK 0x1000 32 n 251 1 Enable Scatter Gather Processing E_SG 0x1000 32 n 252 1 Disable Request D_REQ 0x1000 32 n 253 1 Channel Interrupt Enable When Current Major Iteration Count is Half Complete IN...

Page 402: ...F 0x8 NBYTES 0xC SLAST 0x10 DADDR 0x14 CITER E_ LINK CITER 1 or CITER LINKCH 1 If channel linking on minor link completion is disabled TCD bits 161 175 form a 15 bit CITER field if channel to channel linking is enabled CITER becomes a 9 bit field CITER 1 DOFF 0x18 DLAST_SGA 0x1C BITER E_ LINK BITER 2 or BITER LINKCH 2 If channel linking on minor link completion is disabled TCD bits 225 239 form a ...

Page 403: ...5 DSIZE 0 2 Destination data transfer size Refer to the SSIZE 0 2 definition 48 63 0x4 16 31 SOFF 0 15 Source address signed offset Sign extended offset applied to the current source address to form the next state value as each source read is completed 64 95 0x8 0 31 NBYTES 0 31 Inner minor byte transfer count Number of bytes to be transferred in each service request of the channel As a channel is...

Page 404: ...or loop is completed and updated in the transfer control descriptor memory After the major iteration count is exhausted the channel performs a number of operations for example final source and destination address calculations optionally generating an interrupt to signal channel completion before reloading the CITER field from the beginning iteration count BITER field Note When the CITER field is i...

Page 405: ...annel service request at the channel defined by BITER LINKCH 0 5 by setting that channel s TCD START bit Note When the TCD is first loaded by software this field must be set equal to the corresponding CITER field otherwise a configuration error is reported As the major iteration count is exhausted the contents of this field is reloaded into the CITER field 231 239 0x1C 7 15 BITER 6 14 Beginning or...

Page 406: ... to another channel defined by MAJOR LINKCH 0 5 The link target channel initiates a channel service request via an internal mechanism that sets the TCD START bit of the specified channel NOTE To support the dynamic linking coherency model this field is forced to zero when written to while the TCD DONE bit is set 0 The channel to channel linking is disabled 1 The channel to channel linking is enabl...

Page 407: ...r is read from the local memory and loaded into the registers of the other address path channel x y After the inner minor loop completes execution the address path hardware writes the new values for 253 0x1C 29 INT_HALF Enable an interrupt when major counter is half complete If this flag is set the channel generates an interrupt request by setting the bit in the EDMA_ERQL when the current major it...

Page 408: ...ol logic Control This module provides all the control functions for the eDMA engine For data transfers where the source and destination sizes are equal the eDMA engine performs a series of source read destination write operations until the number of bytes specified in the inner minor loop byte count has been moved A minor loop interaction is defined as the number of bytes to transfer nbytes divide...

Page 409: ...ired address to access the TCD local memory Next the TCD memory is accessed and the required descriptor read from the local memory and loaded into the eDMA engine address path channel x y registers The TCD memory is organized 64 bits in width to minimize the time needed to fetch the activated channel s descriptor and load it into the eDMA engine address path channel x y registers Figure 18 19 eDMA...

Page 410: ...uter major iteration count is exhausted then additional operations are performed These include the final address adjustments and reloading of the BITER field into the CITER Additionally assertion of an optional interrupt request occurs at this time as does a possible fetch of a new TCD from memory using the scatter gather address pointer included in the descriptor The updates to the TCD memory and...

Page 411: ...this environment the speed of the source and destination address spaces remains important but the microarchitecture of the eDMA also factors significantly into the resulting metric The peak transfer rates for several different source and destination transfers are shown in Table 18 20 The following assumptions apply to Table 18 20 and Table 18 21 Internal SRAM can be accessed with zero wait states ...

Page 412: ...cally in the eDMA module and qualified TCD START bit initiated requests start at this point with the registering of the slave write to TCD bit 255 Cycle 3 Channel arbitration begins Cycle 4 Channel arbitration completes The transfer control descriptor local memory read is initiated Cycle 5 6 The first two parts of the activated channel s TCD is read from the local memory The memory width to the eD...

Page 413: ...nd processed if enabled Cycle n 3 The appropriate fields in the first part of the TCDn are written back into the local memory Cycle n 4 The fields in the second part of the TCDn are written back into the local memory This cycle coincides with the next channel arbitration cycle start Cycle n 5 The next channel to be activated performs the read of the first part of its TCD from the local memory This...

Page 414: ...es on the system bus from a cold start no channel is executing eDMA is idle are the following 11 cycles for a software TCD START bit request 12 cycles for a hardware eDMA peripheral request signal request Two cycles account for the arbitration pipeline and one extra cycle on the hardware request resulting from the internal registering of the eDMA peripheral request signals For the peak request rat...

Page 415: ...TCD DADDR and TCD CITER are written back to the main TCD memory and any minor loop channel linking is performed if enabled If the major loop is exhausted further post processing is executed for example interrupts major loop channel linking and scatter gather operations if enabled Figure 18 22 shows how each DMA request initiates one minor loop transfer iteration without CPU intervention DMA arbitr...

Page 416: ...channel number causing the error is recorded in the EDMA_ESR If the error source is not removed before the next activation of the problem channel the error is detected and recorded again DMA Request Minor Loop 3 Current Major Loop Iteration Count CITER Example Memory Array DMA Request Minor Loop 2 DMA Request Minor Loop 1 Major Loop xADDR Starting Address xSIZE Size of one data Minor Loop NBYTES i...

Page 417: ...ixed group arbitration round robin channel arbitration Channels are serviced starting with the highest channel number and rotating through to the lowest channel number without regard to the channel priority levels assigned within the group Table 18 23 DMA request summary for eDMA DMA Request Ch Source Description DMA_MUX_CHCONFIG0_SOURCE 0 DMA_MUX CHCONFIG0 SOURCE DMA MUX channel 0 source DMA_MUX_...

Page 418: ... four bytes for the destination The final source and destination addresses are adjusted to return to their beginning values TCD CITER TCD BITER 1 TCD NBYTES 16 TCD SADDR 0x1000 TCD SOFF 1 TCD SSIZE 0 TCD SLAST 16 TCD DADDR 0x2000 TCD DOFF 4 TCD DSIZE 2 TCD DLAST_SGA 16 TCD INT_MAJ 1 TCD START 1 Initialize all other fields before writing to this bit All other TCD fields 0 This generates the followi...

Page 419: ...channel s hardware requests are enabled in the EDMA_ERQR channel service requests are initiated by the slave device set ERQR after TCD TCD START 0 TCD CITER TCD BITER 2 TCD NBYTES 16 TCD SADDR 0x1000 TCD SOFF 1 TCD SSIZE 0 TCD SLAST 32 TCD DADDR 0x2000 TCD DOFF 4 TCD DSIZE 2 TCD DLAST_SGA 32 TCD INT_MAJ 1 TCD START 0 Initialize all other fields before writing this bit All other TCD fields 0 This g...

Page 420: ...te 0x1018 read_byte 0x1019 read_byte 0x101a read_byte 0x101b f write_word 0x2018 third iteration of the minor loop g read_byte 0x101c read_byte 0x101d read_byte 0x101e read_byte 0x101f h write_word 0x201c last iteration of the minor loop major loop complete 14 eDMA engine writes TCD SADDR 0x1000 TCD DADDR 0x2000 TCD CITER 2 TCD BITER 15 eDMA engine writes TCD ACTIVE 0 TCD DONE 1 EDMA_IRQRn 1 16 Th...

Page 421: ...E 0 executing 3 TCD START 0 TCD ACTIVE 0 TCD DONE 0 completed minor loop and is idle or 4 TCD START 0 TCD ACTIVE 0 TCD DONE 1 completed major loop and is idle The best method to test for minor loop completion when using hardware initiated service requests is to read the TCD CITER field and test for a change The hardware request and acknowledge handshakes signals are not visible in the programmer s...

Page 422: ...CD ACTIVE bit for the preempted channel remains asserted throughout the preemption The preempted channel is temporarily suspended while the preempting channel executes one iteration of the major loop Two TCD ACTIVE bits set at the same time in the overall TCD map indicates a higher priority channel is actively preempting a lower priority channel 18 7 7 Channel linking Channel linking or chaining i...

Page 423: ...linking and dynamic scatter gather is the process of changing the TCD MAJOR E_LINK or TCD E_SG bits during channel execution These bits are read from the TCD local memory at the end of channel execution thus allowing the user to enable either feature during channel execution Because the user is allowed to change the configuration during execution a coherency model is needed Consider the scenario w...

Page 424: ...efore the dynamic link completed This same coherency model is true for dynamic scatter gather operations For both dynamic requests the TCD local memory controller forces the TCD MAJOR E_LINK and TCD E_SG bits to zero on any writes to a channel s TCD after that channel s TCD DONE bit is set indicating the major loop is complete NOTE The user must clear the TCD DONE bit before writing the TCD MAJOR ...

Page 425: ...rces slots to a configurable amount of DMA channels This is illustrated in Figure 19 1 Figure 19 1 DMA Mux block diagram 19 1 2 Features The DMA Mux has these major features 16 independently selectable DMA channel routers 4 channels with normal or periodic triggering capability 12 channels with normal capability Source 1 Source 2 Source 3 Source 21 DMA Channel 1 DMA Channel 15 DMA Channel 0 DMA_CH...

Page 426: ...letely transparent to the system Periodic Trigger Mode In this mode a DMA source may only request a DMA transfer such as when a transmit buffer becomes empty or a receive buffer becomes full periodically Configuration of the period is done in the registers of the Periodic Interrupt Timer PIT DMA channels 0 3 may be used in all the modes listed above but channels 4 15 may be configured only to disa...

Page 427: ...ge 428 0x000F Channel 15 Configuration CHCONFIG15 on page 428 0x0010 Channel 16 Configuration CHCONFIG16 on page 428 0x0011 Channel 17 Configuration CHCONFIG17 on page 428 0x0012 Channel 18 Configuration CHCONFIG18 on page 428 0x0013 Channel 19 Configuration CHCONFIG19 on page 428 0x0014 Channel 20 Configuration CHCONFIG20 on page 428 0x0015 Channel 21 Configuration CHCONFIG21 on page 428 0x0016 C...

Page 428: ...s CHCONFIG n Table 19 2 CHCONFIG x field descriptions Field Description 7 ENBL DMA Channel Enable ENBL enables the DMA Channel 0 DMA channel is disabled This mode is primarily used during configuration of the DMA Mux The DMA has separate channel enables disables that should be used to disable or reconfigure a DMA channel 1 DMA channel is enabled 6 TRIG DMA Channel Trigger Enable for triggered chan...

Page 429: ... DSPI_1 RX DMA MUX Source 4 5 DSPI_2 DSPI_2 TX DMA MUX Source 5 6 DSPI_2 DSPI_2 RX DMA MUX Source 6 7 Not connected DMA MUX Source 7 8 Not connected DMA MUX Source 8 9 CTU_0 CTU DMA MUX Source 9 10 CTU_0 CTU FIFO 1 DMA MUX Source 10 11 CTU_0 CTU FIFO 2 DMA MUX Source 11 12 CTU_0 CTU FIFO 3 DMA MUX Source 12 13 CTU_0 CTU FIFO 4 DMA MUX Source 13 14 flexpwm_0 FlexPWM WR DMA MUX Source 14 15 Not conn...

Page 430: ...lity Besides the normal routing functionality the first four channels of the DMA Mux provide a special periodic triggering capability that can be used to provide an automatic mechanism to transmit bytes frames or packets at fixed intervals without the need for processor intervention The trigger is generated by the Periodic Interrupt Timer PIT as such the configuration of the periodic triggering in...

Page 431: ...ger event has been seen This is illustrated in Figure 19 4 Figure 19 4 DMA mux channel triggering normal operation Once the DMA request has been serviced the peripheral will negate its request effectively resetting the gating mechanism until the peripheral re asserts its request AND the next trigger event is seen This means that if a trigger is seen but the peripheral is not requesting a transfer ...

Page 432: ...ery 5 µs as an example On the receive side of the SPI the SPI and DMA can be configured to transfer receive data into memory effectively implementing a method to periodically read data from external devices and transfer the results into memory without processor intervention Using the GPIO Ports to drive or sample waveforms By configuring the DMA to transfer data to one or more GPIO ports it is pos...

Page 433: ... The reset state of each individual bit is shown within the register description section see Section 19 3 2 Register descriptions In summary after reset all channels are disabled and must be explicitly enabled before use 19 6 2 Enabling and configuring sources Enabling a source with periodic triggering 1 Determine with which DMA channel the source will be associated Remember that only the first fo...

Page 434: ...unsigned char DMAMUX_BASE_ADDR 0x0004 volatile unsigned char CHCONFIG5 volatile unsigned char DMAMUX_BASE_ADDR 0x0005 volatile unsigned char CHCONFIG6 volatile unsigned char DMAMUX_BASE_ADDR 0x0006 volatile unsigned char CHCONFIG7 volatile unsigned char DMAMUX_BASE_ADDR 0x0007 volatile unsigned char CHCONFIG8 volatile unsigned char DMAMUX_BASE_ADDR 0x0008 volatile unsigned char CHCONFIG9 volatile ...

Page 435: ... CHCONFIG9 volatile unsigned char DMAMUX_BASE_ADDR 0x0009 volatile unsigned char CHCONFIG10 volatile unsigned char DMAMUX_BASE_ADDR 0x000A volatile unsigned char CHCONFIG11 volatile unsigned char DMAMUX_BASE_ADDR 0x000B volatile unsigned char CHCONFIG12 volatile unsigned char DMAMUX_BASE_ADDR 0x000C volatile unsigned char CHCONFIG13 volatile unsigned char DMAMUX_BASE_ADDR 0x000D volatile unsigned ...

Page 436: ...HCONFIG4 volatile unsigned char DMAMUX_BASE_ADDR 0x0004 volatile unsigned char CHCONFIG5 volatile unsigned char DMAMUX_BASE_ADDR 0x0005 volatile unsigned char CHCONFIG6 volatile unsigned char DMAMUX_BASE_ADDR 0x0006 volatile unsigned char CHCONFIG7 volatile unsigned char DMAMUX_BASE_ADDR 0x0007 volatile unsigned char CHCONFIG8 volatile unsigned char DMAMUX_BASE_ADDR 0x0008 volatile unsigned char C...

Page 437: ...pheral device The MPC5602P implements the modules DSPI0 1 and 2 The x appended to signal names signifies the module to which the signal applies Thus CS0_x specifies that the CS0 signal applies to DSPI module 0 1 etc 20 2 Block diagram A block diagram of the DSPI is shown in Figure 20 1 Figure 20 1 DSPI block diagram CMD DMA and interrupt control TX FIFO RX FIFO TX data RX data 16 16 Shift register...

Page 438: ... internal SRAM Figure 20 2 DSPI with queues and eDMA 20 4 Features The DSPI supports these SPI features Full duplex three wire synchronous transfers Master and slave modes Buffered transmit and receive operation using the TX and RX FIFOs with depths of 5 entries Visibility into TX and RX FIFOs for ease of debugging FIFO bypass mode for low latency updates to SPI queues Programmable transfer attrib...

Page 439: ... s Modified SPI Transfer Format 16 Mbit s 20 5 Modes of operation The DSPI has four modes of operation These modes can be divided into two categories module specific modes such as master slave and module disable modes and a second category that is an MCU specific mode debug mode All four modes are implemented on this device The module specific modes are entered by host software writing to a regist...

Page 440: ...ugging If the device enters debug mode while the FRZ bit in the DSPIx_MCR is set the DSPI halts operation on the next frame boundary If the device enters debug mode while the FRZ bit is cleared the DSPI behavior is unaffected For more information refer to Section 20 8 1 4 Debug mode 20 6 External signal description 20 6 1 Signal overview Table 20 1 lists off chip DSPI signals Table 20 1 Signal pro...

Page 441: ...PI slave mode as a slave select input set the IBE bit Refer to Section 11 5 2 8 Pad Configuration Registers PCR 0 71 for more information 20 6 2 2 Peripheral Chip Selects 1 3 CS1 3 CS1 3 are peripheral chip select output signals in master mode In slave mode these signals are not used On DSPI_0 these are CS1 3 and CS5 6 20 6 2 3 Peripheral Chip Select 4 CS4 CS4 is a peripheral chip select output si...

Page 442: ...egister 0 on page 447 0x0010 DSPI_CTAR1 DSPI clock and transfer attributes register 1 on page 447 0x0014 DSPI_CTAR2 DSPI clock and transfer attributes register 2 on page 447 0x0018 DSPI_CTAR3 DSPI clock and transfer attributes register 3 on page 447 0x001C DSPI_CTAR4 DSPI clock and transfer attributes register 4 on page 447 0x0020 DSPI_CTAR5 DSPI clock and transfer attributes register 5 on page 44...

Page 443: ...Reserved 0x007C DSPI_RXFR0 DSPI receive FIFO register 0 on page 459 0x0080 DSPI_RXFR1 DSPI receive FIFO register 1 on page 459 0x0084 DSPI_RXFR2 DSPI receive FIFO register 2 on page 459 0x0088 DSPI_RXFR3 DSPI receive FIFO register 3 on page 459 0x008C DSPI_RXFR4 DSPI receive FIFO register 4 on page 459 0x0090 0x3FFF Reserved Address Base 0x0000 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 1...

Page 444: ...ng format enable Enables a modified transfer format to be used Refer to Section 20 8 5 4 Modified SPI transfer format MTFE 1 CPHA 1 for more information 0 Modified SPI transfer format disabled 1 Modified SPI transfer format enabled 6 PCSSE Peripheral chip select strobe enable Enables the CS5_x to operate as a CS strobe output signal Refer to Section 20 8 4 5 Peripheral Chip Select strobe enable CS...

Page 445: ...I clocks 18 DIS_TXF Disable transmit FIFO Enables and disables the TX FIFO When the TX FIFO is disabled the transmit part of the DSPI operates as a simplified double buffered SPI Refer to Section 20 8 3 3 FIFO disable operation for details 0 TX FIFO enabled 1 TX FIFO disabled 19 DIS_RXF Disable receive FIFO Enables and disables the RX FIFO When the RX FIFO is disabled the receive part of the DSPI ...

Page 446: ...following table lists the delayed sample points 24 30 Reserved 31 HALT Halt Provides a mechanism for software to start and stop DSPI transfers Refer to Section 20 8 2 Start and stop of DSPI transfers for details on the operation of this bit 0 Start transfers 1 Stop transfers Address Base 0x0008 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R SPI_TCNT 0 15 W Reset 0 0 0 0 0 0 0 0 0 0...

Page 447: ...e and polarity data bit ordering baud rate and various delays In slave mode a subset of the bit fields in the DSPIx_CTAR0 and DSPIx_CTAR1 registers sets the slave transfer attributes Refer to the individual bit descriptions for details on which bits are used in slave modes When the DSPI is configured as an SPI master the CTAS field in the command portion of the TX FIFO entry selects which of the D...

Page 448: ... divide by three of the system clock then neither the Continuous SCK Enable or the Modified Timing Format Enable bits should be set 0 The baud rate is computed normally with a 50 50 duty cycle 1 The baud rate is doubled with the duty cycle depending on the baud rate prescaler 1 4 FMSZ 0 3 Frame Size The FMSZ field selects the number of bits transferred per frame The FMSZ field is used in Master Mo...

Page 449: ...ld selects the prescaler value for the delay between the last edge of SCK and the negation of PCS This field is only used in Master Mode The table lists the prescaler values See the ASC 0 3 field description for details on how to compute the After SCK delay 12 13 PDT 0 1 Delay after Transfer Prescaler The PDT field selects the prescaler value for the delay between the negation of the PCS signal at...

Page 450: ... 0 3 After SCK Delay Scaler The ASC field selects the scaler value for the After SCK delay This field is only used in Master Mode The After SCK delay is the delay between the last edge of SCK and the negation of PCS Table 20 9 lists the scaler values The After SCK delay is a multiple of the system clock period and it is computed according to the following equation Eqn 20 2 See Section 20 8 4 3 Aft...

Page 451: ... rate is computed according to the following equation Eqn 20 4 See Section 20 8 4 1 Baud rate generator for more details Table 20 6 DSPI SCK duty cycle DBR CPHA PBR SCK duty cycle 0 any any 50 50 1 0 00 50 50 1 0 01 33 66 1 0 10 40 60 1 0 11 43 57 1 1 00 50 50 1 1 01 66 33 1 1 10 60 40 1 1 11 57 43 Table 20 7 DSPI transfer frame size FMSZ Frame size FMSZ Frame size 0000 Reserved 1000 9 0001 Reserv...

Page 452: ...0 128 1110 32768 0111 256 1111 65536 Table 20 9 DSPI after SCK delay scaler ASC After SCK delay scaler value ASC After SCK delay scaler value 0000 2 1000 512 0001 4 1001 1024 0010 8 1010 2048 0011 16 1011 4096 0100 32 1100 8192 0101 64 1101 16384 0110 128 1110 32768 0111 256 1111 65536 Table 20 10 DSPI delay after transfer scaler DT Delay after transfer scaler value DT Delay after transfer scaler ...

Page 453: ...14 15 R TCF TXRXS 0 EOQF TFUF 0 TFFF 0 0 0 0 0 RFOF 0 RFDF 0 W w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R TXCTR TXNXTPTR RXCTR POPNXTPTR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 20 6 DSPI Status Register DSPIx_SR Table 20 12 DSPIx_SR field descriptions Field Description 0 TCF Transfer complete flag Indicates that all bits i...

Page 454: ...an be filled Provides a method for the DSPI to request more entries to be added to the TX FIFO The TFFF bit is set while the TX FIFO is not full The TFFF bit can be cleared by writing 1 to it or an by acknowledgement from the eDMA controller when the TX FIFO is full 0 TX FIFO is full 1 TX FIFO is not full 7 11 Reserved 12 RFOF Receive FIFO overflow flag Indicates that an overflow condition in the ...

Page 455: ...Section 20 8 5 1 Classic SPI transfer format CPHA 0 for details 28 31 POPNXTPTR 0 3 Pop next pointer Contains a pointer to the RX FIFO entry that is returned when the DSPIx_POPR is read The POPNXTPTR is updated when the DSPIx_POPR is read Refer to Section 20 8 3 5 Receive First In First Out RX FIFO buffering mechanism for more details Address Base 0x0030 Access User read write 0 1 2 3 4 5 6 7 8 9 ...

Page 456: ... or interrupt request select Selects between generating a DMA request or an interrupt request When the TFFF flag bit in the DSPIx_SR is set and the TFFF_RE bit in the DSPIx_RSER is set this bit selects between generating an interrupt request or a DMA request 0 Interrupt request is selected 1 DMA request is selected 8 11 Reserved 12 RFOF_RE Receive FIFO overflow request enable Enables the RFOF flag...

Page 457: ...ore information 0 Return peripheral chip select signals to their inactive state between transfers 1 Keep peripheral chip select signals asserted between transfers 1 3 CTAS 0 2 Clock and transfer attributes select Selects which of the DSPIx_CTARs sets the transfer attributes for the SPI frame In SPI slave mode DSPIx_CTAR0 is used The following table shows how the CTAS values map to the DSPIx_CTARs ...

Page 458: ... to clear the SPI transfer counter The CTCNT bit clears the SPI_TCNT field in the DSPIx_TCR The SPI_TCNT field is cleared before transmission of the current SPI frame begins 0 Do not clear SPI_TCNT field in the DSPIx_TCR 1 Clear SPI_TCNT field in the DSPIx_TCR Note Use in SPI master mode only 6 7 Reserved 10 15 PCSx Peripheral chip select x Selects which CSx signals are asserted for the transfer 0...

Page 459: ...five registers to implement the RX FIFO that is DSPIx_RXFR0 DSPIx_RXFR4 are used Table 20 15 DSPIx_POPR field descriptions Field Description 0 15 Reserved must be cleared 16 31 RXDATA 0 15 Received data The RXDATA field contains the SPI data from the RX FIFO entry pointed to by the pop next data pointer POPNXTPTR Address Base 0x003C DSPIx_TXFR0 Base 0x0040 DSPIx_TXFR1 Base 0x0044 DSPIx_TXFR2 Base ...

Page 460: ...nd SIN_x signals to form a distributed 32 bit register When a data transfer operation is performed data is serially shifted a pre determined number of bit positions Because the registers are linked data is exchanged between the master and the slave the data that was in the master s shift register is now in the shift register of the slave and vice versa At the end of a transfer the TCF bit in the D...

Page 461: ...le specific modes while debug mode is a device specific mode All four modes are implemented on this device The module specific modes are determined by bits in the DSPIx_MCR Debug mode is a mode that the entire device can enter in parallel with the DSPI being configured in one of its module specific modes 20 8 1 1 Master mode In master mode the DSPI can initiate communications with peripheral devic...

Page 462: ...ging If the MCU enters debug mode while the FRZ bit in the DSPIx_MCR is set the DSPI stops all serial transfers and enters a stopped state If the MCU enters debug mode while the FRZ bit is cleared the DSPI behavior is unaffected and remains dictated by the module specific mode and configuration of the DSPI The DSPI enters debug mode when a debug request is asserted by an external controller Refer ...

Page 463: ...odes master mode and slave mode The FIFO operations are similar for the master mode and slave mode The main difference is that in master mode the DSPI initiates and controls the transfer according to the fields in the SPI command field of the TX FIFO entry In slave mode the DSPI only responds to transfers initiated by a bus master external to the DSPI and the SPI command field of the TX FIFO entry...

Page 464: ...SPIx_TXFRs and TXNXTPTR are undefined When the RX FIFO is disabled the RFDF RFOF and RXCTR fields in the DSPIx_SR behave as if there is a one entry FIFO but the contents of the DSPIx_RXFRs and POPNXTPTR are undefined Disable the TX and RX FIFOs only if the FIFO must be disabled as a requirement of the application s operating mode A FIFO must be disabled before it is accessed Failure to disable a F...

Page 465: ...he TX FIFO is flushed by writing a 1 to the CLR_TXF bit in DSPIx_MCR If an external SPI bus master initiates a transfer with a DSPI slave while the slave s DSPI TX FIFO is empty the transmit FIFO underflow flag TFUF in the slave s DSPIx_SR is set Refer to Section 20 8 7 4 Transmit FIFO underflow interrupt request TFUF for details 20 8 3 5 Receive First In First Out RX FIFO buffering mechanism The ...

Page 466: ...ains unchanged The data returned from reading an empty RX FIFO is undetermined Refer to Section 20 7 2 7 DSPI POP RX FIFO Register DSPIx_POPR for more information on DSPIx_POPR When the RX FIFO is not empty the RX FIFO drain flag RFDF in the DSPIx_SR is set The RFDF bit is cleared when the RX_FIFO is empty and the eDMA controller indicates that a read from DSPIx_POPR is complete alternatively the ...

Page 467: ... time between the last edge of SCK_x and the deassertion of CS_x Refer to Figure 20 16 and Figure 20 17 for illustrations of the after SCK_x delay The PASC and ASC fields in the DSPIx_CTARn registers select the after SCK delay The relationship between these variables is given in the following formula Eqn 20 7 Table 20 21 shows an example of the computed after SCK delay Table 20 19 Baud rate comput...

Page 468: ...nals to settle after transitioning thereby avoiding glitches When the DSPI is in master mode and PCSSE bit is set in the DSPIx_MCR CS5_x provides a signal for an external demultiplexer to decode the CS4_x signals into as many as 32 glitch free CSx signals Figure 20 15 shows the timing of the CS5_x signal relative to CS signals Figure 20 15 Peripheral Chip Select strobe timing The delay between the...

Page 469: ... the SCK signal clock polarity clock phase and number of bits to transfer must be identical for the master device and the slave device to ensure proper transmission The DSPI supports four different transfer formats Classic SPI with CPHA 0 Classic SPI with CPHA 1 Modified transfer format with CPHA 0 Modified transfer format with CPHA 1 A modified transfer format is supported to allow for high speed...

Page 470: ...e second edge of the SCK_x the master and slave devices place their second data bit on their serial data output signals For the rest of the frame the master and the slave sample their SIN_x pins on the odd numbered clock edges and changes the data on their SOUT_x pins on the even numbered clock edges After the last clock edge occurs a delay of tASC is inserted before the master negates the CS sign...

Page 471: ...CK_x the master and slave sample their SIN_x pins For the rest of the frame the master and the slave change the data on their SOUT_x pins on the odd numbered clock edges and sample their SIN_x pins on the even numbered clock edges After the last clock edge occurs a delay of tASC is inserted before the master negates the CSx signal A delay of tDT is inserted before a new frame transfer can be initi...

Page 472: ... The slave samples the master SOUT_x signal on every odd numbered SCK_x edge The slave also places new data on the slave SOUT_x on every odd numbered clock edge The master places its second data bit on the SOUT_x line one system clock after odd numbered SCK_x edge The point where the master samples the slave SOUT_x is selected by writing to the SMPL_PT field in the DSPIx_MCR Table 20 25 lists the ...

Page 473: ...al on the odd numbered SCK edges starting with the 3rd SCK edge The slave samples the last bit on the last edge of the SCK The master samples the last slave SOUT bit one half SCK cycle after the last edge of SCK No clock edge is visible on the master SCK pin during the sampling of the last bit The SCK to CS delay must be programmed to be greater than or equal to half the SCK period NOTE For the mo...

Page 474: ...the SPI configuration by setting the CONT bit in the SPI command When the CONT bit 0 the DSPI drives the asserted chip select signals to their idle states in between frames The idle states of the chip select signals are selected by the PCSIS field in the DSPIx_MCR Figure 20 20 shows the timing diagram for two 4 bit transfers with CPHA 1 and CONT 0 Figure 20 20 Example of non continuous format CPHA...

Page 475: ...e different from the present transfer the CS signals behave as if the CONT bit was not set NOTE It is mandatory to fill the TXFIFO with the number of entries that will be concatenated together under one PCS assertion for both master and slave before the TXFIFO becomes empty For example while transmitting in master mode it should be ensured that the last entry in the TXFIFO after which TXFIFO becom...

Page 476: ...SPI is in SPI configuration CTAR0 is used initially At the start of each SPI frame transfer the CTAR specified by the CTAS for the frame is used In all configurations the currently selected CTAR remains in use until the start of a frame with a different CTAR specified or the continuous SCK mode is terminated The device is designed to use the same baud rate for all transfers made while using the co...

Page 477: ...entry is set CS remains asserted between the transfers when the CS signal for the next transfer is the same as for the current transfer Figure 20 24 shows timing diagram for continuous SCK format with continuous selection enabled Figure 20 24 Continuous SCK timing diagram CONT 1 SCK CPOL 0 CS SCK CPOL 1 Master SOUT tDT tDT 1 SCK Master SIN SCK CPOL 0 CS SCK CPOL 1 Master SOUT Master SIN Transfer 1...

Page 478: ...o Figure 20 16 and Figure 20 17 that illustrate when EOQF is set 20 8 7 2 Transmit FIFO fill interrupt or DMA request TFFF The transmit FIFO fill request indicates that the TX FIFO is not full The transmit FIFO fill request is generated when the number of entries in the TX FIFO is less than the maximum number of possible entries and the TFFF_RE bit in the DSPIx_RSER is set The TFFF_DIRS bit in the...

Page 479: ...ing on the state of the ROOE bit in the DSPIx_MCR the data from the transfer that generated the overflow is either ignored or shifted in to the shift register If the ROOE bit is set the incoming data is shifted in to the shift register If the ROOE bit is negated the incoming data is ignored 20 8 7 7 FIFO overrun request TFUF or RFOF The FIFO overrun request indicates that at least one of the FIFOs...

Page 480: ...DMA continues to fill TX FIFO until it is full or step 5 occurs 5 Disable DSPI DMA transfers by disabling the DMA enable request for the DMA channel assigned to TX FIFO and RX FIFO This is done by clearing the corresponding DMA enable request bits in the eDMA controller 6 Ensure all received data in RX FIFO has been transferred to memory receive queue by reading the RXCNT in DSPIx_SR or by checkin...

Page 481: ... MHz 5 56 MHz 3 33 MHz 2 38 MHz 8 6 25 MHz 4 17 MHz 2 50 MHz 1 79 MHz 16 3 12 MHz 2 08 MHz 1 25 MHz 893 kHz 32 1 56 MHz 1 04 MHz 625 kHz 446 kHz 64 781 kHz 521 kHz 312 kHz 223 kHz 128 391 kHz 260 kHz 156 kHz 112 kHz 256 195 kHz 130 kHz 78 1 kHz 55 8 kHz 512 97 7 kHz 65 1 kHz 39 1 kHz 27 9 kHz 1024 48 8 kHz 32 6 kHz 19 5 kHz 14 0 kHz 2048 24 4 kHz 16 3 kHz 9 77 kHz 6 98 kHz 4096 12 2 kHz 8 14 kHz 4...

Page 482: ...figure the DSPIx_CTARs to match the default cases for the possible combinations of the MPC500 family control bits in its command RAM The defaults for the QSPI are based on a system clock of 40 MHz Table 20 28 Delay values Delay prescaler values DSPI_CTAR PBR 1 3 5 7 Delay scaler values DSPI_CTAR DT 2 20 0 ns 60 0 ns 100 0 ns 140 0 ns 4 40 0 ns 120 0 ns 200 0 ns 280 0 ns 8 80 0 ns 240 0 ns 400 0 ns...

Page 483: ...e first in entry in each FIFO is memory mapped For the TX FIFO the first in pointer is the transmit next pointer TXNXTPTR For the RX FIFO the first in pointer is the pop next pointer POPNXTPTR Refer to Section 20 8 3 4 Transmit First In First Out TX FIFO buffering mechanism and Section 20 8 3 5 Receive First In First Out RX FIFO buffering mechanism for details on the FIFO operation The TX FIFO is ...

Page 484: ...here TXFIFO base base address of transmit FIFO TXCTR transmit FIFO counter TXNXTPTR transmit next pointer TX FIFO depth transmit FIFO depth depth is 5 20 9 5 2 Address calculation for first in entry and last in entry in RX FIFO The memory address of the first in entry in the RX FIFO is computed by the following equation Eqn 20 13 Entry C Entry A first in 1 Entry B Entry D last in TX FIFO base Push...

Page 485: ... 485 The memory address of the last in entry in the RX FIFO is computed by the following equation Eqn 20 14 where RXFIFO base base address of receive FIFO RXCTR receive FIFO counter POPNXTPTR pop next pointer RX FIFO depth receive FIFO depth depth is 5 Last in entry address RXFIFO base 4 RXCTR POPNXTPTR 1 modulo RXFIFO depth ...

Page 486: ...Chapter 20 Deserial Serial Peripheral Interface DSPI MPC5602P Microcontroller Reference Manual Rev 4 486 Freescale Semiconductor ...

Page 487: ...e handling Classic and enhanced checksum calculation and check Single 8 byte buffer for transmission reception Extended frame mode for In Application Programming IAP purposes Wake up event on dominant bit detection True LIN field state machine Advanced LIN error detection Header response and frame timeout Slave mode Autonomous header handling Autonomous transmit receive data handling LIN automatic...

Page 488: ...ously In Master mode once the software has triggered the header transmission LINFlex does not request any software intervention until the next header transmission request in transmission mode or until the checksum reception in reception mode To minimize the CPU load in Slave mode LINFlex requires software intervention only to Trigger transmission or reception or data discard depending on the ident...

Page 489: ... to the same value as programmed in the Mantissa LINIBRR and Fraction LINFBRR registers LIN master node LIN slave node 1 LIN slave node n LIN LIN LIN Rx Tx LIN Transceiver LINFlex Controller MCU LIN Bus Application LIN PROTOCOL HANDLER REGISTER MODEL APPLICATION INTERFACE LIN status Baud rate Filter configuration Message SLAVE LIN control CONFIGURATION MESSAGE HANDLER MASTER MESSAGE HANDLER Identi...

Page 490: ...unters are updated with the new value of the baud registers after a write to LINIBRR Hence the baud register value must not be changed during a transaction The LINFBRR containing the Fraction bits must be programmed before the LINIBRR NOTE LFDIV must be greater than or equal to 1 5d i e LINIBRR 1 and LINFBRR 8 Therefore the maximum possible baudrate is fperiph_set_1_clk 24 Table 21 1 Error calcula...

Page 491: ... 52 1 0 04 57600 57605 8 69 7 0 01 57554 17 6 0 08 115200 115108 34 12 0 08 115108 8 11 0 08 230400 230216 17 6 0 08 231884 4 5 0 644 460800 460432 8 11 0 08 457143 2 3 0 794 921600 927536 4 5 0 644 941176 1 1 2 124 Table 21 1 Error calculation for programmed baud rates continued Baud rate fperiph_set_1_clk 64 MHz fperiph_set_1_clk 16 MHz Actual Value programmed in the baud rate register Error Cal...

Page 492: ...lex has a low power mode called Sleep mode To enter Sleep mode software sets the SLEEP bit in the LINCR1 In this mode the LINFlex clock is stopped Consequently the LINFlex will not update the status bits but software can still access the LINFlex registers LINFlex can be awakened exit Sleep mode either by software clearing the SLEEP bit or on detection of LIN bus activity if automatic wake up mode ...

Page 493: ...LINTX pin 21 6 2 Self Test mode LINFlex can be put in Self Test mode by setting the LBKM and SFTM bits in the LINCR This mode can be used for a Hot Self Test meaning the LINFlex can be tested as in Loop Back mode but without affecting a running LIN system connected to the LINTX and LINRX pins In this mode the LINRX pin is disconnected from the LINFlex and the LINTX pin is held recessive Figure 21 ...

Page 494: ...ffer data register LSB BDRL 1 on page 512 0x003C Buffer data register MSB BDRM 2 on page 513 0x0040 Identifier filter enable register IFER on page 514 0x0044 Identifier filter match index IFMI on page 514 0x0048 Identifier filter mode register IFMR on page 515 0x004C Identifier filter control register 0 IFCR0 on page 516 0x0050 Identifier filter control register 1 IFCR1 on page 517 0x0054 Identifi...

Page 495: ...his bit disables the checksum calculation see Table 21 4 0 Checksum calculation is done by hardware When this bit is 0 the LINCFR is read only 1 Checksum calculation is disabled When this bit is set the LINCFR is read write User can program this register to send a software calculated CRC provided CFD is 0 Note This bit can be written in Initialization mode only It is read only in Normal or Sleep m...

Page 496: ...only in Normal or Sleep mode LBKM Loop Back Mode This bit controls the Loop Back mode For more details see Section 21 6 1 Loop Back mode 0 Loop Back mode disable 1 Loop Back mode enable Note This bit can be written in Initialization mode only It is read only in Normal or Sleep mode MME Master Mode Enable 0 Slave mode enable 1 Master mode enable Note This bit can be written in Initialization mode o...

Page 497: ... Programmed in LINCFR by bits CF 0 7 0 0 Read only Hardware calculated Table 21 5 LIN master break length selection MBL Length 0000 10 bit 0001 11 bit 0010 12 bit 0011 13 bit 0100 14 bit 0101 15 bit 0110 16 bit 0111 17 bit 1000 18 bit 1001 19 bit 1010 20 bit 1011 21 bit 1100 22 bit 1101 23 bit 1110 36 bit 1111 50 bit Table 21 6 Operating mode selection SLEEP INIT Operating mode 1 0 Sleep reset val...

Page 498: ...or UARTSR is set 1 Interrupt generated when OCF bit in LINESR or UARTSR is set BEIE Bit Error Interrupt Enable 0 No interrupt when BEF bit in LINESR is set 1 Interrupt generated when BEF bit in LINESR is set CEIE Checksum Error Interrupt Enable 0 No interrupt on Checksum error 1 Interrupt generated when checksum error flag CEF in LINESR is set HEIE Header Error Interrupt Enable 0 No interrupt on B...

Page 499: ...completed 1 Interrupt generated when data received flag DRF in LINSR or UARTSR is set DTIE Data Transmitted Interrupt Enable 0 No interrupt when data transmission is completed 1 Interrupt generated when data transmitted flag DTF is set in LINSR or UARTSR HRIE Header Received Interrupt Enable 0 No interrupt when a valid LIN header has been received 1 Interrupt generated when a valid LIN header has ...

Page 500: ...de Break transmission has been completed Break Delimiter transmission is ongoing 0101 Synch Field In Slave mode a valid Break Delimiter has been detected recessive state for at least one bit time Receiving Synch Field In Master mode Synch Field transmission is ongoing 0110 Identifier Field In Slave mode a valid Synch Field has been received Receiving Identifier Field In Master mode identifier tran...

Page 501: ...fer has been filled again in order to start transmission This bit is reset by hardware in Initialization mode DRF Data Reception Completed Flag This bit is set by hardware and indicates the data reception is completed This bit must be cleared by software It is reset by hardware in Initialization mode Note This flag is not set in case of bit error or framing error DTF Data Transmission Completed Fl...

Page 502: ...INFlex moves to Idle state If LTOM bit in LINTCSR is set then OCF is cleared by hardware in Initialization mode If LTOM bit is cleared then OCF maintains its status whatever the mode is BEF Bit Error Flag This bit is set by hardware and indicates to the software that LINFlex has detected a bit error This error can occur during response field transmission Slave and Master modes or during header tra...

Page 503: ...ared by software Offset 0x0010 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 TDFL 0 RDFL 0 0 0 0 RXEN TXEN OP PCE WL UART W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21 10 UART mode control register UARTCR Table 21 10 UARTCR field descriptions Field Descri...

Page 504: ...it check disable 1 Parity transmit check enable This bit can be programmed in Initialization mode only when the UART bit is set WL Word Length in UART mode 0 7 bit data parity bit 1 8 bit data or 9 bit if PCE is set This bit can be programmed in Initialization mode only when the UART bit is set UART UART mode enable 0 LIN mode 1 UART mode This bit can be programmed in Initialization mode only Offs...

Page 505: ...de No interrupt is generated if this error occurs 0 No parity error 1 Parity error PE0 Parity Error Flag Rx0 This bit indicates if there is a parity error in the corresponding received byte Rx0 See Section 21 8 1 1 Buffer in UART mode No interrupt is generated if this error occurs 0 No parity error 1 Parity error RMB Release Message Buffer 0 Buffer is free 1 Buffer ready to be read by software Thi...

Page 506: ...eset by hardware in Initialization mode An interrupt is generated if DTIE bit in LINIER is set NF Noise Flag This bit is set by hardware when noise is detected on a received character This bit is cleared by software Offset 0x0018 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27...

Page 507: ... field indicates the LIN timeout counter value Offset 0x001C Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R OC21 OC11 W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 If LINTCSR LTOM 0 this field is read only Figure 21 13 LIN output compare register LINOCR Table 21 13 ...

Page 508: ...lue This field contains the response timeout duration in bit time for 1 byte The reset value is 0xE 14 corresponding to TResponse_Maximum 1 4 TResponse_Nominal HTO Header timeout value This field contains the header timeout duration in bit time This value does not include the Break and the Break Delimiter The reset value is the 0x2C 44 corresponding to THeader_Maximum Programming LINSR MME 1 chang...

Page 509: ...set 0x0028 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 DIV_M W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21 16 LIN integer baud rate register LINIBRR Table 21 16 LINIBRR field descriptions Field Description DIV_M LFDIV mantissa This field defines the...

Page 510: ...CFR field descriptions Field Description CF Checksum bits When LINCR1 CCD 0 this field is read only When LINCR1 CCD 1 this field is read write See Table 21 4 Offset 0x0030 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 IOBE IOPE 0 0 0 0 0 0 0 0 0 0 0 0 0 W WUR...

Page 511: ...ata Transmission Request Set by software in Slave mode to request the transmission of the LIN Data field stored in the Buffer data register This bit can be set only when HRF bit in LINSR is set Cleared by hardware when the request has been completed or aborted or on an error condition In Master mode this bit is set by hardware when BIDR DIR 1 and header transmission is completed ABRQ Abort Request...

Page 512: ...ecksum applied on the current message 0 Enhanced Checksum covering Identifier and Data fields This is compatible with LIN specification 2 0 and higher 1 Classic Checksum covering Data fields only This is compatible with LIN specification 1 3 and earlier In LIN slave mode MME bit cleared in LINCR1 this bit must be configured before the header reception If the slave has to manage frames with 2 types...

Page 513: ... 14 15 R DATA7 DATA6 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R DATA5 DATA4 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21 21 Buffer data register MSB BDRM Table 21 22 BDRM field descriptions Field Description DATA7 Data Byte 7 Data byte 7 of the data field DATA6 Data Byte 6 Data byte 6 of the data field DATA5 Data Byte 5 Data byte 5 of the data fi...

Page 514: ... 23 IFER field descriptions Field Description FACT Filter activation The software sets the bit FACT x to activate the filters x in identifier list mode In identifier mask mode bits FACT 2n 1 have no effect on the corresponding filters as they act as masks for the Identifiers 2n 0 Filter x is deactivated 1 Filter x is activated This field can be set cleared in Initialization mode only Address Base ...

Page 515: ... 27 28 29 30 31 R 0 0 0 0 0 0 0 0 IFM W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21 24 Identifier filter mode register IFMR Table 21 25 IFMR field descriptions Field Description IFM Filter mode see Table 21 26 0 Filters 2n and 2n 1 are in identifier list mode 1 Filters 2n and 2n 1 are in mask mode filter 2n 1 is the mask for the filter 2n Table 21 26 IFMR IFM configuration Bit Value Result IFM...

Page 516: ...in identifier list mode 1 Filters 14 and 15 are in mask mode filter 15 is the mask for the filter 14 Offsets 0x004C 0x0084 8 registers Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 DFL DIR CCS 0 0 ID W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21 25 Id...

Page 517: ...eset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 DFL DIR CCS 0 0 ID W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21 26 Identifier filter control register IFCR2n 1 Table 21 28 IFCR2n 1 field descriptions Field Description DFL Data Field Length This field defines the number of data bytes in the response part of the frame DFL Number of data bytes 1 DIR Di...

Page 518: ...lex MPC5602P Microcontroller Reference Manual Rev 4 518 Freescale Semiconductor ID Identifier Identifier part of the identifier field without the identifier parity Table 21 28 IFCR2n 1 field descriptions continued Field Description ...

Page 519: ...n even parity is set if the modulo 2 sum of the 7 data bits is 1 An odd parity is cleared in this case Figure 21 27 UART mode 8 bit data frame 9 bit frames The 9th bit is a parity bit Even Odd Parity can be selected by the Odd Parity bit in the UARTCR An even parity is set if the modulo 2 sum of the 8 data bits is 1 An odd parity is cleared in this case Figure 21 28 UART mode 9 bit data frame 21 8...

Page 520: ...ng a reception then the current reception is completed and no further reception can be invoked until RXEN is set If a parity error occurs during reception of any byte then the corresponding PEx bit in the UARTSR is set No interrupt is generated in this case If a framing error occurs in any byte UARTSR FE 1 then an interrupt is generated if the LINIER FEIE bit is set If the last received frame has ...

Page 521: ...Slave task of a node To transmit a header with LINFlex the application must set up the identifier the data field length and configure the message direction and checksum type in the BIDR before requesting the header transmission by setting LINCR2 HTRQ 21 8 2 1 2 Data transmission transceiver as publisher When the master node is publisher of the data corresponding to the identifier sent in the heade...

Page 522: ...have been received The application has to read the buffer BDR before resetting the DBFF bit Once the last data byte or the checksum byte has been received the DRF flag is set 21 8 2 1 4 Data discard To discard data from a slave the BIDR DIR bit must be reset and the LINCR2 DDRQ bit must be set before starting the header transmission 21 8 2 1 5 Error detection LINFlex is able to detect and handle L...

Page 523: ...filter is configured in transmission and activated and if the received identifier matches the filter a specific TX interrupt instead of an RX interrupt is generated Typically the application has to copy the data from SRAM locations to the BDR To copy the data to the right location the application has to identify the data by means of the identifier To avoid this and to ease the access to the SRAM l...

Page 524: ... filters to handle all identifiers the software has to receive the data for then a filter can be configured in mask mode see Section 21 8 2 3 Slave mode with identifier filtering in order to manage several identifiers with one filter only 21 8 2 2 3 Data discard When LINFlex receives the identifier the LINSR HRF bit is set and if LINIER HRIE 1 an RX interrupt is generated If the received identifie...

Page 525: ...ck function control bit is set LINCR1 RBLM 1 the most recent message is discarded and the oldest message is available in the buffer If buffer is not released LINSR RMB 1 before reception of next Identifier and if RBLM is set then ID along with the data is discarded 21 8 2 3 Slave mode with identifier filtering In the LIN protocol the identifier of a message is not associated with the address of a ...

Page 526: ... the direction TX or RX the data field length and the checksum type If no filter is active an RX interrupt is generated on any received identifier event If at least one active filter is configured as TX all received identifiers matching this filter generate a TX interrupt If at least one active filter is configured as RX all received identifiers matching this filter generate an RX interrupt If no ...

Page 527: ...es on RDI is sampled on fperiph_set_1_clk and the result of this measurement is stored in an internal 19 bit register called SM not user accessible see Figure 21 31 Then the LFDIV value and its associated registers LINIBRR and LINFBRR is automatically updated at the end of the fifth falling edge During a a 0 a 0 TX interrupt on identifiers matching the filters RX interrupt on all other identifiers...

Page 528: ...ld The deviation error is checked by comparing the current baud rate relative to the slave oscillator with the received LIN Synch Field relative to the master oscillator Two checks are performed in parallel The first check is based on a measurement between the first falling edge and the last falling edge of the Synch Field If D1 14 84 LHE is set If D1 14 06 LHE is not set If 14 06 D1 14 84 LHE can...

Page 529: ...s if the data field length in the BIDR is configured with a value higher than 8 data bytes 21 8 3 1 1 LIN Master mode The LINTOCR RTO field can be used to tune response timeout and frame timeout values Header timeout value is fixed to HTO 28 bit time Field OC1 checks THeader and TResponse and field OC2 checks TFrame see Figure 21 32 When LINFlex moves from Break delimiter state to Synch Field stat...

Page 530: ...it is set On the start bit of the first response data byte and if no error occurred during the header reception OC1 is updated with the value of OCResponse OCResponse CNT RTO 9 response timeout value for an 8 byte frame Once the first response byte is received OC1 and OC2 are automatically updated to check TResponse and TFrame according to RTO tolerance and DFL On the checksum reception or in case...

Page 531: ...s RXI or TXI depending on the value of identifier received Data Transmitted interrupt DTF DTIE TXI Data Received interrupt DRF DRIE RXI Data Buffer Empty interrupt DBEF DBEIE TXI Data Buffer Full interrupt DBFF DBFIE RXI Wake up interrupt WUPF WUPIE RXI LIN State interrupt 2 2 For debug and validation purposes LSF LSIE RXI Buffer Overrun interrupt BOF BOIE ERR Framing Error interrupt FEF FEIE ERR ...

Page 532: ...Chapter 21 LIN Controller LINFlex MPC5602P Microcontroller Reference Manual Rev 4 532 Freescale Semiconductor ...

Page 533: ...ing Rx Individual Mask Registers Support for 32 MBs is provided The functions of the submodules are described in subsequent sections Figure 22 1 FlexCAN block diagram 22 1 1 Overview The CAN protocol was primarily but not only designed to be used as a vehicle serial data bus meeting the specific requirements of this field real time processing reliable operation in the EMI environment of 544 byte B...

Page 534: ...CAN module includes these features Full Implementation of the CAN protocol specification Version 2 0B Standard data and remote frames Extended data and remote frames 0 to 8 bytes data length Programmable bit rate as high as 1 Mbit s Content related addressing 32 Flexible Message Buffers MBs of 0 to 8 bytes data length Each MB configurable as Rx or Tx all supporting standard and extended messages I...

Page 535: ...ozen and the module operates in a CAN Error Passive mode Ref 1 Only messages acknowledged by another CAN station will be received If FlexCAN detects a message that has not been acknowledged it will flag a BIT0 error without changing the REC as if it was trying to acknowledge the message Loop Back mode The module enters this mode when the LPB bit in the Control Register is asserted In this mode Fle...

Page 536: ...logic level 1 22 3 Memory map and registers description This section describes the registers and data structures in the FlexCAN module The base address of the module depends on the particular memory map of the device The addresses presented here are relative to the base address The address space occupied by FlexCAN has 96 bytes for registers starting at the module base address followed by MB stora...

Page 537: ...t the specific MCU documentation to find out if this feature is supported If not supported the address range 0x0880 0x097F is considered reserved space independent of the value of the BCC bit Table 22 2 FlexCAN module memory map Offset from FlexCAN_BASE 0xFFFC_0000 Register Location 0x0000 Module Configuration Register MCR on page 544 0x0004 Control Register CTRL on page 548 0x0008 Free Running Ti...

Page 538: ...0x3FFF Reserved Table 22 3 FlexCAN register reset status Register Affected by hard reset Affected by soft reset Module Configuration Register MCR Yes Yes Control Register CTRL Yes No Free Running Timer TIMER Yes Yes Reserved Rx Global Mask RXGMASK Yes No Rx Buffer 14 Mask RX14MASK Yes No Rx Buffer 15 Mask RX15MASK Yes No Error Counter Register ECR Yes Yes Error and Status Register ESR Yes Yes Inte...

Page 539: ...ceived as either recessive or dominant If FlexCAN receives this bit as dominant then it is interpreted as arbitration loss 0 Dominant is not a valid value for transmission in Extended Format frames 1 Recessive value is compulsory for transmission in Extended Format frames IDE ID Extended Bit This bit identifies whether the frame format is standard or extended 0 Frame format is standard 1 Frame for...

Page 540: ...buffers Rx Code BEFORE Rx New Frame Description Rx Code AFTER Rx New Frame Comment 0000 INACTIVE MB is not active MB does not participate in the matching process 0100 EMPTY MB is active and empty 0010 MB participates in the matching process When a frame is received successfully the code is automatically updated to FULL 0010 FULL MB is full 0010 The act of reading the C S word followed by unlocking...

Page 541: ...smit a data frame whenever a remote request frame with the same ID is received This MB participates simultaneously in both the matching and arbitration processes The matching process compares the ID of the incoming remote request frame with the ID of the MB If a match occurs this MB is allowed to participate in the current arbitration process and the Code field is automatically updated to 1110 to ...

Page 542: ... 8 entry ID table that specifies filtering criteria for accepting frames into the FIFO Table 22 9 shows the three different formats that the elements of the ID table can assume depending on the IDAM field of the MCR Note that all elements of the table must have the same format See Section 22 4 7 Rx FIFO for more information Base 0x00D0 MB5 Base 0x01D0 MB21 Base 0x00E0 MB6 Base 0x01E0 MB22 Base 0x0...

Page 543: ...0 Reserved to 0xDF 0xE0 ID Table 0 0xE4 ID Table 1 0xE8 ID Table 2 0xEC ID Table 3 0xF0 ID Table 4 0xF4 ID Table 5 0xF8 ID Table 6 0xFC ID Table 7 Unimplemented or Reserved Figure 22 3 Rx FIFO structure 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 A REM EXT RXIDA Standard 2 12 Extended 2 31 B REM EXT RXIDB_0 Standard 2 12 Extended 2 15 REM EXT RXIDB_1 Stand...

Page 544: ...ard frames are rejected RXIDA Rx Frame Identifier Format A Specifies an ID to be used as acceptance criteria for the FIFO In the standard frame format only the 11 most significant bits 3 to 13 are used for frame identification In the extended frame format all bits are used RXIDB_0 RXIDB_1 Rx Frame Identifier Format B Specifies an ID to be used as acceptance criteria for the FIFO In the standard fr...

Page 545: ...se the corresponding memory region 0x80 0xFF is used by the FIFO engine See Section 22 3 3 Rx FIFO structure and Section 22 4 7 Rx FIFO for more information 0 FIFO disabled 1 FIFO enabled 3 HALT Halt FlexCAN Assertion of this bit puts the FlexCAN module into Freeze Mode The CPU should clear it after initializing the Message Buffers and Control Register No reception or transmission is performed by ...

Page 546: ...ransmission or reception processes have finished Therefore the software can poll the FRZ_ACK bit to know when FlexCAN has actually entered Freeze Mode If Freeze mode request is negated then this bit is negated once the FlexCAN prescaler is running again If Freeze mode is requested while FlexCAN is in any of the low power modes then the FRZ_ACK bit will only be set when the low power mode is exited...

Page 547: ...ividual Rx ID masking this feature is disabled Instead of individual ID masking per MB FlexCAN uses its previous masking scheme with RXGMASK RX14MASK and RX15MASK The reception queue feature is disabled Upon receiving a message if the first MB with a matching ID that is found is still occupied by a previous unread message FlexCAN will not look for another matching MB It will override this MB with ...

Page 548: ...mber of Message Buffers This 6 bit field defines the maximum number of message buffers that will take part in the matching and arbitration processes The reset value 0x0F is equivalent to 16 MB configuration This field should be changed only while the module is in Freeze Mode Maximum MBs in use MAXMB 1 Note MAXMB has to be programmed with a value smaller or equal to the number of available Message ...

Page 549: ...egment 2 PSEG2 1 x Time Quanta 16 BOFF_MSK Bus Off Mask This bit provides a mask for the Bus Off Interrupt 0 Bus Off interrupt disabled 1 Bus Off interrupt enabled 17 ERR_MSK Error Mask This bit provides a mask for the Error Interrupt 0 Error interrupt disabled 1 Error interrupt enabled 18 CLK_SRC CAN Engine Clock Source This bit selects the clock source to the CAN Protocol Interface CPI to be eit...

Page 550: ...ated automatic recovering from Bus Off state occurs according to the CAN Specification 2 0B If the bit is asserted automatic recovering from Bus Off is disabled and the module remains in Bus Off state until the bit is negated by the user If the negation occurs before 128 sequences of 11 recessive bits are detected on the CAN bus then Bus Off recovery happens as if the BOFF_REC bit had never been a...

Page 551: ...t that the data will take some time to be actually written to the register If desired software can poll the register to discover when the data was actually written 28 LOM Listen Only Mode This bit configures FlexCAN to operate in Listen Only Mode In this mode transmission is disabled all error counters are frozen and the module operates in a CAN Error Passive mode Ref 1 Only messages acknowledged ...

Page 552: ...ividual masking per Message Buffer feature For MCUs supporting individual masks per MB setting the BCC bit in the MCR causes the RX14MASK register to have no effect on the module operation RX14MASK is used as an acceptance mask for the Identifier in Message Buffer 14 When the FEN bit in the MCR is set FIFO enabled the RX14MASK also applies to element 6 of the ID filter table This Table 22 14 TIMER...

Page 553: ...eiving frames Address Base 0x0014 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R MI31 MI30 MI29 MI28 MI27 MI26 MI25 MI24 MI23 MI22 MI21 MI20 MI19 MI18 MI17 MI16 W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R MI15 MI14 MI13 MI12 MI11 MI10 MI9 MI8 MI7 MI6 MI5 MI4 MI3 MI2 MI1 MI0 W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 22 8 Rx Buffer 1...

Page 554: ...r Tx_Err_Counter or Rx_Err_Counter decrements to a value less than or equal to 127 while the other already satisfies this condition the FLT_CONF field in the Error and Status Register is updated to reflect Error Active state If the value of Tx_Err_Counter increases to be greater than 255 the FLT_CONF field in the Error and Status Register is updated to reflect Bus Off state and an interrupt may be...

Page 555: ...register The CPU read action clears bits 16 21 Bits 22 28 are status bits Most bits in this register are read only except TWRN_INT RWRN_INT BOFF_INT and ERR_INT that are interrupt flags that can be cleared by writing 1 to them writing 0 has no effect See Section 22 4 10 Interrupts for more details Address Base 0x001C Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 ...

Page 556: ... such occurrence 1 At least one bit sent as recessive is received as dominant Note This bit is not set by a transmitter in case of arbitration field or ACK slot or in case of a node sending a passive error flag that detects dominant bits 17 BIT0_ERR Bit0 Error This bit indicates when an inconsistency occurs between the transmitted and the received bit in a message 0 No such occurrence 1 At least o...

Page 557: ...et the FLT_CONF field will not be affected by soft reset if the LOM bit is asserted 29 BOFF_INT Bus Off Interrupt This bit is set when FlexCAN enters Bus Off state If the corresponding mask bit in the Control Register BOFF_MSK is set an interrupt is generated to the CPU This bit is cleared by writing it to 1 Writing 0 has no effect 0 No such occurrence 1 FlexCAN module entered Bus Off state 30 ERR...

Page 558: ...CR is set FIFO enabled the function of the eight least significant interrupt flags BUF7I BUF0I is changed to support the FIFO operation BUF7I BUF6I and BUF5I indicate operating conditions of the FIFO while BUF4I to BUF0I are not used 01 Error Passive 1X Bus Off Address Base 0x0028 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R BUF 31M BUF 30M BUF 29M BUF 28M BUF 27M BUF 26M BUF 25M...

Page 559: ...er MBi Interrupt Each bit flags the respective FlexCAN Message Buffer MB8 to MB31 interrupt 0 No such occurrence 1 The corresponding MB has successfully completed transmission or reception 24 BUF7I Buffer MB7 Interrupt or FIFO Overflow If the FIFO is not enabled this bit flags the interrupt for MB7 If the FIFO is enabled this flag indicates an overflow condition in the FIFO frame lost because FIFO...

Page 560: ...3 14 15 R MI31 MI30 MI29 MI28 MI27 MI26 MI25 MI24 MI23 MI22 MI21 MI20 MI19 MI18 MI17 MI16 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R MI15 MI14 MI13 MI12 MI11 MI10 MI9 MI8 MI7 MI6 MI5 MI4 MI3 MI2 MI1 MI0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 22 14 Rx Individual Mask Registers RXIMR0 RXIMR31 Table 22 22 RXIMR0 RXIMR31 field descriptions Field D...

Page 561: ...RXIMR9 Base 0x08E4 RXIMR25 Base 0x08A8 RXIMR10 Base 0x08E8 RXIMR26 Base 0x08AC RXIMR11 Base 0x08EC RXIMR27 Base 0x08B0 RXIMR12 Base 0x08F0 RXIMR28 Base 0x08B4 RXIMR13 Base 0x08F4 RXIMR29 Base 0x08B8 RXIMR14 Base 0x08F8 RXIMR30 Base 0x08BC RXIMR15 Base 0x08FC RXIMR31 Table 22 23 RXIMR0 RXIMR31 addresses continued Address Register Address Register ...

Page 562: ... to Table 22 6 Similarly a Tx MB with a 1000 or 1001 code is also inactive refer to Table 22 7 An MB not programmed with 0000 1000 or 1001 will be temporarily deactivated will not participate in the current arbitration or matching run when the CPU writes to the C S field of that MB see Section 22 4 6 2 Message Buffer deactivation 22 4 2 Transmit process In order to transmit a CAN frame the CPU mus...

Page 563: ... number buffer is transmitted first When LBUF and LPRIO_EN are both negated the MB with the lowest ID is transmitted first but If LBUF is negated and LPRIO_EN is asserted the PRIO bits augment the ID used during the arbitration process With this extended ID concept arbitration is done based on the full 32 bit ID and the PRIO bits define which MB should be transmitted first therefore MBs with PRIO ...

Page 564: ...n the Interrupt Flag Register and an interrupt is generated if allowed by the corresponding Interrupt Mask Register bit Upon receiving the MB interrupt the CPU should service the received frame using the following procedure 1 Read the Control and Status word mandatory activates an internal lock for this buffer 2 Read the ID field optional needed only if a mask was used 3 Read the Data field 4 Read...

Page 565: ...is full the matching algorithm will always look for a matching MB outside the FIFO region When the frame is received it is temporarily stored in a hidden auxiliary MB called Serial Message Buffer SMB The matching process takes place during the CRC field of the received frame If a matching ID is found in the FIFO table or in one of the regular MBs the contents of the SMB will be transferred to the ...

Page 566: ...Section 22 3 4 11 Rx Individual Mask Registers RXIMR0 RXIMR31 During the matching algorithm if a mask bit is asserted then the corresponding ID bit is compared If the mask bit is negated the corresponding ID bit is don t care Please note that the Individual Mask Registers are implemented in RAM so they are not initialized out of reset Also they can only be programmed if the BCC bit is asserted and...

Page 567: ...ote the abort code in this case the MB is deactivated and not aborted because the transmission did not start yet One MB is only aborted when the abort request is captured and kept pending until one of the previous conditions are satisfied The abort procedure can be summarized as follows 1 CPU writes 1001 into the code field of the C S word 2 CPU reads the CODE field and compares it to the value th...

Page 568: ...ence mechanism for the receive process When the CPU reads the Control and Status word of an active not empty Rx MB FlexCAN assumes that the CPU wants to read the whole MB in an atomic operation and thus it sets an internal lock flag for that MB The lock is released when the CPU reads the Free Running Timer global unlock operation or when it reads the Control and Status word of another MB The MB lo...

Page 569: ...when new frames are available in the FIFO Upon receiving the interrupt the CPU must read the frame accessing an MB in the 0x80 address and then clear the interrupt The act of clearing the interrupt triggers the FIFO engine to replace the MB in 0x80 with the next frame in the queue and then issue another interrupt to the CPU If the FIFO is full and more frames continue to be received an OVERFLOW in...

Page 570: ...immediately enters the internal arbitration process but is considered as normal Tx MB with no higher priority The data length of this frame is independent of the DLC field in the remote frame that initiated its transmission If the Rx FIFO is enabled bit FEN set in MCR FlexCAN will not generate an automatic response for Remote Request Frames that match the FIFO filtering criteria If the remote fram...

Page 571: ...y the oscillator clock or it may use only the PLL clock feeding the FlexCAN module In these cases the CLK_SRC bit in the CTRL Register has no effect on the module operation The FlexCAN module supports a variety of means to setup bit timing parameters that are required by the CAN protocol The Control Register has various fields used to control bit timing parameters PRESDIV PROPSEG PSEG1 PSEG2 and R...

Page 572: ... an overview of the CAN compliant segment settings and the related parameter values Table 22 24 Time segment syntax Syntax Description SYNC_SEG System expects transitions to occur on the bus during this period Transmit Point A node in transmit mode transfers a new value to the CAN bus at this point Sample Point A node samples the bus at this point If the three samples per bit option is selected th...

Page 573: ...ole Message Buffer memory during the available time slot In order to have sufficient time to do that the following requirements must be observed A valid CAN bit timing must be programmed as indicated in Table 22 25 The peripheral clock frequency can not be smaller than the oscillator clock frequency that is the PLL can not be programmed to divide down the oscillator clock There must be a minimum r...

Page 574: ...g transmission or reception FlexCAN does the following Waits to be in either Intermission Passive Error Bus Off or Idle state Waits for all internal activities like arbitration matching move in and move out to finish Ignores the Rx input pin and drives the Tx pin as recessive Stops the prescaler thus halting all CAN protocol activities Grants write access to the Error Counters Register which is re...

Page 575: ... pin as recessive Sets the NOT_RDY and LPM_ACK bits in MCR Sends a Stop Acknowledge signal to the CPU so that it can shut down the clocks globally Stop Mode is exited by the CPU resuming the clocks and removing the Stop Mode request 22 4 10 Interrupts The module can generate as many as 38 interrupt sources 32 interrupts due to message buffers and 6 interrupts due to ORed interrupts from MBs Bus Of...

Page 576: ...ed address space also results in access error Any access to unimplemented MB or Rx Individual Mask Register locations results in access error Any access to the Rx Individual Mask Register space when the BCC bit in the MCR is negated results in access error If MAXMB is programmed with a value smaller than the available number of MBs then the unused memory space can be used as general purpose RAM sp...

Page 577: ...es Note that the Message Buffers and the Rx Individual Mask Registers are not affected by reset so they are not automatically initialized For any configuration change initialization it is required that FlexCAN is put into Freeze Mode see Section 22 4 9 1 Freeze mode The following is a generic initialization sequence applicable to the FlexCAN module Initialize the Module Configuration Register Enab...

Page 578: ...Chapter 22 FlexCAN MPC5602P Microcontroller Reference Manual Rev 4 578 Freescale Semiconductor ...

Page 579: ...as many as 4 analog input channels Clock stretching with CTU pulse Sampling and conversion time register CTR0 internal precision channels Left aligned result format Right aligned result format One Shot Scan Modes Chain Injection Mode Power down mode 2 different Abort functions allow aborting either single channel conversion or chain conversion As many as 16 data registers for storing converted dat...

Page 580: ...5 not used ADC channel 15 is internally connected to the core voltage 23 1 3 Device specific implementation Figure 23 1 ADC implementation diagram 23 2 Introduction The analog to digital converter ADC block provides accurate and fast conversions for a wide range of applications The ADC contains advanced features for normal or injected conversion It provides support for eDMA direct memory access mo...

Page 581: ... starts when the MCR NSTART bit is set By trigger An on chip internal signal triggers an ADC conversion The settings in the MCR select how conversions are triggered based on these internal signals A rising falling edge detected in the signal sets the MSR NSTART bit and starts the programmed conversion The conversion is started if and only if the MCR NSTART bit is set and the programmed level on th...

Page 582: ...r One Shot mode Conversion starts from the channel B followed by conversion of channels D E At the end of conversion of channel E the scanning of channels stops The NSTART status bit in the MSR is automatically set when the Normal conversion starts At the same time the MCR NSTART bit is reset allowing the software to program a new start of conversion In that case the new requested conversion start...

Page 583: ...ng the MCR JSTART the current conversion is suspended and the injected chain is converted At the end of the chain the JSTART bit in the MSR is reset and the normal chain conversion is resumed By an internal trigger signal from the PIT when MCR JTRGEN is set a programmed event rising falling edge depending on MCR JEDGE on the signal coming from PIT or CTU starts the injected conversion by setting t...

Page 584: ... is automatically reset together with the MCR ABORTCHAIN bit Otherwise if the scan mode is enabled a new chain conversion is started The EOC interrupt of the current aborted conversion is not generated but an ECH interrupt is generated to signal the end of the chain When a chain conversion abort is requested ABORTCHAIN bit is set while an injected conversion is running over a suspended Normal conv...

Page 585: ...ve analog input pin allowing the capacitance to charge up to the input voltage value The time to load the capacitor is referred to as sampling time After completion of the sampling phase the evaluation phase starts and all the bits corresponding to the resolution of the ADC are estimated to provide the conversion result The conversion times are programmed via the bit fields of the CTR Bit fields I...

Page 586: ...e timings refer to the unit Tck where fck 1 2 x ADC peripheral set clock Table 23 2 ADC sampling and conversion timing at 5 V 3 3 V for ADC0 Clock MHz Tck s INPSAMPLE1 Ndelay2 Tsample 3 Tsample Tck INPCMP Teval s INPLATCH Tconv s Tconv Tck 6 0 167 4 0 5 0 583 3 500 1 1 667 0 2 333 14 000 7 0 143 4 0 5 0 500 3 500 1 1 429 0 2 000 14 000 8 0 125 5 0 5 0 563 4 500 1 1 250 0 1 875 15 000 0 5 cycles 2 ...

Page 587: ...he MC_PLL_CLK in both cases 23 3 4 2 CTU in control mode In CTU control mode the CPU is able to write in the ADC registers but it cannot start any conversion Conversion requests can be generated only by the CTU trigger pulse If a normal or injected conversion is requested it is automatically discarded When a CTU trigger pulse is received with the injected channel number the conversion starts The C...

Page 588: ...3 4 Depending on the mask bits WTIMR MSKWDGxL and WTIMR MSKWDGxH an interrupt is generated on threshold violation The TRC THRCH field specifies the channel on which the analog watchdog is applied The analog watchdog is enabled by setting the corresponding TRC THREN The lower and higher threshold values for the analog watchdog are programmed using the THRHLR registers For example if channel number ...

Page 589: ... the THROP bit in TRC register will be set to 0 If the converted voltage lies between the upper and the lower threshold guard window then THROP bit in TRC register will keep its logic value The logic level of the THROP bit can be programmed by software In fact the user can decide to keep the behavior described or to invert the output logic level by setting the THRINV bit in the TRC register An exa...

Page 590: ... this the total number of interrupt lines is 2 If the ADC is in CTU Control Mode only the sources EOCTU WDG0L WDG0H WDG1L WDG1H WDG2L WDG2H WDG3L and WDG3H can generate an interrupt request 23 3 8 Power down mode The analog part of the ADC can be put in low power mode by setting the MCR PWDN After releasing the reset signal the ADC analog module is kept in power down mode by default so this state ...

Page 591: ...6 lists ADC registers with their address offsets and reset values Table 23 6 ADC digital registers Offset from base address 0xFFE0_0000 Register name Location 0x0000 Main Configuration Register MCR on page 593 0x0004 Main Status Register MSR on page 594 0x0008 0x000F Reserved 0x0010 Interrupt Status Register ISR on page 596 0x0014 0x001F Reserved 0x0020 Interrupt Mask Register IMR on page 596 0x00...

Page 592: ...annel 0 Data Register CDR0 on page 607 0x0104 Channel 1 Data Register CDR1 on page 607 0x0108 Channel 2 Data Register CDR2 on page 607 0x010C Channel 3 Data Register CDR3 on page 607 0x0110 Channel 4 Data Register CDR4 on page 607 0x0114 Channel 5 Data Register CDR5 on page 607 0x0118 Channel 6 Data Register CDR6 on page 607 0x011C Channel 7 Data Register CDR7 on page 607 0x0120 Channel 8 Data Reg...

Page 593: ...on WLSIDE Write left right aligned 0 The conversion data is written right aligned 1 Data is left aligned from 15 to 15 resolution 1 The WLSIDE bit affects all the CDR registers simultaneously See Figure 23 22 and Figure 23 22 MODE One Shot Scan 0 One Shot Mode Configures the normal conversion of one chain 1 Scan Mode Configures continuous chain conversion mode when the programmed chain conversion ...

Page 594: ...s bit is set the ongoing Chain Conversion is aborted This bit is reset by hardware as soon as a new conversion is requested 0 Conversion is not affected 1 Aborts the ongoing chain conversion ABORT Abort Conversion When this bit is set the ongoing conversion is aborted and a new conversion is invoked This bit is reset by hardware as soon as a new conversion is invoked If it is set during a scan cha...

Page 595: ... used to signal that a Normal conversion is ongoing JABORT This status bit is used to signal that an Injected conversion has been aborted This bit is reset when a new injected conversion starts JSTART This status bit is used to signal that an Injected conversion is ongoing CTUSTART This status bit is used to signal that a CTU conversion is ongoing CHADDR Current conversion channel address This sta...

Page 596: ...18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 EO CTU JEOC JECH EOC ECH W w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 23 9 Interrupt Status Register ISR Table 23 9 ISR field descriptions Field Description EOCTU End of CTU Conversion interrupt flag When this bit is set an EOCTU interrupt has occurred JEOC End of Injected Channel Conversion interrupt flag When...

Page 597: ... 0 0 0 0 0 0 0 0 0 0 0 Figure 23 10 Interrupt Mask Register IMR Table 23 10 IMR field descriptions Field Description MSKEOCTU Mask for end of CTU conversion EOCTU interrupt When set the EOCTU interrupt is enabled MSKJEOC Mask for end of injected channel conversion JEOC interrupt When set the JEOC interrupt is enabled MSKJECH Mask for end of injected chain conversion JECH interrupt When set the JEC...

Page 598: ... Mask Register 0 CIMR0 Address Base 0x0030 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 WDG 3H WDG 2H WDG 1H WDG 0H WDG 3L WDG 2L WDG 1L WDG 0L W w1c w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 23 12 Watchdog Thresh...

Page 599: ...3H MSK WDG 2H MSK WDG 1H MSK WDG 0H MSK WDG 3L MSK WDG 2L MSK WDG 1L MSK WDG 0L W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 23 13 Watchdog Threshold Interrupt Mask Register WTIMR Table 23 12 WTIMR field descriptions Field Description MSKWDGxH This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold for x 0 3 When set t...

Page 600: ...12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCLR DMAEN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 23 14 DMA Enable DMAE register Table 23 13 DMAE field descriptions Field Description DCLR DMA clear sequence enable 0 DMA request cleared by Acknowledge from DMA controller 1 DMA...

Page 601: ...6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R DMA 15 DMA 14 DMA 13 DMA 12 DMA 11 DMA 10 DMA 9 DMA 8 DMA 7 DMA 6 DMA 5 DMA 4 DMA 3 DMA 2 DMA 1 DMA 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 23 15 DMA Channel Select Register 0 DMAR0 Table 23 14 DMARx field descriptions Field Description DMAn...

Page 602: ... 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R THR EN THR INV THR OP 0 0 0 0 0 0 THRCH W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 23 16 Threshold Control Register TRCx x 0 3 Table 23 15 TRCx field descriptions Field Description THREN Threshold enable When set this bit enables the threshold detection...

Page 603: ... Base 0x0064 THRHLR1 Base 0x0068 THRHLR2 Base 0x006C THRHLR3 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 THRH W Reset 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 THRL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 23 17 Threshold Register THRHLR 0 3 Table 23 16 THRHLRx field descriptions Field Description THRH High th...

Page 604: ...0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R INPLATCH 0 OFFSHIFT 0 INPCMP 0 INPSAMP W Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 Figure 23 18 Conversion Timing Registers CTR 0 Table 23 17 CTR field descriptions Field Description INPLATCH Configuration bit for latching phase duration OFFSHIFT Configuration for offset shift characteristic 00 No shift that ...

Page 605: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 23 19 Normal Conversion Mask Register 0 NCMR0 Table 23 18 NCMR field descriptions Field Description CHn Sampling enable When set Sampling is enabled for channel...

Page 606: ...4 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 23 20 Injected Conversion Mask Register 0 JCMR0 Table 23 19 JCMR field descriptions Field Descri...

Page 607: ...corresponding result as described below Address Base 0x00C8 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 PDED W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 23 21 Power Down Exit Delay Register PDEDR Table 23 20 PDEDR field descriptions Field D...

Page 608: ...lue has been written It is automatically cleared when data is read OVERW Overwrite data This bit signals that the previous converted data has been overwritten by a new conversion This functionality depends on the value of MCR OWREN When OWREN 0 then OVERW is frozen to 0 and CDATA field is protected against being overwritten until being read When OWREN 1 then OVERW flags the CDATA field overwrite s...

Page 609: ... for the CTU registers is used in order to activate the new settings at the beginning of the next control cycle Additionally four FIFOs inside the CTU are available to store the ADC results 24 2 CTU overview The CTU receives various incoming signals from different sources PWM timers position decoder and or external pins These signals are then processed to generate as many as eight trigger events A...

Page 610: ... description The following describes the functionality of the CTU 24 3 1 Trigger events features The TGS has the capability to generate as many as eight trigger events Each trigger event has the following characteristics Generation of the trigger event is sequential in time The triggers list uses eight 16 bit double buffered registers On each Master Reload Signal MRS the new triggers list is loade...

Page 611: ...of commands The TGS Mode is selected using the TGS_M bit in the TGS Control Register 24 3 3 TGS in triggered mode The structure of the TGS in Triggered mode is shown in Figure 24 2 Figure 24 2 TGS in triggered mode The TGS has 16 input signals each of which is selected from the input selection register TGSISR selecting the states inactive rising falling or both Depending on the selection as many a...

Page 612: ...own in Figure 24 3 The red arrows indicate the MRS occurrences while the black arrows indicate the trigger event occurrences with the relevant delay in respect to the last MRS occurrence Figure 24 3 Example timing for TGS in triggered mode 24 3 4 TGS in sequential mode The structure of the TGS in sequential mode is shown in Figure 24 4 The 32 input events 16 signals with two edges for signal which...

Page 613: ...s from 0x8000 to 0x7FFF Figure 24 6 shows examples in order to explain the TGS counter counts The compare operation to stop the TGS counter is not enabled during the first counting cycle in order to allow the counting if the value of the TGSCRR is the same as the value of the TGSCCR CTU Clock as PWM EXT_IN ETIMER0_IN PWM_REL PWM_ODD_x PWM_EVEN_x RPWM_x Individual inputs selection rising falling bo...

Page 614: ...ger pulse can be linked to any of eight trigger events by the Trigger Handler block Each trigger event can be linked to one or more SU outputs If two events at the same time are linked to the same output only one output is generated and an error is provided The output is generated using the trigger with the lowest index For example if trigger 0 and trigger 1 are linked to the ADC output and they o...

Page 615: ...xternal Triggers External signals can be asynchronous with motor control clock For this reason a programmable digital filter is available The external signal is considered at 1 if it is latched N time at 1 and is considered at 0 if it is latched N time at 0 where N is a value in the digital filter control register Trigger events in the SU can be initiated by hardware or by software and an addition...

Page 616: ... Dual Conversion Mode In Single Conversion Mode only one ADC starts a conversion at a time In Dual Conversion Mode both ADCs start a conversion at the same time in particular both the ADC conversions are performed at the same time while the storage of the results is performed in series In Dual Conversion Mode 4 bits select each channel number and the conversion mode selection bit selects the Dual ...

Page 617: ...DC_0 channel 5 Single sampling ADC_0 channel 5 Single sampling ADC_0 channel 6 Not valid force EOC to CTU Single sampling ADC_0 channel 7 Not valid force EOC to CTU Single sampling ADC_0 channel 8 Not valid force EOC to CTU Single sampling ADC_0 channel 9 Not valid force EOC to CTU Single sampling ADC_0 channel 10 Not valid force EOC to CTU Single sampling ADC_0 channel 11 Single sampling ADC_0 ch...

Page 618: ...nd the channel number 4 bits The result registers only for the FIFOs can be read from two different addresses in the ADC memory map The format of the result depends on the address from which it is read The available formats are Unsigned right justified Conversion result is unsigned right justified data Bits 9 0 are used for 10 bit resolution and bits 15 10 always return zero when read Signed left ...

Page 619: ...if this bit is 0 the reload is not performed A correct reload resets the GRE bit None of the double buffered registers can be written while the GRE bit remains set The GRE bit can be reset by the occurrence of the next MRS that is a correct reload or by software setting the CGRE bit The CGRE is reset by hardware after that GRE bit is reset If the user sets the CGRE bit and at the same time a MRS o...

Page 620: ...r to avoid the problems linked to a wrong trigger the CTU output can be disabled by the CTU_ODIS bitand the ADC interface state machine can be reset by the CRU_ADC_R see Section 24 8 21 Cross triggering unit control register CTUCR 24 7 Interrupts and DMA requests 24 7 1 DMA support The DMA can be used to configure the CTU registers One DMA channel is reserved for performing a block transfer and th...

Page 621: ... trigger to the eTimer0 in the middle of an ADC conversion that is the SU will be considered busy only if a request to perform the same action that the SU is already performing occurs One of the following bits is set ADC_OE T0_OE T1_OE or ET_OE Invalid unrecognized ADC command and the ICE bit is set The MRS occurs before the enabled trigger events occur and the MRS_O bit is set TGS overrun in sequ...

Page 622: ...write operation occurs when corresponding FIFO_FULL0 flag is set ORed onto FIFO2_I IRQ203 FIFO_FULL1 This bit is set to 1 if the FIFO 1 is full FIFO_EMPTY1 This bit is set to 1 if the FIFO 1 is empty FIFO_OVERFLOW 1 This bit is set to 1 if the number of words exceeds the value set in the threshold 1 FIFO_OVERRUN1 This bit is set to 1 if a write operation occurs when corresponding FIFO_FULL1 flag i...

Page 623: ...ubunit Control Register on page 629 0x0006 T0CR Trigger 0 Compare Register on page 630 0x0008 T1CR Trigger 1 Compare Register on page 630 0x000A T2CR Trigger 2 Compare Register on page 630 0x000C T3CR Trigger 3 Compare Register on page 630 0x000E T4CR Trigger 4 Compare Register on page 630 0x0010 T5CR Trigger 5 Compare Register on page 630 0x0012 T6CR Trigger 6 Compare Register on page 630 0x0014 ...

Page 624: ...page 636 0x0048 CLR15 Commands List Register 15 on page 636 0x004A CLR16 Commands List Register 16 on page 636 0x004C CLR17 Commands List Register 17 on page 636 0x004E CLR18 Commands List Register 18 on page 636 0x0050 CLR19 Commands List Register 19 on page 636 0x0052 CLR20 Commands List Register 20 on page 636 0x0054 CLR21 Commands List Register 21 on page 636 0x0056 CLR22 Commands List Registe...

Page 625: ...ring unit control register on page 647 0x00CA CTUDF Cross Triggering Unit Digital Filter register on page 648 0x00CC CTUPCR Cross Triggering Unit Power Control Register on page 648 0x00CE 0x3FFF Reserved Table 24 4 TGS registers Offset from CTU_BASE Register Double buffered Synchronization Reset value 0x0000 TGSISR Trigger Generator Subunit Input Selection Register Yes TGSISR_RE 0x0000_0000 0x0004...

Page 626: ...lue 0x00C0 CTUEFR Cross Triggering Unit Error Flag Register No 0x0000 0x00C2 CTUIFR Cross Triggering Unit Interrupt Flag Register No 0x0000 0x00C4 CTUIR Cross Triggering Unit Interrupt Register No 0x0000 0x00C6 COTR Control ON Time Register Yes MRS 0x0000 0x00C8 CTUCR Cross triggering unit control register No 0x0000 0x00CA CTUDF Cross Triggering Unit Digital Filter Yes DFE 0x0000 0x00CC CTUPCR Cro...

Page 627: ..._ RE I9_ FE I9_ RE I8_ FE I8_ RE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R I7_ FE I7_ RE I6_ FE I6_ RE I5_ FE I5_ RE I4_ FE I4_ RE I3_ FE I3_ RE I2_ FE I2_ RE I1_ FE I1_ RE I0_ FE I0_ RE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 24 9 Trigger Generator Sub unit Input Selection Register TGSISR Table 24 8 TGSISR field descriptions Field Description...

Page 628: ...ng edge Enable 0 Disabled 1 Enabled I9_RE Input 9 PWM X 0 Rising edge Enable 0 Disabled 1 Enabled I8_FE Input 8 PWM OUT_TRIG 1 3 Falling edge Enable 0 Disabled 1 Enabled I8_RE Input 8 PWM OUT_TRIG 1 3 Rising edge Enable 0 Disabled 1 Enabled I7_FE Input 7 PWM OUT_TRIG 1 2 Falling edge Enable 0 Disabled 1 Enabled I7_RE Input 7 PWM OUT_TRIG 1 2 Rising edge Enable 0 Disabled 1 Enabled I6_FE Input 6 PW...

Page 629: ...1 Enabled I2_FE Input 2 PWM OUT_TRIG 0 1 Falling edge Enable 0 Disabled 1 Enabled I2_RE Input 2 PWM OUT_TRIG 0 1 Rising edge Enable 0 Disabled 1 Enabled h I1_FE Input 1 PWM OUT_TRIG 0 0 Falling edge Enable 0 Disabled 1 Enabled I1_RE Input 1 PWM OUT_TRIG 0 0 Rising edge Enable 0 Disabled 1 Enabled I0_FE Input 0 PWM Reload Falling edge Enable 0 Disabled 1 Enabled I0_RE Input 0 PWM Reload Rising edge...

Page 630: ... 0 Triggered Mode 1 Sequential Mode Address Base 0x0006 T0CR Base 0x0008 T1CR Base 0x000A T2CR Base 0x000C T3CR Base 0x000E T4CR Base 0x0010 T5CR Base 0x0012 T6CR Base 0x0014 T7CR Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R TxCRV W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 24 11 Trigger x Compare Register TxCR x 0 7 Table 24 10 TxCR field descriptions Field Description TxCRV ...

Page 631: ...on TGSCRV TGS Counter Reload Value Address Base 0x001C Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 T3_INDEX 0 0 0 T2_INDEX W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 T1_INDEX 0 0 0 T0_INDEX W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 24 14 Commands list control register 1 CLCR1 Table 24 13 CLCR1 field descriptions Fie...

Page 632: ...ommands List first command address T6_INDEX Trigger 6 Commands List first command address T5_INDEX Trigger 5 Commands List first command address T4_INDEX Trigger 4 Commands List first command address Address Base 0x0024 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 T3_E T3_ ETE T3_ T1E T3_ T0E T3_ ADCE 0 0 0 T2_E T2_ ETE T2_ T1E T2_ T0E T2_ ADCE W Reset 0 0 0 0 0 0 0 0 0 0 0...

Page 633: ... 1 Enabled T2_T1E Trigger 2 Timer 1 output enable 0 Disabled 1 Enabled T2_T0E Trigger 2 Timer 0 output enable 0 Disabled 1 Enabled T2_ADCE Trigger 2 ADC command output enable 0 Disabled 1 Enabled T1_E Trigger 1 enable 0 Disabled 1 Enabled T1_ETE Trigger 1 External Trigger output enable 0 Disabled 1 Enabled T1_T1E Trigger 1 Timer 1 output enable 0 Disabled 1 Enabled T1_T0E Trigger 1 Timer 0 output ...

Page 634: ...T7_E T7_ ETE T7_ T1E T7_ T0E T7_ ADCE 0 0 0 T6_E T6_ ETE T6_ T1E T6_ T0E T6_ ADCE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 T5_E T5_ ETE T5_ T5E T5_ T0E T5_ ADCE 0 0 0 T4_E T4_ ETE T4_ T1E T4_ T0E T4_ ADCE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 24 17 Trigger handler control register 2 THCR2 Table 24 16 THCR2 field descriptions Field Des...

Page 635: ...nabled T6_ADCE Trigger 6 ADC command output enable 0 Disabled 1 Enabled T5_E Trigger 5 enable 0 Disabled 1 Enabled T5_ETE Trigger 5 External Trigger output enable 0 Disabled 1 Enabled T5_T1E Trigger 5 Timer 1 output enable 0 Disabled 1 Enabled T5_T0E Trigger 5 Timer 0 output enable 0 Disabled 1 Enabled T5_ADCE Trigger 5 ADC command output enable 0 Disabled 1 Enabled T4_E Trigger 4 enable 0 Disable...

Page 636: ...002C 0x005A See Table 24 3 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R CIR FC CMS 0 FIFO 0 0 0 0 SU 0 CH W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 24 18 Commands list register x x 1 24 CMS 0 Table 24 17 CLRx CMS 0 field descriptions Field Description CIR Command Interrupt Request bit 0 Disabled 1 Enabled FC First command bit 0 Not first command 1 First command CMS Conversio...

Page 637: ...ons Field Description CIR Command Interrupt Request bit 0 Disabled 1 Enabled FC First command bit 0 Not first command 1 First command CMS Conversion mode selection 0 Single conversion mode 1 Dual conversion mode FIFO FIFO for ADC unit A B CH_B ADC unit B channel number CH_A ADC unit A channel number Address Base 0x006C Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 ...

Page 638: ... _EN0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 24 21 FIFO control register FCR Table 24 20 FCR field descriptions Field Description OR_EN3 FIFO 3 Overrun interrupt enable 0 Disabled 1 Enabled OF_EN3 FIFO 3 threshold Overflow interrupt enable 0 Disabled 1 Enabled EMPTY_EN3 FIFO 3 Empty interrupt enable 0 Disabled 1 Enabled FULL_EN3 FIFO 3 Full interrupt enable 0 Disabled 1 Enabled OR_EN2 FIFO...

Page 639: ...IFO 0 threshold Overflow interrupt enable 0 Disabled 1 Enabled EMPTY_EN0 FIFO 0 Empty interrupt enable 0 Disabled 1 Enabled FULL_EN0 FIFO 0 Full interrupt enable 0 Disabled 1 Enabled Address Base 0x0074 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R TH3 TH2 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R TH1 TH0 W Reset 0 0 0 0 0 0 0 0 0 0 ...

Page 640: ...descriptions Field Description OR3 FIFO 3 Overrun interrupt flag A read of this bit clears it 0 Interrupt has not occurred 1 Interrupt has occurred OF3 FIFO 3 threshold Overflow interrupt flag 0 Interrupt has not occurred 1 Interrupt has occurred EMP3 FIFO 3 Empty interrupt flag 0 Interrupt has not occurred 1 Interrupt has occurred FULL3 FIFO 3 Full interrupt flag 0 Interrupt has not occurred 1 In...

Page 641: ...occurred 1 Interrupt has occurred OR0 FIFO 0 Overrun interrupt flag A read of this bit clears it 0 Interrupt has not occurred 1 Interrupt has occurred OF0 FIFO 0 threshold Overflow interrupt flag 0 Interrupt has not occurred 1 Interrupt has occurred EMP0 FIFO 0 Empty interrupt flag 0 Interrupt has not occurred 1 Interrupt has occurred FULL0 FIFO 0 Full interrupt flag 0 Interrupt has not occurred 1...

Page 642: ...14 15 R 0 0 0 0 0 0 0 0 0 0 0 N_CH 4 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 DATA 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 24 25 FIFO signed Left aligned data x x 0 3 FLx Table 24 24 FLx field descriptions Field Description N_CH 4 0 Number of stored channel 0xxxx Result comes from an ADC_1 channel 1xxxx Result comes from an ADC_...

Page 643: ...r has not occurred 1 Error has occurred TGS_OSM TGS Overrun in Sequential Mode 0 Error has not occurred 1 Error has occurred MRS_O Master Reload Signal Overrun 0 Error has not occurred 1 Error has occurred ICE Invalid Command Error 0 Error has not occurred 1 Error has occurred SM_TO Trigger Overrun more than 8 EV in TGS Sequential Mode 0 Error has not occurred 1 Error has occurred MRS_RE Master Re...

Page 644: ...d T4_I Trigger 4 interrupt flag 0 Interrupt has not occurred 1 Interrupt has occurred T3_I Trigger 3 interrupt flag 0 Interrupt has not occurred 1 Interrupt has occurred T2_I Trigger 2 interrupt flag 0 Interrupt has not occurred 1 Interrupt has occurred T1_I Trigger 1 interrupt flag 0 Interrupt has not occurred 1 Interrupt has occurred T0_I Trigger 0 interrupt flag 0 Interrupt has not occurred 1 I...

Page 645: ...er 3 Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled T2_IE Trigger 2 Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled T1_IE Trigger 1 Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled T0_IE Trigger 0 Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled MRS_DMAE DMA transfer Enable on MRS occurrence if GRE bit is set 0 Interrupt disabled 1 Interrupt enabled MRS_IE MR...

Page 646: ...Cross Triggering Unit CTU MPC5602P Microcontroller Reference Manual Rev 4 646 Freescale Semiconductor Table 24 28 COTR field descriptions Field Description COTR Control ON Time and Guard Time for external trigger ...

Page 647: ...rigger 6 Software Generated 0 Trigger has not been generated 1 Trigger has been generated T5_SG Trigger 5 Software Generated 0 Trigger has not been generated 1 Trigger has been generated T4_SG Trigger 4 Software Generated 0 Trigger has not been generated 1 Trigger has been generated T3_SG Trigger 3 Software Generated 0 Trigger has not been generated 1 Trigger has been generated T2_SG Trigger 2 Sof...

Page 648: ...ure 24 31 Cross triggering unit digital filter CTUDF Table 24 30 CTUDF field descriptions Field Description 0 7 Reserved 8 15 N Digital Filter value the external signal is considered at 1 if it is latched N time at 1 and is considered at 0 if it is latched N time at 0 Address Base 0x00CC Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDIS W Reset 0 0 0...

Page 649: ...PWM supported Double buffered PWM registers Integral reload rates from 1 to 16 Half cycle reload capability Multiple output trigger events can be generated per PWM cycle via hardware Support for double switching PWM outputs Fault inputs can be assigned to control multiple PWM outputs Programmable filters for fault inputs Independently programmable PWM output polarity Independent top and bottom dea...

Page 650: ...and optionally under WAIT HALT and debug modes PWM outputs will be reactivated assuming they were active to begin with when these modes are exited Table 25 1 Modes when PWM operation is restricted Mode Description STOP Peripheral and CPU clocks are stopped PWM outputs are driven inactive WAIT HALT CPU clocks are stopped while peripheral clocks continue to run PWM outputs are driven inactive as a f...

Page 651: ... diagrams 25 4 1 Module level Figure 25 1 PWM block diagram PWMA0 PWMB0 PWMX0 Fault Channel 0 EXT_SYNC Faults Master Reload Output Triggers Aux Clock Submodule 1 Submodule 2 PWMA1 PWMB1 PWMX1 PWMA2 PWMB2 PWMX2 EXT_FORCE Interrupts Master Sync Master Force Submodule 0 Submodule 3 PWMA3 PWMB3 PWMX3 FAULT0 1 ...

Page 652: ...Compare 0 value Compare 1 value Compare 2 value Compare 3 value Compare 4 value Compare 5 value Comp vs Indep Dead Time Generator Fault protection Output override control PWMA PWMB Fault inputs from module bus Output Triggers Interrupts 16 bit counter Prescaler Clock Master Sync submodule 0 only Master Reload submodule 0 only Reload Logic LDOK Mid cycle reload Modulo counter value Preload Counter ...

Page 653: ...lize the PWM counter In this manner the PWM can be synchronized to external circuitry 25 5 5 EXT_FORCE external output force signal This input signal allows a source external to the PWM to force an update of the PWM outputs In this manner the PWM can be synchronized to external circuitry An example would be to simultaneously switch all of the PWM outputs on a commutation boundary for trapezoidal c...

Page 654: ...ed 0x0018 OCTRL Output Control Register Submodule 0 R W 0x0000 on page 665 0x001A STS Status Register Submodule 0 R W 0x0000 on page 666 0x001C INTEN Interrupt Enable Register Submodule 0 R W 0x0000 on page 667 0x001E DMAEN DMA Enable Register Submodule 0 R W 0x0000 on page 668 0x0020 TCTRL Output Trigger Control Register Submodule 0 R W 0x0000 on page 669 0x0022 DISMAP Fault Disable Mapping Regis...

Page 655: ...ister Submodule 2 R W 0x0000 on page 658 0x00A6 CTRL1 Control 1 Register Submodule 2 R W 0x0000 on page 660 0x00A8 VAL0 Value Register 0 Submodule 2 R W 0x0000 on page 662 0x00AA VAL1 Value Register 1 Submodule 2 R W 0x0000 on page 663 0x00AC VAL2 Value Register 2 Submodule 2 R W 0x0000 on page 663 0x00AE VAL3 Value Register 3 Submodule 2 R W 0x0000 on page 664 0x00B0 VAL4 Value Register 4 Submodu...

Page 656: ...66 0x010C INTEN Interrupt Enable Register Submodule 3 R W 0x0000 on page 667 0x010E DMAEN DMA Enable Register Submodule 3 R W 0x0000 on page 668 0x0110 TCTRL Output Trigger Control Register Submodule 3 R W 0x0000 on page 669 0x0112 DISMAP Fault Disable Mapping Register Submodule 3 R W 0xFFFF on page 670 0x0114 DTCNT0 Deadtime Count Register 0 Submodule 3 R W 0x07FF on page 670 0x0116 DTCNT1 Deadti...

Page 657: ...ster defines the initial count value for the PWM in PWM clock periods This is the value loaded into the submodule counter when local sync master sync or master reload is asserted based on the value of INIT_SEL or when FORCE is asserted and force init is enabled For PWM operation the buffered contents of this register are loaded into the counter at the start of every PWM cycle This register is not ...

Page 658: ...ilure to do so could result in damage to the motor or inverter For other types of motors such as DC motors this bit might safely be set enabling the PWM in debug mode The key point is that PWM parameter updates will not occur in debug mode Any motors requiring such updates should be disabled during debug mode If in doubt leave this bit cleared 1 WAITEN WAIT Enable When this bit is set the PWM cont...

Page 659: ...on 0 Initialization from a Force Out event is disabled 1 Initialization from a Force Out event is enabled 9 FORCE Force Initialization If the FORCE_SEL bits 000 writing a 1 to this bit results in a Force Out event This causes the following actions to be taken The PWMA and PWMB output pins will assume values based on the SELA and SELB bits If the FRCEN bit is set the counter value will be initializ...

Page 660: ... as it will force the clock to logic 0 11 Reserved Address Base 0x0006 Submodule 0 Base 0x0056 Submodule 1 Base 0x00A6 Submodule 2 Base 0x00F6 Submodule 3 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R LDFQ HALF FULL DT 0 PRSC 0 0 0 DBL EN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 25 6 Control 1 Register CTRL1 Table 25 4 CTRL1 field descriptions Field Description 0 3 LDFQ Load...

Page 661: ...s 9 11 PRSC Prescaler These buffered read write bits select the divide ratio of the PWM clock frequency selected by CLK_SEL as illustrated in Table 25 6 15 DBLEN Double Switching Enable This read write bit enables the double switching PWM behavior 0 Double switching disabled 1 Double switching enabled Table 25 5 PWM reload frequency LDFQ PWM reload frequency 0000 Every PWM opportunity 0001 Every 2...

Page 662: ...iods This register is not byte accessible NOTE The VAL0 register is buffered The value written does not take effect until the LDOK bit is set and the next PWM load cycle begins VAL0 cannot be written when LDOK is set Reading VAL0 reads the value in a buffer It is not necessarily the value the PWM generator is currently using Table 25 6 PWM prescaler PRSC PWM clock frequency 000 fclk 001 fclk 2 010...

Page 663: ... 16 bit signed value in this register defines the count value to set PWMA high Figure 25 2 This register is not byte accessible NOTE The VAL2 register is buffered The value written does not take effect until the LDOK bit is set and the next PWM load cycle begins VAL2 cannot be written when LDOK is set Reading VAL2 reads the value in a buffer and not necessarily the value the PWM generator is curre...

Page 664: ...set PWMB high Figure 25 2 This register is not byte accessible NOTE The VAL4 register is buffered The value written does not take effect until the LDOK bit is set and the next PWM load cycle begins VAL4 cannot be written when LDOK is set Reading VAL4 reads the value in a buffer and not necessarily the value the PWM generator is currently using Address Base 0x000E Submodule 0 Base 0x005E Submodule ...

Page 665: ... 0 0 0 0 0 Figure 25 12 Value register 5 VAL5 Address Base 0x0018 Submodule 0 Base 0x0068 Submodule 1 Base 0x00B8 Submodule 2 Base 0x0108 Submodule 3 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R PWM A_IN PWM B_IN PWM X_IN 0 0 POL A POL B POL X 0 0 PWMAFS PWMBFS PWMXFS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 25 13 Output Control register OCTRL Table 25 7 OCTRL field descrip...

Page 666: ...1x Output is tristated 12 13 PWMBFS PWMB Fault State These bits determine the fault state for the PWMB output during fault conditions and STOP mode It may also define the output state during WAIT HALT and DEBUG modes depending on the settings of WAITEN and DBGEN 00 Output is forced to logic 0 state prior to consideration of output polarity control 01 Output is forced to logic 1 state prior to cons...

Page 667: ...0 No reload error occurred 1 Reload signal occurred with non coherent data and LDOK 0 3 RF Reload Flag This read write flag is set at the beginning of every reload cycle regardless of the state of the LDOK bit Clear RF by writing a logic one to the RF bit when VALDE is clear non DMA mode RF can also be cleared by the DMA done signal when VALDE is set DMA mode Reset clears RF 0 No new reload cycle ...

Page 668: ...corresponding CMPF bit will not cause an interrupt request 1 The corresponding CMPF bit will cause an interrupt request Address Base 0x001E Submodule 0 Base 0x006E Submodule 1 Base 0x00BE Submodule 2 Base 0x010E Submodule 3 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 VAL DE FAN D 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 25 16 DMA Enable register...

Page 669: ..._EN 5 0 Output Trigger Enables These bits enable the generation of OUT_TRIG0 and OUT_TRIG1 outputs based on the counter value matching the value in one or more of the VAL0 5 registers where OUT_TRIG_EN 0 refers to VAL0 OUT_TRIG_EN 1 refers to VAL1 and so on VAL0 VAL2 and VAL4 are used to generate OUT_TRIG0 and VAL1 VAL3 and VAL5 are used to generate OUT_TRIG1 The OUT_TRIGx signals are only asserte...

Page 670: ...1 1 1 1 1 Figure 25 18 Fault Disable Mapping register DISMAP Table 25 12 DISMAP field descriptions Field Description 4 7 DISX PWMX Fault Disable Mask Each of the 4 bits of this read write field is one to one associated with the four FAULTx inputs The PWMX output will be turned off if there is a logic 1 on a FAULTx input and a 1 in the corresponding bit of the DISX field A reset sets all DISX bits ...

Page 671: ...dule 2 PWMx_EN 1 enables disables submodule 1 PWMx_EN 0 enables disables submodule 0 Address Base 0x0024 Submodule 0 Base 0x0074 Submodule 1 Base 0x00C4 Submodule 2 Base 0x0114 Submodule 3 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 DTCNT0 W Reset 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 Figure 25 19 Deadtime Count Register 0 DTCNT0 Address Base 0x0026 Submodule 0 Base 0x0076 S...

Page 672: ... These bits enable the PWMB outputs of each submodule 0 PWMB output disabled 1 PWMB output enabled 12 15 PWMX_EN 3 0 PWMX Output Enables These bits enable the PWMX outputs of each submodule These bits should be set to 0 output disabled when a PWMX pin is being used for deadtime correction 0 PWMX output disabled 1 PWMX output enabled Address Base 0x0142 Access User read write 0 1 2 3 4 5 6 7 8 9 10...

Page 673: ...ontrolled Output Register SWCOUT Table 25 15 SWCOUT field descriptions Field Description 8 OUTA_3 Software Controlled Output A_3 This bit is only used when SELA for submodule 3 is set to 0b10 It allows software control of which signal is supplied to the deadtime generator of that submodule 0 A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWMA 1 A logic 1 is supplied to t...

Page 674: ...trolled Output B_1 This bit is only used when SELB for submodule 1 is set to 0b10 It allows software control of which signal is supplied to the deadtime generator of that submodule 0 A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWMB 1 A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWMB 14 OUTA_0 Software Controlled Output A_0 This bit is only...

Page 675: ... Generated PWMA_2 signal is used by the deadtime logic 01 Inverted generated PWMA_2 signal is used by the deadtime logic 10 OUTA_2 bit is used by the deadtime logic 11 Reserved 6 7 SELB_2 PWMB_2 Control Select This field selects possible over rides to the generated PWMB signal in submodule 2 that will be passed to the deadtime logic upon the occurrence of a Force Out event in that submodule 00 Gen...

Page 676: ... 0 that will be passed to the deadtime logic upon the occurrence of a Force Out event in that submodule 00 Generated PWMA_0 signal is used by the deadtime logic 01 Inverted generated PWMA_0 signal is used by the deadtime logic 10 OUTA_0 bit is used by the deadtime logic 11 Reserved 14 15 SELB_0 PWMB_0 Control Select This field selects possible over rides to the generated PWMB signal in submodule 0...

Page 677: ...ite a 1 to this location to clear the corresponding LDOK If a reload occurs with LDOK set at the same time that CLDOK is written then the reload will not be performed and LDOK will be cleared This bit is self clearing and always reads as a 0 12 15 LDOK 3 0 Load Okay This read set bit loads the PRSC bits of CTRL1 and the INIT and VALx registers into a set of buffers The buffered prescaler divisor s...

Page 678: ...uts disabled by this fault are not enabled until the FFLAGx bit is clear at the start of a half cycle without regard to the state of the FFPINx bit The PWM outputs disabled by this fault input will not be re enabled until the actual FAULTx input signal de asserts since the fault input will combinationally disable the PWM outputs as programmed in DISMAP 1 Safe mode PWM outputs disabled by this faul...

Page 679: ...5 FFLAG Fault Flags These read only flags are set within 2 CPU cycles after a transition to active on the FAULTx pin Clear FFLAGx by writing a logic one to it A reset clears FFLAG 0 No fault on the FAULTx pin 1 Fault on the FAULTx pin Note The FFLAG 3 0 flags will be set out of reset They should be cleared before enabling the Fault Control feature Address Base 0x0150 Access User read write 0 1 2 3...

Page 680: ...also be traded off against the desire for minimal latency in recognizing input transitions Turning on the input filter setting FILT_PER to a non zero value introduces a latency of FILT_CNT 4 x FILT_PER x IPBus clock period Note that even when the filter is enabled there is a combinational path to disable the PWM outputs This is to ensure rapid response to fault conditions and also to ensure fault ...

Page 681: ...y a function of the turn on and turn off edge values Figure 25 29 also illustrates an additional enhancement to the PWM generation process When the counter resets it is reloaded with a user specified value which may or may not be zero If the value chosen happens to be the 2 s complement of the modulus value then the PWM generator operates in signed mode This means that if each PWM s turn on and tu...

Page 682: ...here a 50 duty cycle results in 0 volts on the load Duty cycles less than 50 result in negative load voltages and duty cycles greater than 50 generate positive load voltages If the module is set to signed mode operation the INIT and VAL1 values are the same number with opposite signs then there is a direct proportionality between the PWM turn off edge value and the motor voltage INCLUDING the sign...

Page 683: ... can be seen in Figure 25 32 In this case an H bridge circuit is driven by four PWM signals to control the voltage waveform on the primary of a transformer Both left and right side PWMs are configured to always generate a square wave with 50 duty cycle This works for the H bridge since no narrow pulse widths are generated reducing the high frequency switching requirements of the transistors Notice...

Page 684: ...onstruction This method support two independent rising edges and two independent falling edges per PWM cycle The VAL2 and VAL3 registers generate the even channel labeled as PWMA in the figure while VAL4 and VAL5 generate the odd channel The two channels are combined using XOR logic see Figure 25 41 as shown in Figure 25 33 The DBLPWM signal can be run through the deadtime insertion logic Top Left...

Page 685: ...ardware per PWM cycle without the requirement of another timer module Figure 25 34 shows how this is accomplished When specifying complimentary mode of operation only two edge comparators are required to generate the output PWM signals for a given submodule This means that the other comparators are free to perform other functions In this example the software does not need to respond quickly after ...

Page 686: ... a lower frequency but still synchronized to the timer in submodule 0 Figure 25 35 shows how this feature can be used to schedule ADC triggers over multiple PWM cycles A suggested use for this configuration would be to use the lower frequency submodule to control the sampling frequency of the software control algorithm where multiple ADC triggers can now be scheduled over the entire sampling perio...

Page 687: ...ubmodule from submodule 0 or from external to the PWM module and in most cases is supplied from an external timer channel configured for output compare In a typical application software sets up the desired states of the output pins in preparation for the next FORCE_OUT event This selection lays dormant until the FORCE_OUT signal transitions and then all outputs are switched simultaneously The sign...

Page 688: ...l which immediately changes the state of the PWM pins to the next commutation state with no software latency Figure 25 36 Sensorless BLDC commutation using the force out function 25 8 Functional details This section describes the implementation of various features of the PWM in greater detail 25 8 1 PWM clocking Figure 25 37 shows the logic used to generate the main counter clock Each submodule ca...

Page 689: ...ister reload logic The register reload logic determines when the outer set of registers for all double buffered register pairs will be transferred to the inner set of registers The register reload event can be scheduled to occur every n PWM cycles using the LDFQ bits and the FULL bit A half cycle reload option is also supported HALF where the reload can take place in the middle of a PWM cycle The ...

Page 690: ... either on or off chip depending on the system architecture This signal may be selected as the source for counter initialization so that an external source can control the period of all submodules If the Master Reload signal is selected as the source for counter initialization then the period of the counter will be locked to the register reload frequency of submodule 0 Since the reload frequency i...

Page 691: ...f the counter is not initialized at the start of each commutation interval the result will be an oscillation caused by the beating between the PWM frequency and the commutation frequency 25 8 4 PWM generation Figure 25 40 illustrates how PWM generation is accomplished in each submodule In each case two comparators and associated VALx registers are utilized for each PWM output signal One comparator...

Page 692: ...he flip flop are both asserted then the flop output goes to 0 25 8 5 Output compare capabilities By using the VALx registers in conjunction with the submodule timer and 16 bit comparators buffered output compare functionality can be achieved with no additional hardware required Specifically the following output compare functions are possible An output compare sets the output high An output compare...

Page 693: ...cified by software via the OUTA and OUTB bits The selection can be determined ahead of time and when a FORCE_OUT event occurs these values are presented to the signal selection mux which immediately switches the requested signal to the output of the mux for further processing downstream Figure 25 41 Force out logic The local Force signal of submodule 0 can be broadcast as the Master Force signal t...

Page 694: ...tput as a pair of complementary channels The PWM pins are paired as shown in Figure 25 42 in complementary channel operation The IPOL bit determines which signal is connected to the output pin PWMA or PWMB Figure 25 42 Complementary channel pair The complementary channel operation is for driving top and bottom transistors in a motor drive circuit such as the one in Figure 25 43 Figure 25 43 Typica...

Page 695: ...d bottom transistor However the transistor s characteristics may cause its switching off time to be longer than its switching on time To avoid the conducting overlap of top and bottom transistors deadtime needs to be inserted in the switching period as illustrated in Figure 25 45 The deadtime generators automatically insert software selectable activation delays into the pair of PWM outputs The dea...

Page 696: ...me insertion 25 8 9 Top bottom correction In complementary mode either the top or the bottom transistor controls the output voltage However deadtime has to be inserted to avoid overlap of conducting interval between the top and bottom transistor Both transistors in complementary mode are off during deadtime allowing the output voltage to be determined by the current status of load and introduce di...

Page 697: ...it in complementary channel operation only one of the transistors will be effective in controlling the output voltage at any given time This depends on the direction of the motor current for that pair See Figure 25 47 To correct distortion one of two different factors must be added to the desired PWM value depending on whether the top or bottom transistor is controlling the output voltage Therefor...

Page 698: ...s Figure 25 47 Current status sense scheme for deadtime correction Both D flip flops latch low DT0 0 DT1 0 during deadtime periods if current is large and flowing out of the complementary circuit See Figure 25 47 Both D flip flops latch the high DT0 1 DT1 1 during deadtime periods if current is also large and flowing into the complementary circuit However under low current the output voltage of th...

Page 699: ... inverter being turned ON The voltage level required at the PWM output pin to turn the transistor ON or OFF is a function of the logic between the pin and the transistor Therefore it is imperative that the user program the POLA and POLB bits before enabling the output pins A fault condition can result in the PWM output being tristated forced to a logic 1 or forced to a logic 0 depending on the val...

Page 700: ... the output pins are forced to logic 0 logic 1 or tristated depending the values of the PWMxFS bits The fault decoder disables PWM pins selected by the fault logic and the disable mapping register DISMAP See Figure 25 50 for an example of the fault disable logic Each bank of bits in DISMAP control the mapping for a single PWM pin Refer to Table 25 21 The fault protection is enabled even when the P...

Page 701: ...ding FFPINx and fault flag FFLAGx bits are set The FFPINx bit remains set as long as the filtered FAULTx pin is zero Clear FFLAGx by writing a logic 1 to FFLAGx If the FIEx FAULTx pin interrupt enable bit is set the FFLAGx flag generates a CPU interrupt request The interrupt request latch remains set until Software clears the FFLAGx flag by writing a logic one to the bit Software clears the FIEx b...

Page 702: ...aring the automatic clearing mode bit FAUTOx configures faults from the FAULTx pin for manual clearing If the fault safety mode bits FSAFEx are clear then PWM pins disabled by the FAULTx pins are enabled when Software clears the corresponding FFLAGx flag The pins are enabled when the next PWM half cycle begins regardless of the logic level detected by the filter at the FAULTx pin See Figure 25 52 ...

Page 703: ...tor is engaged RUN equals one But the OUTx bits can control the PWM pins while the PWM generator is off RUN equals zero Thus fault clearing occurs at IPBus cycles while the PWM generator is off and at the start of PWM cycles when the generator is engaged 25 8 16 Fault testing The FTEST bit simulates a fault condition on each of the fault inputs 25 9 PWM generator loading 25 9 1 Load enable The LDO...

Page 704: ...ncy The LDFQ bits in the CTRL1 register select an integral loading frequency of one to 16 PWM reload opportunities The LDFQ bits take effect at every PWM reload opportunity regardless the state of the LDOK bit The HALF and FULL bits in the CTRL1 register control reload timing If FULL is set a reload opportunity occurs at the end of every PWM cycle when the count equals VAL1 If HALF is set a reload...

Page 705: ...PWMF reload interrupt request 25 9 4 Reload errors Whenever one of the VALx or PSRC registers is updated the RUF flag is set to indicate that the data is not coherent RUF will be cleared by a successful reload which consists of the reload signal while LDOK is set If RUF is set and LDOK is clear when the reload signal occurs a reload error has taken place and the REF bit is set If RUF is clear when...

Page 706: ...25 12 DMA Each submodule can request a DMA write request for its double buffered VALx registers Table 25 22 Interrupt summary Core interrupt flag Interrupt flag Interrupt enable Name Description COF0 CMPF_0 CMPIE_0 Submodule 0 compare interrupt Compare event has occurred RF0 RF_0 RIE_0 Submodule 0 reload interrupt Reload event has occurred COF1 CMPF_1 CMPIE_1 Submodule 1 compare interrupt Compare ...

Page 707: ...iption Submodule 0 write request VALDE_0 VALx write request VALx registers need to be updated Submodule 1 write request VALDE_1 VALx write request VALx registers need to be updated Submodule 2 write request VALDE_2 VALx write request VALx registers need to be updated Submodule 3 write request VALDE_3 VALx write request VALx registers need to be updated ...

Page 708: ...Chapter 25 FlexPWM MPC5602P Microcontroller Reference Manual Rev 4 708 Freescale Semiconductor ...

Page 709: ... COMP1 and COMP2 registers provide the values to which the counter is compared If a match occurs the OFLAG signal can be set cleared or toggled At match time an interrupt is generated if enabled and the new compare value is loaded into the COMP1 or COMP2 registers from CMPLD1 and CMPLD2 if enabled The Prescaler provides different time bases useful for clocking the counter timer The Counter provide...

Page 710: ... support of capture registers and compare registers 32 bit watchdog capability to detect stalled quadrature counting OFLAG comparison for safety critical applications Programmable operation during debug mode and stop mode Programmable input filter Counting start can be synchronized across counters ...

Page 711: ...diagram The eTimer block diagram is shown in Figure 26 1 Figure 26 1 eTimer block diagram Watchdog Timer Channel 0 Channel n Channel 1 Channel 2 Filter Filter Filter 1 Error signal OFLAG 0 OFLAG 1 OFLAG 2 OFLAG n WDF Count IPBus Clock Reset DMA Inp 0 Inp 2 Inp 1 Filter Aux Inp 0 Filter Aux Inp 1 Filter Aux Inp 2 ...

Page 712: ...ETC 5 0 eTimer input outputs These pins can be independently configured to be either timer input sources or output flags 26 6 Memory map and registers 26 6 1 Overview Table 26 1 shows the memory map for the eTimer module Switch Matrix Polarity Select Input Filter Prescaler Edge Detect Control Status and DMA I F Control Counter Load Hold Capture1 COMP1 COMP2 CMPLD1 CMPLD2 OFLAG Control Comparator C...

Page 713: ...6 INTDMA Interrupt and DMA Enable Register on page 726 0x0018 CMPLD1 Comparator Load Register 1 on page 727 0x001A CMPLD2 Comparator Load Register 2 on page 728 0x001C CCCTRL Compare and Capture Control Register on page 728 0x001E FILT Input Filter Register on page 730 eTimer Channel 1 0x0020 COMP1 Compare Register 1 on page 716 0x0022 COMP2 Compare Register 2 on page 717 0x0024 CAPT1 Capture Regi...

Page 714: ...ol Register 3 on page 724 0x0054 STS Status Register on page 725 0x0056 INTDMA Interrupt and DMA Enable Register on page 726 0x0058 CMPLD1 Comparator Load Register 1 on page 727 0x005A CMPLD2 Comparator Load Register 2 on page 728 0x005C CCCTRL Compare and Capture Control Register on page 728 0x005E FILT Input Filter Register on page 730 eTimer Channel 3 0x0060 COMP1 Compare Register 1 on page 716...

Page 715: ...C CNTR Counter Register on page 719 0x008E CTRL1 Control Register 1 on page 720 0x0090 CTRL2 Control Register 2 on page 722 0x0092 CTRL3 Control Register 3 on page 724 0x0094 STS Status Register on page 725 0x0096 INTDMA Interrupt and DMA Enable Register on page 726 0x0098 CMPLD1 Comparator Load Register 1 on page 727 0x009A CMPLD2 Comparator Load Register 2 on page 728 0x009C CCCTRL Compare and C...

Page 716: ... 13 Usage of compare registers 0x00AE CTRL1 Control Register 1 on page 720 0x00B0 CTRL2 Control Register 2 on page 722 0x00B2 CTRL3 Control Register 3 on page 724 0x00B4 STS Status Register on page 725 0x00B6 INTDMA Interrupt and DMA Enable Register on page 726 0x00B8 CMPLD1 Comparator Load Register 1 on page 727 0x00BA CMPLD2 Comparator Load Register 2 on page 728 0x00BC CCCTRL Compare and Captur...

Page 717: ...ase 0x0060 eTimer3 Base 0x0080 eTimer4 Base 0x00A0 eTimer5 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R COMP1 15 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 26 3 Compare register 1 COMP1 Table 26 2 COMP1 field descriptions Field Description COMP1 15 0 Compare 1 Stores the value used for comparison with the counter value Note This register is not byte accessible Address Base ...

Page 718: ... 0x0084 eTimer4 Base 0x00A4 eTimer5 Access User read only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R CAPT1 15 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 26 5 Capture register 1 CAPT1 Table 26 4 CAPT1 field descriptions Field Description CAPT1 15 0 Capture 1 Stores the value captured from the counter Note This register is not byte accessible Address Base 0x0006 eTimer0 Base 0x0026 eTimer1 Base 0...

Page 719: ... LOAD 15 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 26 7 Load register LOAD Table 26 6 LOAD field descriptions Field Description LOAD 15 0 Load Stores the value used to initialize the counter Note This register is not byte accessible Address Base 0x000A eTimer0 Base 0x002A eTimer1 Base 0x004A eTimer2 Base 0x006A eTimer3 Base 0x008A eTimer4 Base 0x00AA eTimer5 Access User read only 0 1 2 3 4 ...

Page 720: ...ns Field Description CNTMODE 2 0 Count Mode These bits control the basic counting and behavior of the counter 000 No Operation 001 Count rising edges of primary source Rising edges counted only when PIPS 0 Falling edges counted when PIPS 1 If primary count source is IP bus clock only rising edges are counted regardless of PIPS value 010 Count rising and falling edges of primary source IP Bus clock...

Page 721: ...t the counter is to be loaded from the CMPLD registers then CMPLD1 will have priority if both compares happen at the same value When output mode 0x4 is used alternating values of COMP1 and COMP2 are used to generate successful comparisons For example the counter counts until COMP1 value is reached reinitializes then counts until COMP2 value is reached reinitializes then counts until COMP1 value is...

Page 722: ...Enable This bit determines the direction of the external pin 0 The external pin is configured as an input 1 OFLAG output signal is driven on the external pin Other timer channels using this external pin as their input will see the driven value The polarity of the signal will be determined by the OPS bit RDNT Redundant Channel Enable This bit enables redundant channel checking between adjacent chan...

Page 723: ...n the module to force the reinitialization of this channel when the other channel has an active compare event 00 Other channels cannot force reinitialization of this channel 01 Other channels may force a reinitialization of this channel s counter using the LOAD reg 10 Other channels may force a reinitialization of this channel s counter with the CMPLD2 reg when this channel is counting down or the...

Page 724: ... COMP2 0100 Toggle OFLAG output using alternating compare registers 0101 Set on compare with COMP1 cleared on secondary source input edge 0110 Set on compare with COMP2 cleared on secondary source input edge 0111 Set on compare cleared on counter roll over 1000 Set on successful compare on COMP1 clear on successful compare on COMP2 1001 Asserted while counter is active cleared when counter is stop...

Page 725: ...during debug mode 10 Force OFLAG to logic 0 prior to consideration of the OPS bit during debug mode 11 Both halt counter and force OFLAG to 0 during debug mode Address Base 0x0014 eTimer0 Base 0x0034 eTimer1 Base 0x0054 eTimer2 Base 0x0074 eTimer3 Base 0x0094 eTimer4 Base 0x00B4 eTimer5 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 WDF RCF ICF2 ICF1 IEHF IELF TOF TCF2 ...

Page 726: ...bit IELF Input Edge Low Flag This bit is set when a negative input transition occurs on an input selected by SECSRC while the counter is enabled This bit is cleared by writing a 1 to this bit TOF Timer Overflow Flag This bit is set when the counter rolls over its maximum value 0xFFFF or 0x0000 depending on count direction This bit is cleared by writing a 1 to this bit TCF2 Timer Compare 2 Flag Thi...

Page 727: ...D1 register whenever data is transferred out of the CMPLD1 reg into either the CNTR COMP1 or COMP2 registers WDFIE Watchdog Flag Interrupt Enable Setting this bit enables interrupts when the WDF bit is set This bit is used in channel 0 only RCFIE Redundant Channel Flag Interrupt Enable Setting this bit enables interrupts when the RCF bit is set This bit is used in even channels 0 2 4 only ICF2IE I...

Page 728: ...re 26 15 Comparator Load 1 CMPLD1 Table 26 15 CMPLD1 field descriptions Field Description CMPLD1 15 0 Specifies the preload value for the COMP1 register Address Base 0x001A eTimer0 Base 0x003A eTimer1 Base 0x005A eTimer2 Base 0x007A eTimer3 Base 0x009A eTimer4 Base 0x00BA eTimer5 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R CMPLD2 15 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figu...

Page 729: ...upon successful compare with the value in COMP2 CMPMODE Compare Mode These bits control when the COMP1 and COMP2 registers are used in regards to the counting direction 00 COMP1 register is used when the counter is counting up COMP2 register is used when the counter is counting up 01 COMP1 register is used when the counter is counting down COMP2 register is used when the counter is counting up 10 ...

Page 730: ...nput capture process This bit can be cleared at any time to disable input capture operation This bit is self cleared when in one shot mode and the enabled capture circuit s has had a capture event s 0 Input capture operation is disabled 1 Input capture operation as specified by the CPT1MODE and CPT2MODE bits is enabled Address Base 0x001E eTimer0 Base 0x003E eTimer1 Base 0x005E eTimer2 Base 0x007E...

Page 731: ...he eTimer plus an offset of 0x100 26 6 3 1 Watchdog Time Out registers WDTOL and WDTOH Address Base 0x0100 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R WDTOL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 26 19 Watchdog Time out Low Word register WDTOL Address Base 0x0102 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R WDTOH W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ...

Page 732: ...caler if it is being used and counter in each channel Multiple ENBL bits can be set at the same time to synchronize the start of separate channels If an ENBL bit is set then the corresponding channel will start counting as soon as the CNTMODE field has a value other than 000 When an ENBL bit is clear the corresponding channel maintains its current value 0 Timer channel is disabled 1 Timer channel ...

Page 733: ...hich DMA request source will be muxed onto one of the two module level DMA request outputs Make sure each of the DREQ registers is programmed with a different value else a single DMA source will cause multiple DMA requests Enable a DMA request in the channel specific INTDMA register after the DREQ registers are programmed 00000Channel 0 CAPT1 DMA read request 00001Channel 0 CAPT2 DMA read request ...

Page 734: ...mable Any channel can be assigned as a Master A master s compare signal can be broadcast to the other channels within the module The other channels can be configured to reinitialize their counters and or force their OFLAG output signals to predetermined values when a Master channel s compare event occurs 26 7 2 Counting modes The selected external signals are sampled at the eTimer s base clock rat...

Page 735: ... encoded signals Quadrature signals are usually generated by rotary or linear sensors used to monitor movement of motor shafts or mechanical equipment The quadrature signals are square waves that are 90 degrees out of phase The decoding of quadrature signal provides both count and direction information Figure 26 24 shows a timing diagram illustrating the basic operation of a quadrature incremental...

Page 736: ...aisy chained mode enables multiple counters to be cascaded to yield longer counter lengths When operating in cascade mode a special high speed signal path is used between modules rather than the OFLAG output signal If the selected source counter is counting up and it experiences a compare event the counter will be incremented If the selected source counter is counting down and it experiences a com...

Page 737: ...es is equal to the compare value minus the init value This mode is useful for driving step motor systems NOTE This does not work if the PRISRC is set to 11000 Figure 26 27 Pulse Output mode 26 7 2 11 FIXED FREQUENCY PWM mode When the counter is set up for CNTMODE 001 count through roll over LENGTH 0 continuous count ONCE 0 and the OFLAG OUTMODE is 0111 set on compare cleared on counter roll over t...

Page 738: ...ing alternating compare registers In this variable frequency PWM mode the COMP2 value defines the desired pulse width of the on time and the COMP1 register defines the off time COMP1 is used when OFLAG 0 and COMP2 is used when OFLAG 1 Use caution when changing COMP1 and COMP2 while the counter is active If the counter has already passed the new value it will count to 0xFFFF or 0x0000 roll over the...

Page 739: ... mode or 101 count with direction mode Use count through roll over LENGTH 0 and continuous count ONCE 0 Set COMP1 and CMPLD1 to the upper boundary value Set COMP2 and CMPLD2 to the lower boundary value Set CMPMODE 10 COMP1 is used when counting up and COMP2 is used when counting down Set CLC2 110 load CNTR with value of CMPLD2 on COMP1 compare and CLC1 111 load CNTR with value of CMPLD1 on COMP2 c...

Page 740: ...er capture sequence is initiated Both capture circuits are capable of generating an interrupt to the CPU 26 7 3 4 Master Slave mode Any timer channel can be assigned as a Master MSTR 1 A Master s compare signal can be broadcast to the other channels within the module The other counters can be configured to reinitialize their counters COINIT 1 and or force their OFLAG output signals COFRC 1 to pred...

Page 741: ...rupt Compare of the counter and COMP2 register TOF TOFIE Overflow interrupt Generated on counter roll over or roll under IELF IELFIE Input Low Edge interrupt Falling edge of the secondary input signal IEHF IEHFIE Input High Edge interrupt Rising edge of the secondary input signal ICF1 ICF1IE Input Capture 1 interrupt Input capture event for CAPT1 ICF2 ICF2IE Input Capture 2 interrupt Input capture...

Page 742: ...Chapter 26 eTimer MPC5602P Microcontroller Reference Manual Rev 4 742 Freescale Semiconductor ...

Page 743: ...ined memory mapped address locations in a module under protection from being written The address locations that can be protected are module specific The register protection module is located between the module under protection and the PBRIDGE This is shown in Figure 27 1 Figure 27 1 Register protection module block diagram 27 2 2 Features The register protection module includes these features PBRI...

Page 744: ...ernal signals 27 2 5 Memory map and registers description This section provides a detailed description of the memory map of a module using the Register protection The original 16 KB module memory space is divided into five areas as shown in Figure 27 2 Figure 27 2 Register protection memory diagram Area 1 is 6 KB and holds the normal functional module registers and is transparent for all read writ...

Page 745: ...mode There is one configuration hard lock bit per module that prevents all further modifications to the Soft Lock Bits and can only be cleared by a system reset once set The other bits if set will allow user access to the protected module If any locked byte is accessed with a write transaction a transfer error will be issued to the system and the write transaction will not be executed This is true...

Page 746: ...ble by one associated bit in a SLBRn SLBm according to the mapping described in Table 27 2 27 2 5 2 3 Soft Lock Bit Register SLBR0 1535 These registers hold the Soft Lock Bits for the protected registers in memory area 1 Table 27 3 gives some examples how SLBRn SLB and SLBRn MRn go together Address Base 0x3800 0x3DFF Access User read only Supervisor read write 0 1 2 3 4 5 6 7 R 0 0 0 0 SLB0 SLB1 S...

Page 747: ...25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 27 4 Global Configuration Register GCR Table 27 4 GCR field descriptions Field Description HLB Hard Lock Bit This register cannot be cleared once it is set by software It can only be cleared by a system reset 0 All SLB bits are accessible and can be modified 1 All SLB bits are write protected and ...

Page 748: ...ter what software is writing to 27 2 6 2 Change lock settings To change the setting whether an address is locked or unlocked the corresponding SLBRn SLBm bit needs to be changed This can be done using the following methods Modify the SLBRn SLBm bit directly by writing to area 4 Set the SLBRn SLBm bit s by writing to the mirror module space area 3 Both methods are explained in the following section...

Page 749: ...BRn WE 3 2 are cleared the lock bits SLBRn SLB 3 2 remain unchanged In the example on the left side of Figure 27 6 the data written to SLBRn SLB0 is mirrored to SLBRn SLB1 and the data written to SLBRn SLB2 is mirrored to SLBRn SLB3 as for both registers the write enables are set In Figure 27 7 a 32 bit wise protected register is shown When SLBRn WE0 is set the data written to SLBRn SLB0 is automa...

Page 750: ...pace area 3 It is possible to enable locking for a register after writing to it To do so the mirrored module address space must be used Figure 27 9 shows one example Figure 27 9 Enable locking via mirror module space area 3 When writing to address 0x0008 the registers MR9 and MR8 in the protected module are updated The corresponding lock bits remain unchanged left part of Figure 27 6 1 SLB0 SLB1 S...

Page 751: ... 2 Enable locking via mirror module space area 3 is only possible as long as the GCR HLB bit is cleared Once this bit is set the locking bits can no longer be modified until there was a system reset 27 2 6 3 Access errors The protection module generates transfer errors under several circumstances For the area definition refer to Figure 27 2 1 If accessing area 1 or area 3 the protection module wil...

Page 752: ...indow functionality When this functionality is programmed the servicing action should take place within the defined window When occurring outside the defined period the SWT will generate a reset 27 3 2 Features The SWT has the following features 32 bit time out register to set the time out period The unique SWT counter clock is the undivided low power internal oscillator IRC 16 MHz no other clock ...

Page 753: ...ent size are invalid Other types of invalid accesses include writes to read only registers incorrect values written to the service register when enabled accesses to reserved addresses and accesses by masters without permission If the RIA bit in the SWT_CR is set the SWT generates a system reset on an invalid access Otherwise a bus error is generated If either the HLK or SLK bits in the SWT_CR are ...

Page 754: ...8 29 30 31 R 0 0 0 0 0 0 KEY RIA WND ITR HLK SLK CSL STP FRZ WEN W Reset 0 0 0 0 0 0 0 1 0 0 0 1 1 0 1 1 Figure 27 11 SWT Control Register SWT_CR Table 27 6 SWT_CR field descriptions Field Description MAPn Master Access Protection for Master n The platform bus master assignments are device specific 0 Access for the master is disabled 1 Access for the master is enabled KEY Keyed Service Mode 0 Fixe...

Page 755: ...e 0 SWT counter continues to run in stop mode 1 SWT counter is stopped in stop mode FRZ Debug Mode Control Allows the watchdog timer to be stopped when the device enters debug mode 0 SWT counter continues to run in debug mode 1 SWT counter is stopped in debug mode WEN Watchdog Enabled 0 SWT is disabled 1 SWT is enabled Address Base 0x0004 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1...

Page 756: ...y if either the SWT_CR HLK or SWT_CR SLK bits are set Address Base 0x0008 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R WTO W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R WTO W Reset 1 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 Figure 27 13 SWT Time Out register SWT_TO Table 27 8 SWT_TO field descriptions Field Description WTO Watchdog time out period...

Page 757: ...r read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R WSC W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 27 15 SWT Service Register SWT_SR Table 27 10 SWT_SR field descriptions Field Description WSC Watchdog Service Code This field services the watchdog and clears the SWT_CR SLK...

Page 758: ...ue of this bit is 1 the watchdog starts operation automatically after reset is released Some devices can be configured to clear this bit automatically during the boot process Table 27 11 SWT_CO field descriptions Field Description CNT Watchdog Count When the watchdog is disabled SWT_CR WEN 0 this field shows the value of the internal down counter When the watchdog is enabled the value of this fiel...

Page 759: ...hronization logic in the SWT design recognition of the service sequence or configuration changes may require as many as 3 system plus 7 counter clock cycles If window mode is enabled SWT_CR WND bit is set the service sequence must be performed in the last part of the time out period defined by the window register The window is open when the down counter is less than the value in the SWT_WN registe...

Page 760: ...Chapter 27 Functional Safety MPC5602P Microcontroller Reference Manual Rev 4 760 Freescale Semiconductor ...

Page 761: ...logic for dormant fault detection can be performed under software control The FCU is developed to increase the level of safety of the system MCU level Functional safety features of the FCU include It is an independent module If other control modules are behaving abnormally the user can still trigger actions to prevent a critical situation Collection and external reporting of faults occurring on th...

Page 762: ...andling The FCU module and its state machine run on the system clock making the two modules synchronous The high speed RC clock 16 MHz is used only in the Alarm state in order to compute a deterministic timeout Input Unit Control Unit finite state machine Output Unit Destructive reset FCU 0 FCU 1 32 bit Fault sources IPBus 4 bit Clock Reset Power Mode state Fault Collection Unit SYS_CLK IRC_CLK Fu...

Page 763: ... state and communi cates fault to the external pin YES FCU goes into Alarm state and a timer is started FCTER Is the fault recovered in SW before timeout Fault flag can be cleared FFR If fault flag is cleared FCU returns NO to Normal state Is the fault recovered in HW before YES timeout SW recoverable fault YES Fault flag is cleared automatically FCU returns to Normal state HW recoverable fault NO...

Page 764: ...es of operation This section describes the basic functional modes of the FCU module 28 1 3 1 Normal mode In Normal operation the FCU captures all the faults in real time and processes them according to the fault type and the configuration set by the user 28 1 3 2 Test mode Test mode provides a testing mechanism of the FCU for dormant fault detection Test mode can be entered during the configuratio...

Page 765: ...page 771 0x0014 Key Register FCU_KR on page 772 0x0018 Timeout Register FCU_TR on page 773 0x001C Timeout Enable Register FCU_TER on page 773 0x0020 Module State Register FCU_MSR on page 774 0x0024 Microcontroller State Register FCU_MCSR on page 774 0x0028 Frozen MC State Register FCU_FMCSR on page 776 0x002C 0x3FFF Reserved Table 28 2 Register summary Name 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16...

Page 766: ... HRF 1 F HRF 0 W 0x0000_001 0 FCU_FER R ESF 0 ESF 1 ESF 2 ESF 3 ESF 4 0 0 0 0 0 0 0 0 0 0 0 W R EHF 15 EHF 14 EHF 13 EHF 12 EHF 11 EHF 10 EHF 9 EHF 8 EHF 7 EHF 6 EHF 5 EHF 4 EHF 3 EHF 2 EHF 1 EHF 0 W 0x0000_001 4 FCU_KR R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W 0x0000_001 8 FCU_TR R TR 31 16 W R TR 15 0 W 0x0000_001 C FCU_TER R TES F0 TES F1 TES F2 TES F3 TES F4 0 0 0...

Page 767: ...ending on the value of field TM 1 0 To exit from Test mode field TM must be written either 00 or 11 While exiting the Test mode the FCU must return to the Init state and automatically clear all the fault flags 0x0000_002 4 FCU_MCSR R 0 0 0 0 0 0 0 0 0 0 0 0 MCPS 3 0 W R 0 0 0 0 0 0 0 0 0 0 0 0 MCAS 3 0 W 0x0000_002 8 FCU_FMCS R R 0 0 0 0 0 0 0 0 0 0 0 0 FRMCPS 3 0 W R 0 0 0 0 0 0 0 0 0 0 0 0 FRMCA...

Page 768: ...ld description Field Description 0 MCL Module Configuration Lock 0 Configuration not locked FCU remains in Init state 1 Configuration locked FCU moves to Normal state 1 2 TM 1 0 Test Mode 00 Test Mode not entered 01 Test Mode entered fake faults can be generated output pins disabled 10 Test Mode entered fake faults can be generated output pins enabled 11 Test Mode not entered 22 23 PS 1 0 Polarity...

Page 769: ...ed field descriptions in Table 28 4 Table 28 5 provides the hardware software fault descriptions Address Base 0x0004 Access User read write Supervisor read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R SRF 0 SRF 1 SRF 2 SRF 3 SRF 4 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R HRF 15 HRF 14 HRF 13 HRF 12 HRF 11 HRF 10 HRF 9 HRF 8 HR...

Page 770: ...atchdog reset HRF9 JTAG JTAG reset TAP controller HRF10 PMU Comparators HRF11 PMU LVD 4 5 HRF12 PMU LVD 2 7 VREG HRF13 PMU LVD 2 7 FLASH HRF14 PMU LVD 2 7 I O HRF15 PMU LVD 1 2 digital SRF0 FCU FCU error SRF1 FCU Software triggered error SRF2 SRAM ECC multi bit error SRF3 Data Flash ECC multi bit error SRF4 Code Flash ECC multi bit error Address Base 0x0008 Access User read only 0 1 2 3 4 5 6 7 8 ...

Page 771: ...can be configured only during the Init phase before the configuration is locked Table 28 6 FCU_FFFR field descriptions Field Description 0 4 FRSRF0 FRSRF4 Software Recoverable Fault 0 No error latched 1 Error latched 16 31 FRHRF15 FRHRF0 Hardware Recoverable Fault 0 No error latched 1 Error latched Address Base 0x000C Access User read write Supervisor read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ...

Page 772: ... 15 EHF 14 EHF 13 EHF 12 EHF 11 EHF 10 EHF 9 EHF 8 EHF 7 EHF 6 EHF 5 EHF 4 EHF 3 EHF 2 EHF 1 EHF 0 W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 28 7 Fault Enable Register FCU_FER Table 28 8 FCU_FER field descriptions Field Description 0 4 ESF0 ESF4 Enable Software Recoverable Fault 0 FCU takes no action on Software recoverable Fault 0 4 1 FCU goes into Alarm Fault state on Software recoverable F...

Page 773: ...0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R TR 31 16 W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 28 9 Timeout Register FCU_TR Table 28 9 FCU_TR field descriptions Field Description 0 31 TR FCU Timeout 00000 Timeout is one clock 16 MHz cycle 00001 Timeout is one clock 16 MHz cycle 00002 Timeout is two clock 16 MHz cycles 00003 Timeout is three clock 16 MHz cycles De...

Page 774: ... 0 4 1 FCU goes into Alarm state on Software recoverable Fault 0 4 Note TESF1 not implemented or usable on this device 16 31 TEHF15 TEHF0 Timeout Enable for Hardware Recoverable Fault 0 FCU goes into Fault state on Hardware recoverable Fault 15 0 1 FCU goes into Alarm state on Hardware recoverable Fault 15 0 Address Base 0x0020 Access User read only Supervisor read only 0 1 2 3 4 5 6 7 8 9 10 11 1...

Page 775: ... W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Figure 28 12 MC State Register FCU_MCSR Table 28 12 FCU_MCSR field description Field Description 12 15 MCPS 3 0 MC Previous State 0000 RESET 0001 TEST 0010 SAFE 0011 DRUN 0100 RUN0 0101 RUN1 0110 RUN2 0111 RUN3 1000 HALT0 1001 Reserved 1010 STOP 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved 28 31 MCAS 3 0 MC Actual State 0000 RESET 0...

Page 776: ... 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 FRMCPS 3 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 FRMCAS 3 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 28 13 Frozen MC State Register FCU_FMCSR Table 28 13 FCU_FMCSR field description Field Description 12 15 FRMCPS 3 0 MC Previous State 0000 RESET 0001 TE...

Page 777: ...4 Functional block diagram 28 31 FRMCAS 3 0 MC Actual State 0000 RESET 0001 TEST 0010 SAFE 0011 DRUN 0100 RUN0 0101 RUN1 0110 RUN2 0111 RUN3 1000 HALT0 1001 Reserved 1010 STOP 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved Table 28 13 FCU_FMCSR field description Field Description FCU Output Prescaler Timeout Counter Output Generation FCU Control Mapped Modules Registers Logi...

Page 778: ...R the FCU goes into Normal state Then when a fault occurs the FCU can move into Alarm Fault states depending on the Fault Enable Register FCU_FER The Fault Flag Register FCU_FFR stores any fault that has occurred even if the FCU is not entering into the Alarm or the Fault state When the FCU is in Alarm state a timer starts counting up to a fixed timeout see Section 28 2 3 7 Timeout Register FCU_TR...

Page 779: ...arity of the first signal the MSB sets the polarity of the second signal 28 3 2 1 Dual rail protocol Dual rail encoding is an alternate method for encoding bits In contrast to classical encoding where each wire carries a single bit value dual rail encoded circuits use two wires to carry each bit Table 28 14 summarizes the encoding As long as the FCU is in Normal or Alarm state the output shows a n...

Page 780: ...ycle d 50 Eqn 28 1 Frequency can be varied by using the same prescaler as used for the dual rail protocol FOP field in FCU_MCR This frequency modulation protocol is violated when the FCU goes into Fault state During initialization phase FCU 0 is set high When a fault is detected FCU 0 is set low Reset Configuration phase Normal behavior Error occurred FCU 0 FCU 1 During configuration phase fake fa...

Page 781: ... is indicated Table 28 15 shows bi stable encoding for FCU 0 Figure 28 18 Bi stable coding example Table 28 15 Bi stable coding Logical value Bi stable encoding faulty 0 non faulty 1 Reset Configuration phase Normal behavior Error occurred FCU 0 During configuration phase fake faults can be injected so output may be different Reset is asserted Reset Configuration phase Normal behavior Fault occurr...

Page 782: ...Chapter 28 Fault Collection Unit FCU MPC5602P Microcontroller Reference Manual Rev 4 782 Freescale Semiconductor ...

Page 783: ...e that the Wake up pins are enabled in ALL modes therefore the Wake up pins should be correctly terminated to ensure minimal current consumption Any unused Wake up signal input should be terminated by using an external pull up or pull down or by internal pull up enabled at WKUP_WIPUER Also care has to be taken on packages where the Wake up signal inputs are not bonded For these packages the user m...

Page 784: ...0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 29 1 NMI Status Flag Register NSR Table 29 2 NSR field descriptions Field Description 0 NIF NMI Status Flag This flag can be cleared only by writing a 1 Writing a 0 has no effect If enabled NCR NREE or NCR NFEE is set NIF causes an interrupt request 0 No event has occurred on the pad 1 An event as defined by NRRC NREE or NCR NFEE has occ...

Page 785: ...8 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 29 2 NMI Configuration Register NCR Table 29 3 NCR field descriptions Field Description 0 NLOCK NMI Configuration Lock Register Writing a 1 to this bit locks the configuration for the NMI until it is unlocked by a system reset Writing a 0 has no effect 1 2 NDSS NMI Destination Source Select 00 Non maskable ...

Page 786: ...ng an NMI event Each NMI passes through a bypassable analog glitch filter NOTE Glitch filter control and pad configuration should be done while the NMI is disabled in order to avoid erroneous triggering by glitches caused by the configuration process itself Figure 29 3 NMI pad diagram 29 5 2 1 NMI management The NMI can be enabled or disabled using the single NCR register laid out to contain all c...

Page 787: ...led the pad cannot be reconfigured in the IOMUX to override or disable the NMI The NMI destination interrupt is controlled by the user through the configuration of the NDSS bits See Table 29 3 for details An NMI supports a status flag and an overrun flag which are located in the NSR register see Figure 29 1 This register is a clear by write 1 register type preventing inadvertent overwriting of oth...

Page 788: ...Chapter 29 Wakeup Unit WKPU MPC5602P Microcontroller Reference Manual Rev 4 788 Freescale Semiconductor ...

Page 789: ...ring general purpose interrupts and system wakeup Figure 30 1 shows the PIT block diagram Figure 30 1 PIT block diagram 30 1 1 Overview This chapter describes the function of the Periodic Interrupt Timer block PIT The PIT is an array of four timers that can be used to raise interrupts and trigger DMA channels 30 1 2 Features The main features of this block are Timer 0 Timer 3 Timer 1 PIT Registers...

Page 790: ...30 1 PIT memory map Offset from PIT_BASE 0xC3FF_0000 Register Location 0x0000 PITMCR PIT Module Control Register on page 791 0x0004 0x00FF Reserved Timer Channel 0 0x0100 LDVAL0 Timer 0 Load Value Register on page 792 0x0104 CVAL0 Timer 0 Current Value Register on page 792 0x0108 TCTRL0 Timer 0 Control Register on page 793 0x010C TFLG0 Timer 0 Flag Register on page 794 Timer Channel 1 0x0110 LDVAL...

Page 791: ...and whether the timers run in debug mode Timer Channel 3 0x0130 LDVAL3 Timer 3 Load Value Register on page 792 0x0134 CVAL3 Timer 3 Current Value Register on page 792 0x0138 TCTRL3 Timer 3 Control Register on page 793 0x013C TFLG3 Timer 3 Flag Register on page 794 0x0140 0x3FFF Reserved Address Base 0x0000 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 792: ...E 0x0110 LDVAL2 PIT_BASE 0x0120 LDVAL3 PIT_BASE 0x0130 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R TSV 31 TSV 30 TSV 29 TSV 28 TSV 27 TSV 26 TSV 25 TSV 24 TSV 23 TSV 22 TSV 21 TSV 20 TSV 19 TSV 18 TSV 17 TSV 16 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R TSV 15 TSV 14 TSV 13 TSV 12 TSV 11 TSV 10 TSV 9 TSV 8 TSV7 TSV6 TSV5 TSV4 TSV3 T...

Page 793: ...VL6 TVL5 TVL4 TVL3 TVL2 TVL1 TVL0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 30 4 Current Timer Value register n CVALn Table 30 4 CVALn field descriptions Field Description TVLn Current Timer Value These bits represent the current timer value Note that the timer uses a downcounter NOTE The timer values will be frozen in Debug mode if the FRZ bit is set in the PIT Module Control Register see Fi...

Page 794: ...terrupt will immediately cause an interrupt event To avoid this the associated TIF flag must be cleared first TEN Timer Enable Bit 0 Timer will be disabled 1 Timer will be active Address Channel Base 0x000C TFLG0 PIT_BASE 0x010C TFLG1 PIT_BASE 0x011C TFLG2 PIT_BASE 0x012C TFLG3 PIT_BASE 0x013C Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 ...

Page 795: ...t counter value of the timer can be read via the CVAL registers The counter period can be restarted by first disabling then enabling the timer with the TEN bit see Figure 30 7 The counter period of a running timer can be modified by first disabling the timer setting a new load value and then enabling the timer again see Figure 30 8 It is also possible to change the counter period without restartin...

Page 796: ... writing a 1 to that TIF bit 30 5 Initialization and application information 30 5 1 Example configuration In the example configuration The PIT clock has a frequency of 50 MHz Timer 1 creates an interrupt every 5 12 ms Timer 3 creates a trigger event every 30 ms First the PIT module needs to be activated by writing a 0 to the MDIS bit in the PITMCR The 50 MHz clock frequency equates to a clock peri...

Page 797: ...s at 0 The following example code matches the described setup turn on PIT PIT_CTRL 0x00 RTI PIT_RTI_LDVAL 0x004C4B3F setup RTI for 5000000 cycles PIT_RTI_TCTRL PIT_TIE let RTI generate interrupts PIT_RTI_TCTRL PIT_TEN start RTI Timer 1 PIT_LDVAL1 0x0003E7FF setup timer 1 for 256000 cycles PIT_TCTRL1 TIE enable Timer 1 interrupts PIT_TCTRL1 TEN start timer 1 Timer 3 PIT_LDVAL3 0x0016E35F setup time...

Page 798: ...Chapter 30 Periodic Interrupt Timer PIT MPC5602P Microcontroller Reference Manual Rev 4 798 Freescale Semiconductor ...

Page 799: ...an be stopped in debug mode 31 3 Modes of operation The STM supports two device modes of operation normal and debug When the STM is enabled in normal mode its counter runs continuously In debug mode operation of the counter is controlled by the FRZ bit in the STM_CR If the FRZ bit is set the counter is stopped in debug mode otherwise it continues to run 31 4 External signal description The STM doe...

Page 800: ...TM Channel 0 Control Register on page 802 0x0014 STM_CIR0 STM Channel 0 Interrupt Register on page 802 0x0018 STM_CMP0 STM Channel 0 Compare Register on page 803 0x001C Reserved 0x00200 STM_CCR1 STM Channel 1 Control Register on page 802 0x00244 STM_CIR1 STM Channel 1 Interrupt Register on page 802 0x00288 STM_CMP1 STM Channel 1 Compare Register on page 803 0x002C Reserved 0x0030 STM_CCR2 STM Chan...

Page 801: ...ble 31 2 STM_CR field descriptions Field Description CPS 7 0 Counter Prescaler Selects the clock divide value for the prescaler 1 256 0x00 Divide system clock by 1 0x01 Divide system clock by 2 0xFF Divide system clock by 256 FRZ Freeze Allows the timer counter to be stopped when the device enters debug mode 0 STM counter continues to run in debug mode 1 STM counter is stopped in debug mode TEN Ti...

Page 802: ...1 Base 0x0030 STM_CCR2 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 31 3 STM Channel Control Register STM_CCRn Table 31 4 STM_CCRn field descriptions Field Description CEN Channel...

Page 803: ...request 1 Interrupt request due to a match on the channel Address Base 0x0018 STM_CMP0 Base 0x0028 STM_CMP1 Base 0x0038 STM_CMP2 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R CMP W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R CMP W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 31 5 STM Channel Compare Register STM_CMPn Table 31 6 STM_CMPn ...

Page 804: ...th the STM_CR TEN bit When enabled in normal mode the counter continuously increments When enabled in debug mode the counter operation is controlled by the STM_CR FRZ bit When the STM_CR FRZ bit is set the counter is stopped in debug mode otherwise it continues to run in debug mode The counter rolls over at 0xFFFF_FFFF to 0x0000_0000 with no restrictions at this boundary The STM has four identical...

Page 805: ...two hard wired polynomials normally used for most of the standard communication protocols The data stream supports multiple data width byte half word word formats 32 1 1 Glossary CRC cyclic redundancy check CPU central processing unit DMA direct memory access CCITT ITU T for Telecommunication Standardization Sector of the International Telecommunications Union SW software WS wait state SPI serial ...

Page 806: ...dule are accessible read write in each access mode user supervisor or test In terms of bus performance of the operations following the summary 0 WS single bus cycle for each write read operations to the CRC_CFG and CRC_INP registers 0 WS single bus cycle for each write operation to the CRC_ CSTAT register Double WS 3 bus cycles for each read operation to the CRC_ CSTAT or CRC_OUTP registers immedi...

Page 807: ...or the CRC CCITT The design implementation executes the CRC computation in a single clock cycle parallel data loading A pipeline scheme has been adopted to de couple the IPS bus interface from the CRC engine in order to allow the computation of the CRC at speed zero wait states In case of usage of the CRC signature for encapsulation in the data frame of a communication protocol e g SPI a bit swap ...

Page 808: ...ge 809 0x0004 CRC_INP CRC Input Register Context 1 on page 810 0x0008 CRC_CSTAT CRC Current Status Register Context 1 on page 810 0x000C CRC_OUTP CRC Output Register Context 1 on page 811 0x0010 CRC_CFG CRC Configuration Register Context 2 on page 809 CRC configuration polynomial swap inversion setting the CRC_CFG register CRC seed initialization CRC_CSTAT register Data is written in the CRC_INP r...

Page 809: ...rved bits These bits are always read as 0 and must always be written with 0 29 POLYG Polynomial selection 0 CRC CCITT polynomial 1 CRC 32 polynomial This bit can be read and written by the software This bit can be written only during the configuration phase 30 SWAP SWAP selection 0 No swap selection applied on the CRC_OUTP content 1 Swap selection MSB LSB LSB MSB applied on the CRC_OUTP content In...

Page 810: ...gure 32 5 CRC Input Register CRC_INP Table 32 3 CRC_INP field descriptions Field Description 0 31 INP Input data for the CRC computation The INP register can be written at byte half word high and low or word in any sequence In case of half word write operation the bytes must be contiguous This register can be read and written by the software Address Context 1 Base 0x0008 Context 2 Base 0x0018 Acce...

Page 811: ...the CRC signature No bit swap and inversion are applied to this register In case of CRC CCITT polynomial only the16 LSB bits are significant The 16 MSB bits are tied at 0b during the computation The CSTAT register can be written at byte half word or word This register can be read and written by the software This register can be written only during the configuration phase Address Context 1 Base 0x0...

Page 812: ... be applied to manage the transmission data flow DMA CRC module configuration context x channel x by CPU Payload transfer from the MEM to the CRC module CRC_INP register to calculate the CRC signature phase1 by DMA mem2mem data transfer channel x CRC signature copy from the CRC module CRC_OUTP register to the MEM phase 2 by CPU Data block payload CRC transfer from the MEM to the PERIPH module e g ...

Page 813: ...iven in Figure 32 9 shall be applied to manage the reception data flow DMA CRC module configuration context x channel x by CPU CRC_OUTP CRC_INP Memory CRC context x CPU Transmission Phase 2 CRC_OUTP CRC_INP Memory CRC context x DMA Transmission Phase 1 CRC Checksum Tx FIFO Memory SPI DMA Transmission Phase 3 CRC Checksum Payload mem2mem channel x mem2periph channel x Payload Payload ...

Page 814: ...fer from the PERIPH e g SPI Rx fifo module to the MEM phase 1 by DMA periph2mem data transfer channel x Data block transfer payload CRC transfer from the MEM to the CRC module CRC_INP register to calculate the CRC signature phase 2 by DMA mem2mem data transfer channel x CRC signature check from the CRC module CRC_OUTP register by CPU phase 3 1 ...

Page 815: ...ctor 815 Figure 32 9 DMA CRC Reception Sequence CRC_OUTP CRC_INP Memory CRC context x DMA CRC Checksum Rx FIFO Memory SPI DMA Reception Phase 1 CRC Checksum Received Data Reception Phase 2 CRC_OUTP CRC_INP CRC context x Reception Phase 3 Software Check Payload Payload mem2mem channel x periph2mem channel x ...

Page 816: ...Chapter 32 Cyclic Redundancy Check CRC MPC5602P Microcontroller Reference Manual Rev 4 816 Freescale Semiconductor ...

Page 817: ...RAM Censorship protection for internal flash module 33 3 Boot modes The MPC5602P device supports the following boot modes Single Chip SC The device boots from the first bootable section of the Flash main array Serial Boot SBL The device downloads boot code from either LINFlex or FlexCAN interface and then execute it If booting is not possible with the selected configuration e g if no Boot ID is fo...

Page 818: ...set sequence The type of alternate boot mode is selected according to the ABS Alternate Boot Selector pins see Table 33 2 If FAB is not asserted the device boots from the lowest Flash sector that contains a valid boot signature If no Flash sector contains a valid boot signature the device will go into static mode Figure 33 1 Boot mode selection Boot configuration pins are FABM 1 Flash Boot ID ABS ...

Page 819: ...re described in the Table 33 3 for 64 pin and 100 pin LQFP packages Table 33 2 Hardware configuration to select boot mode FAB ABS 1 0 1 1 During reset the boot configuration pins are weak pull down Standby RAM Boot Flag Boot ID Boot Mode 1 00 0 LINFlex without autobaud 1 01 0 FlexCAN without autobaud 1 10 0 Autobaud scan Table 33 3 MPC5602P boot pins Port pin Function Pin 64 pin 100 pin A 2 1 1 We...

Page 820: ...2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 VLE BOOT_ID 0 7 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 33 2 Reset Configuration Half Word RCHW Table 33 4 RCHW field descriptions Field Description 0 6 Reserved 7 VLE VLE Indicator This bit configures the MMU for the boot block to execute as either Power Architecture techmology code or as Freescale VLE code 0 Boot code executes as Power Arc...

Page 821: ... is the address where the startup code is located reset boot vector Then the device executes this startup code A user application should have a valid instruction at the reset boot vector address Table 33 5 Flash boot sector Block Address 0 0x0000_0000 1 0x0000_8000 2 0x0000_C000 3 0x0001_0000 4 0x0001_8000 32K Boot information 16K 16K 32K 0x0000 0000 0x0000 8000 0x0000 C000 0x0001 0000 0x0002 0000...

Page 822: ...tor does not need to be consecutive to the main boot sector This ensures that even if one boot sector is erased still there will always be another active boot sector Sector shall be activated i e program a valid BOOT_ID instead of 0xFF as initially programmed Sector shall be deactivated writing to 0 some of the bits BOOT_ID bit field bit1 and or bit3 and or bit4 and or bit6 33 5 5 Boot through BAM...

Page 823: ...SSCM_STATUS register see Section 10 2 2 1 System Status register STATUS indicate which boot has to be executed see Table 33 6 If the BMODE field shows either a single chip value 011 or a reserved value the boot mode is not considered valid and the BAM pushes the device into static mode In all other cases the code of the relative boot is called Data is downloaded and saved into proper SRAM location...

Page 824: ...word check see Table 33 6 and Figure 33 5 External oscillator The following hardware resources are used only when autobaud feature is selected STM to measure the baud rate CMU to measure the external clock frequency related to the internal RC clock source FMPLL to work with system clock near the maximum allowed frequency this to have higher resolution during baud rate measurement As already mentio...

Page 825: ...llowed by the MCU transmission 1 Host sends data to MCU and start waiting 2 MCU echoes to host the data received 3 MCU verifies if echo is correct If data is correct the host can continue to send data If data is not correct the host stops transmitting and the MCU needs to be reset All multi byte data structures are sent MSB first A more detailed description of these steps follows 33 5 5 5 Download...

Page 826: ...owed user password configured in the NVPWD0 and NVPWD1 registers the user must set the swapped password NVPWD1 and NVPWD0 to access the device refer to following examples Example 33 1 In devices with flash secured registers are programmed NVPWD0 0x87654321 NVPWD1 0x12345678 NVSCI0 0x55AA1111 NVSCI1 0x55AA1111 To download the code via SLB the provided password is 0x1234_5678_8765_4321 swapped WITH ...

Page 827: ...the code has been compiled This device family supports only VLE 1 The bit is used for backward compatibility The Start Address defines where the received data will be stored and where the MCU will branch after the download is finished The two LSB bits of the Start Address are ignored by the BAM program such that the loaded code should be 32 bit word aligned The Length defines how many data bytes h...

Page 828: ...avoid ECC error during core prefetch 33 5 5 8 Execute code The BAM program waits for the last echo message transmission being completed Then it restores the initial MCU configuration and jumps to the loaded code at Start Address that was received in step 3 of the protocol At this point BAM has finished its tasks and MCU is controlled by new code executing from SRAM 33 5 6 Boot from UART autobaud d...

Page 829: ...N 2 0A specification FlexCAN controller bit timing is programmed with 10 time quanta and the sample point is 2 time quanta before the end as shown in Figure 33 8 Table 33 8 UART boot mode download protocol autobaud disabled Protoco l step Host sent message BAM response message Action 1 64 bit password MSB first 64 bit password Password checked for validity and compared against stored password 2 32...

Page 830: ... Password checked for validity and compared against stored password 2 FlexCAN ID 0x012 32 bit store address VLE bit 31 bit number of bytes FlexCAN ID 0x002 32 bit store address VLE bit 31 bit number of bytes Load address is stored for future use Size of download is stored for future use Verify if VLE bit is set to 1 3 FlexCAN ID 0x013 8 to 64 bits of raw binary data FlexCAN ID 0x003 8 to 64 bits o...

Page 831: ...urement itself is performed by software polling the related inputs as general purpose IO s resulting in a detection granularity that is directly related to the execution speed of the software One main difference of the autobaud feature is that the system clock is not driven directly by the external oscillator but it is driven by the FMPLL output The reason is that to have an optimum resolution for...

Page 832: ...t starts and then sets up the FlexCAN baud rate accordingly when UART RX corresponds to pin B 3 on LQFP100 or B 7 on LQFP64 level is low the UART autobaud measurement starts and then sets up the LINFlex baud rate accordingly After performing the autobaud measurement and setting up the baud rate the corresponding RX input is reconfigured and the related standard download process is started in case ...

Page 833: ...from falling edge and rising edge The baud rate can be calculated from this time Figure 33 10 Baud measurement on UART boot FlexCAN RX and LINFlex RX configured as GPIO inputs FlexCAN RX 1 FlexCAN RX 0 LINFlex RX 0 CAN Autobaud Set matching baud rate for FlexCAN Autobaud measurement Continue with FlexCAN LINFlex Autobaud Set matching baud rate for LINFlex Autobaud measurement download Continue wit...

Page 834: ...configured to work in UART mode with the calculated baud rate Then an acknowledge byte 0x59 ASCII char Y is sent From this point the BAM follows the normal UART mode boot protocol see Figure 33 11 Figure 33 11 BAM rate measurement flow during UART boot Start UART_RX 0 NO NO YES YES UART_RX configured as GPIO input Stop STM Read elapsed time Calculate baud rate Baud rate configuration UART_RX 1 Fol...

Page 835: ...eption of next high bit Error introduced due to polling will be small typically 6 cycles The following equation gives the relation between baud rate and LINFlex register configuration Eqn 33 1 LDIV is an unsigned fixed point number and its mantissa is coded into 13 bits of the LINFlex s register LINIBRR From this equation and considering that a single UART transmission contains 9 bits it is possib...

Page 836: ... bits the time base will measure 9 4e6 250e3 144 cycles Thus LINIBB is set to 144 144 1 This results in a baud rate of exactly 250 kBd However a slower 225 kBd signal operating with 4 MHz XTAL would again result in LINIBB 1 but this time with an 11 1 deviation Table 33 11 Maximum and minimum recommended baud rates fsys fxtal MHz Max baud rate for guaranteed 2 5 deviation Min baud rate for guarante...

Page 837: ...th Code DLC 0x0 As all the bits to be transmitted are dominant bits there is a succession of 5 dominant bits and 1 stuff bit on the FlexCAN network see Figure 33 13 From the duration of this frame the MCU calculates the corresponding baud rate factor with respect to the current CPU clock and initializes the FlexCAN interface accordingly Figure 33 13 Bit time measure In FlexCAN boot mode the FlexCA...

Page 838: ...e Calculate baud rate Baud rate configuration These steps are executed 4 times to work with FlexCAN module CAN_RX pin is configured FlexCAN is configured with calculated baud is enabled on the network There is a glitch if measured time CAN_GLITCH_WIDTH Read STM measured time STM value CAN_RX 1 CAN_RX 0 Glitch CAN_0_RX pin configured as GPIO input YES NO NO YES Start STM If CAN is connected CAN_RX ...

Page 839: ...e time quantum TSEG1 PROGPSEG PSEG1 2 TSEG2 PSEG2 1 Time base result 29 Presdiv 1 SYNCSEG TSEG1 TSEG2 FlexCAN protocol specifies that the FlexCAN bit timing should comprise a minimum of 8 time quanta and a maximum of 25 time quanta Therefore the available range is 8 1 TSEG1 TESG2 25 For 29 bit times the possible range in which the result in the time base may lie accounting for PRESDIV is 232 1 PRE...

Page 840: ...imings Desired number of Time quanta DTq Time Segment 2 Time segment 1 PSEG2 1 PSEG1 1 PROPSEG 1 8 to 131 1 PRESDIV 1 1 2 2 DTq 5 8 to 132 2 PRESDIV 1 1 to accommodate information processing time IPT of 3 tq Note All TSEG1 and TSEG2 times have been chosen to preserve a sample time between 70 and 85 of the bit time 3 2 DTq 6 14 to 15 3 3 DTq 6 16 to 17 4 4 DTq 7 18 to 19 5 5 DTq 8 20 to 21 6 6 DTq ...

Page 841: ...ESDIV 232 725 PRESDIV 0 To calculate time quanta requirement Time base result 29 Presdiv 1 SYNCSEG TSEG1 TSEG2 232 29 1 1 TSEG1 TSEG2 1 TSEG1 TSEG2 8 From the lookup table CANA_CR 0x004A_2001 This give a baud rate of X This give 0 error Table 33 16 PRESDIV 1 1 YY PRESDIV Desired number of time quanta Register contents for CANA_CR 8 0xYY49_2002 9 0xYY49_2003 10 0xYY49_2004 11 0xYY49_2005 12 0xYY49_...

Page 842: ...rotect the contents of the flash memory from being read or modified In order to achieve this the censorship mechanism controls access to the JTAG Nexus debug interface Serial boot mode which could otherwise be used to download and execute code to query or modify the flash memory To re gain access to the flash memory via JTAG or serial boot a 64 bit password must be correctly entered CAUTION When c...

Page 843: ...shown below which disables censorship NVSCI0 0x55AA_55AA NVSCI1 0x55AA_55AA Each 32 bit register is split into an upper and lower 16 bit field The upper 16 bits the SC field are used to control serial boot mode censorship The lower 16 bits the CW field are used to control flash memory boot censorship CAUTION If the contents of the shadow flash memory are erased and the NVSCI0 1 registers are not r...

Page 844: ...no way to get back in Table 33 18 shows all the possible modes of censorship The red shaded areas are to be avoided as these show the configuration for a device that is permanently locked out If you wish to enable censorship with a private password there is only one valid configuration to modify the CW field in both NVSCI0 1 registers so they match but do not equal 0x55AA This will allow you to en...

Page 845: ...VSCI0 NVSCI1 Enabled Enabled N A Private flash memory password and censored 0x55AA AND NVSCI0 NVSCI1 0x55AA AND NVSCI0 NVSCI1 Enabled Enabled with password NVPWD1 0 SSCM reads flash memory1 1 When the SSCM reads the passwords from flash memory the NVPWD0 and NVPWD1 password order is swapped so you have to submit the 64 bit password as NVPWD1 NVPWD0 Censored with no password access lockout 0x55AA 0...

Page 846: ...emory boot mode FAB 0 Flash boot mode NVSCI0 NVSCI1 True Censored with no password access Locked out JTAG password details Enter password as NVPWD1 NVPWD0 False False False Both SC and CW 0x55AA CW 0x55AA True Censored with no password access Locked out True Censored with private password over JTAG Uncensored example 0x89ABCDEF_01234567 Note SC 0x55AA ...

Page 847: ...ked out Serial password details Enter public password 0xFEEDFACE_CAFEBEEF False False False Both SC and CW 0x55AA SC 0x55AA True Censored with no password access Locked out True Note CW 0x55AA False CW 0x55AA True Note SC 0x55AA Public password Uncensored Flash private password Censored Flash private password Uncensored Enter password as NVPWD1 NVPWD0 example 0x89ABCDEF_01234567 Enter password as ...

Page 848: ...Chapter 33 Boot Assist Module BAM MPC5602P Microcontroller Reference Manual Rev 4 848 Freescale Semiconductor ...

Page 849: ...upply to a 1 2 V digital supply The nominal target output is 1 28 V Due to all variations the actual output will be in range of 1 08 V to 1 32 V in the full current load range 0 250 mA after trimming The stabilization for HPREG is achieved using an external capacitance The minimum recommended value is 3 10 µF with low ESR refer to datasheet for details NOTE In general an offset voltage must be avo...

Page 850: ...t 5V_LVD_MASK in the VREG_CTL register POR is required to initialize the device during supply rise POR works only on the rising edge of main supply To ensure its functioning during the following rising edge of the supply it is reset by the output of the LVD_MAIN block when main supply reaches below the lower voltage threshold of the LVD_MAIN POR is asserted on power up when VDD supply is above VPO...

Page 851: ...0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 5V_LVD _MASK W Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 Figure 34 1 Voltage Regulator Control register VREG_CTL Table 34 1 VREG_CTL field descriptions Field Description 5V_LVD_MASK Mask bit for 5 V LVD from regulator This is a read write bit and must be unmasked by writing...

Page 852: ... provided to connect the low voltage power supply Refer to the device datasheet for details The three dedicated supply domains are further divided within the package in order to reduce EMI and noise as much as possible HV_REG High voltage regulator supply HV_IOn High voltage PAD supply HV_OSC1 High voltage external oscillator and regulator supply HV_AD0 High voltage supply and reference for ADC mo...

Page 853: ...ulators and Power Supplies MPC5602P Microcontroller Reference Manual Rev 4 Freescale Semiconductor 853 LV_CORn Low voltage supply for the core It is also used to provide supply for PLL and Flsah memory through double bonding ...

Page 854: ...Chapter 34 Voltage Regulators and Power Supplies MPC5602P Microcontroller Reference Manual Rev 4 854 Freescale Semiconductor ...

Page 855: ... 35 1 is a block diagram of the JTAG Controller JTAGC Figure 35 1 JTAG controller block diagram 35 3 Overview The JTAGC provides the means to test device functionality and connectivity while remaining transparent to system logic when not in test mode Testing is performed via a boundary scan technique as defined in the IEEE 1149 1 2001 standard In addition instructions can be executed that allow th...

Page 856: ...sults in asynchronous entry into the reset state While in reset the following actions occur The TAP controller is forced into the test logic reset state thereby disabling the test logic and allowing normal operation of the on chip system logic to continue unhindered The instruction register is loaded with the IDCODE instruction In addition execution of certain instructions can result in assertion ...

Page 857: ...regains control of the JTAG port during the UPDATE DR state if the PAUSE DR state was entered Auxiliary TAP controllers are held in RUN TEST IDLE while they are inactive For more information on the TAP controllers refer to Chapter 36 Nexus Development Interface NDI 35 6 External signal description The JTAGC consists of four signals that connect to off chip development tools and allow access to tes...

Page 858: ...Bypass register The bypass register is a single bit shift register path selected for serial data transfer between TDI and TDO when the BYPASS CLAMP HIGHZ or reserve instructions are active After entry into the capture DR state the single bit shift register is set to a logic 0 Therefore the first bit shifted out after selecting the bypass register is always a logic 0 35 7 3 Device identification re...

Page 859: ... The JTAGC uses the IEEE 1149 1 2001 Test Access Port TAP for accessing registers This port can be shared with other TAP controllers on the MCU For more detail on TAP sharing via JTAGC instructions refer to Section 35 8 4 2 ACCESS_AUX_TAP_x instructions Data is shifted between TDI and TDO though the selected register starting with the least significant bit as illustrated in Figure 35 4 This applie...

Page 860: ...ous state machine that interprets the sequence of logical values on the TMS pin Figure 35 5 shows the machine s states The value shown next to each state is the value of the TMS signal sampled on the rising edge of the TCK signal As Figure 35 5 shows holding TMS at logic 1 while clocking TCK through a sufficient number of rising edges also causes the state machine to enter the test logic reset sta...

Page 861: ...state machine Test logic reset Run test idle Select DR scan Select IR scan Capture DR Capture IR Shift DR Shift IR Exit1 DR Exit1 IR Pause DR Pause IR Exit2 DR Exit2 IR Update DR Update IR 1 0 1 1 1 0 0 0 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 NOTE The value shown adjacent to each state transition in this figure represents the value of TMS at the time of a rising edge of TCK ...

Page 862: ...uctions listed in Table 35 3 Table 35 3 JTAG instructions Instruction Code 4 0 Instruction summary IDCODE 00001 Selects device identification register for shift SAMPLE PRELOAD 00010 Selects boundary scan register for shifting sampling and preloading without disturbing functional operation SAMPLE 00011 Selects boundary scan register for shifting and sampling without disturbing functional operation ...

Page 863: ...P instruction CLAMP allows the state of signals driven from MCU pins to be determined from the boundary scan register while the bypass register is selected as the serial path between TDI and TDO CLAMP enhances test efficiency by reducing the overall shift path to a single bit the bypass register while conducting an EXTEST type of instruction through the boundary scan register CLAMP also asserts th...

Page 864: ... of the instruction samples the system data and control signals on the MCU input pins and just before the boundary scan register cells at the output pins This sampling occurs on the rising edge of TCK in the capture DR state when the SAMPLE PRELOAD instruction is active The sampled data is viewed by shifting it through the boundary scan register to the TDO output during the shift DR state Both the...

Page 865: ...ws 35 9 2 1 Enabling the TAP controller To access the e200z0 OnCE controller the proper JTAGC instruction needs to be loaded in the JTAGC instruction register as discussed in Section 35 5 2 2 TAP sharing mode The e200z0 OnCE TAP controller may either be accessed independently or chained with the e200z1 OnCE TAP controller such that the TDO output of the e200z1 TAP controller is fed into the TDI in...

Page 866: ...rce is accessed in the DR scan sequence of the TAP controller and as such the update DR state must be transitioned through in order for an access to occur In addition the update DR state must also be transitioned through in order for the single step and or exit functionality to be performed even though the command appears to have no data resource requirement associated with it 0 1 2 3 4 5 6 7 8 9 ...

Page 867: ...d 1 Place the JTAGC in reset through TAP controller state machine transitions controlled by TMS 2 Load the appropriate instruction for the test or action to be performed 010 0111 Data Value Compare 2 DVC2 010 1000 010 1111 Reserved 011 0000 Debug Status Register DBSR 011 0001 Debug Control Register 0 DBCR0 011 0010 Debug Control Register 1 DBCR1 011 0011 Debug Control Register 2 DBCR2 011 0100 101...

Page 868: ...Chapter 35 IEEE 1149 1 Test Access Port Controller JTAGC MPC5602P Microcontroller Reference Manual Rev 4 868 Freescale Semiconductor ...

Page 869: ...veral individual Nexus blocks that are selected to provide the development support interface for MPC5602P The NDI block interfaces to the e200z0 and internal buses to provide development support as per the IEEE ISTO 5001 2003 standard The development support provided includes the MCU s internal memory map and access to the e200z0 internal registers via the JTAG port 36 2 Information specific to th...

Page 870: ...eatures The NDI module of the MPC5602P is compliant with Class 1 of the IEEE ISTO 5001 2003 standard The following features are implemented 4 pin JTAG port TDI TDO TMS and TCK All features controllable and configurable via the JTAG port All features are independently configurable and controllable via the IEEE 1149 1 I O port Support for internal censorship mode to prevent external access to flash ...

Page 871: ...tput buffer is disabled if the NDI has control of the TAP The TDI TMS and TCK inputs are ignored The NDI block indicates to the MCU that it is not using the auxiliary output port This indication can be used to tristate the output pins or use them for another function 36 5 2 NDI modes 36 5 2 1 Censored mode The NDI supports internal flash censorship mode by preventing the transmission of trace mess...

Page 872: ...n supervisor mode Multiple exception conditions can map to a single interrupt vector and may be distinguished by examining registers associated with the interrupt The Exception Syndrome register ESR is updated with information specific to the exception type when an interrupt occurs To prevent loss of state information interrupt handlers must save the information stored in the machine state save re...

Page 873: ...data breakpoints and program single stepping The debug facilities consist of a set of debug control registers DBCR0 2 DBCR4 DBERC0 a set of address compare registers IAC1 IAC2 IAC3 IAC4 DAC1 and DAC2 a set of data value compare registers DVC1 DVC2 a Debug Status Register DBSR for enabling and recording various kinds of debug events and a special Debug interrupt type built into the interrupt mechan...

Page 874: ...R0EDM Setting DBCR0EDM overrides the Internal Debug Mode enable bit DBCR0IDM unless resources are provided back to software via the settings in DBERC0 When the Hardware Debug facility is enabled software is blocked from modifying the hardware owned debug facilities In addition since resources are owned by the hardware debugger inconsistent values may be present if software attempts to read hardwar...

Page 875: ...ers as appropriate when hardware modifications to the debug registers is performed 36 9 4 1 Simultaneous Hardware and Software Debug Event Handing Since it is possible that a hardware owned resource can produce a debug event in conjunction with a software owned resource producing a different debug event simultaneously a priority ordering mechanism is implemented which guarantees that the hardware ...

Page 876: ...rule it is always enabled Once a Debug Status Register DBSR bit is set corresponding to a debug resource which is owned by software other than MRR if Debug interrupts are enabled by MSRDE a Debug interrupt will be generated The debug interrupt handler is responsible for ensuring that multiple repeated debug interrupts do not occur by clearing the DBSR as appropriate Certain debug events are not al...

Page 877: ...en debug events 5 Instruction Complete debug events 6 Interrupt Taken debug events 7 Return debug events 8 Unconditional debug events In addition e200z0h defines additional debug events The External debug events DEVT1 and DEVT2 which are described in Section 36 10 11 External Debug Event The Critical Interrupt Taken debug event CIRPT which is described in Section 36 10 8 Critical Interrupt Taken D...

Page 878: ...he load or store class instruction from completing If a load or store class instruction completes successfully without a Data TLB or Data Storage interrupt Data Address Compare exceptions are reported at the completion of the instruction If the exception results in a precise Debug interrupt the address value saved in DSRR0 or CSRR0 if the Debug APU is disabled is the address of the instruction fol...

Page 879: ...nt Updates 1stload storeclass instruction 2nd load store class instruction Result DTLB Error no DAC Take DTLB exception no DBSR update update MASx registers for 1st load store class instruction Update ESR DSI no DAC Take DSI exception no DBSR update no MASx register update Update ESR DTLB Error with DACx1 Take Debug exception DBSR update setting DACx and IDE DAC_OFST not set No MASx register updat...

Page 880: ... Take Debug exception DBSR update setting DACx DACy DAC_OFST set to 2 b01 DSRR0 points to instruction after 2nd load store class instruction Debug counter update occurs for the 2nd ld st as appropriate Note in this case debug counter updates can occur for the 2nd ld st even though the 1st ld st has a DVC DAC exception Note in this case if x y then the resultant state of DBSR and DSRR0 may be indis...

Page 881: ...status bits are not set if the corresponding Instruction Address Compare register is linked Linking is enabled using control bits in DBCR2 NOTE Linked DAC events will not be recorded if a load multiple word or store multiple word instruction is interrupted prior to completion by a critical input or external input interrupt 36 10 4 Trap Debug Event A Trap debug event TRAP occurs if Trap debug event...

Page 882: ...nly non critical class interrupts cause an Interrupt Taken debug event This event can occur and be recorded in DBSR regardless of the setting of MSRDE When an Interrupt Taken debug event occurs the DBSRIRPT bit is set to 1 to record the debug exception The value saved in DSRR0 will be the address of the non critical interrupt handler 36 10 8 Critical Interrupt Taken Debug Event A Critical Interrup...

Page 883: ...ns to the asserted state This event can occur and be recorded in DBSR regardless of the setting of MSRDE When an External debug event occurs DBSRDEVT 1 2 is set to 1 to record the debug exception 36 10 12 Unconditional Debug Event An Unconditional debug event UDE occurs when the Unconditional Debug Event p_ude input transitions to the asserted state and either DBCR0IDM 1 or DBCR0EDM 1 The Uncondit...

Page 884: ... values for data comparison purposes DVC1 and DVC2 are 32 bit registers Data value comparisons are used to qualify Data Address compare debug events DVC1 is associated with DAC1 and DVC2 is associated with DAC2 The most significant byte of the DVC1 2 register labeled B0 in Figure 36 3 corresponds to the byte data value transferred to from memory byte offset 0 and the least significant byte of the ...

Page 885: ...ent s may be disabled via DBCR0 from setting DBSR flags 36 11 2 1 Debug Control Register 0 DBCR0 Debug Control Register 0 is used to enable debug modes and controls which debug events are allowed to set DBSR flags e200z0h adds some implementation specific bits to this register as seen in Figure 36 4 SPR 308 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R EDM IDM RST ICMP BRT IRPT TRAP IAC1 IAC2 IAC3 IAC4 ...

Page 886: ...debug registers The hardware debugger must set the EDM bit to 1 before other bits in this register and other debug registers may be altered On the initial setting of this bit to 1 all other bits are unchanged This bit is only writable through the OnCE port 1 IDM Internal Debug Mode 0 Debug exceptions are disabled Debug events do not affect DBSR unless EDM is set 1 Debug exceptions are enabled Enab...

Page 887: ...ata storage accesses 11 DAC1 debug events are enabled for load type or store type data storage accesses 14 15 DAC2 Data Address Compare 2 Debug Event Enable 00 DAC2 debug events are disabled 01 DAC2 debug events are enabled only for store type data storage accesses 10 DAC2 debug events are enabled only for load type data storage accesses 11 DAC2 debug events are enabled for load type or store type...

Page 888: ...d by MSRPR 01 Reserved 10 IAC1 debug events can only occur if MSRPR 0 Supervisor mode 11 IAC1 debug events can only occur if MSRPR 1 User mode 2 3 IAC1ER Instruction Address Compare 1 Effective Real Mode 00 IAC1 debug events are based on effective address 01 Unimplemented in e200z0h Book E real address compare no match can occur 10 IAC1 debug events are based on effective address and can only occu...

Page 889: ...ecified in IAC2 IAC2 debug events do not occur IAC1US and IAC1ER settings are used 10 15 Reserved 16 17 IAC3US Instruction Address Compare 3 User Supervisor Mode 00 IAC3 debug events not affected by MSRPR 01 Reserved 10 IAC3 debug events can only occur if MSRPR 0 Supervisor mode 11 IAC3 debug events can only occur if MSRPR 1 User mode 18 19 IAC3ER Instruction Address Compare 3 Effective Real Mode ...

Page 890: ...can occur only if the address of the instruction fetch is greater than or equal to the value specified in IAC3 and less than the value specified in IAC4 IAC4 debug events do not occur IAC3US and IAC3ER settings are used 11 Exclusive address range compare IAC3 debug events can occur only if the address of the instruction fetch is less than the value specified in IAC3 or is greater than or equal to ...

Page 891: ...ective address and can only occur if MSRDS 0 11 DAC2 debug events are based on effective address and can only occur if MSRDS 1 8 9 DAC12M Data Address Compare 1 2 Mode 00 Exact address compare DAC1 debug events can only occur if the address of the data access is equal to the value specified in DAC1 DAC2 debug events can only occur if the address of the data access is equal to the value specified i...

Page 892: ... when any byte specified in the DVC1BE field matches the corresponding data byte value for active byte lanes of the memory access 11 DAC1 debug events can only occur when all bytes specified in the DVC1BE field within at least one of the halfwords of the data value of the memory access matches the corresponding DVC1 value Note Inactive byte lanes of the memory access are automatically masked When ...

Page 893: ...e Inactive byte lanes of the memory access are automatically masked 16 19 Reserved 20 23 DVC1BE Data Value Compare 1 Byte Enables Specifies which bytes in the aligned doubleword value associated with the memory access are compared to the corresponding bytes in DVC1 Inactive byte lanes of a memory access smaller than 32 bits are automatically masked by hardware If all bits in the DVC1BE field are c...

Page 894: ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 36 7 DBCR4 Register Table 36 5 DBCR4 Bit Definitions Bit s Name Description 17 20 Reserved 0 DVC1C Data Value Compare 1 Control 0 Normal DVC1 operation 1 Inverted polarity DVC1 operation DVC1C controls whether DVC1 data value comparisons utilize the normal BookE operation or ...

Page 895: ...sponsible for clearing DBSR bits prior to returning to normal execution The Power Architecture technology VLE APU adds the DBSRVLES status bit to indicate debug events occurring due to a Power Architecture technology VLE instruction When resource sharing is enabled DBCR0EDM 1 and DBERC0IDM 1 only software owned resources may be modified by software and all status bits associated with hardware owne...

Page 896: ...nstruction Complete debug event occurred 5 BRT Branch Taken Debug Event Set to 1 if an Branch Taken debug event occurred 6 IRPT Interrupt Taken Debug Event Set to 1 if an Interrupt Taken debug event occurred 7 TRAP Trap Taken Debug Event Set to 1 if a Trap Taken debug event occurred 8 IAC1 Instruction Address Compare 1 Debug Event Set to 1 if an IAC1 debug event occurred 9 IAC2 Instruction Address...

Page 897: ...DBERC0 a set bit in DBSR which is software owned other than MRR or VLES will cause a debug interrupt to be generated Debug status bits in DBSR are set by hardware owned debug events only while External Debug Mode is enabled DBCR0EDM 1 16 RET Return Debug Event Set to 1 if a Return debug event occurred 17 20 Reserved 21 DEVT1 External Debug Event 1 Debug Event Set to 1 if a DEVT1 debug event occurr...

Page 898: ...tions to these registers with read modify write operations to implement any control sharing with software Settings in DBERC0 should be considered by the debug firmware in order to preserve software settings of control and status registers as appropriate when hardware modifications to the debug registers is performed The DBERC0 register is shown in Figure 36 9 SPR 569 0 1 2 3 4 5 6 7 8 9 10 11 12 1...

Page 899: ... Debug Event 0 Event owned by hardware debug No mtspr access by software to DBSRUDE field 1 Event owned by software debug DBSRUDE is software readable writeable 4 ICMP Instruction Complete Debug Event 0 Event owned by hardware debug No mtspr access by software to DBCR0ICMP or DBSRICMP fields 1 Event owned by software debug DBCR0ICMP and DBSRICMP are software readable writeable 5 BRT Branch Taken D...

Page 900: ...e to DAC1 control and status fields 1 Event owned by software debug DAC1 control and status fields are software readable writeable 13 Reserved 14 DAC2 Data Address Compare 2 Debug Event 0 Event owned by hardware debug No mtspr access by software to DAC2 control and status fields 1 Event owned by software debug DAC2 control and status fields are software readable writeable 15 Reserved 16 RET Return...

Page 901: ...ntry into debug mode 1 Breakpoint owned by software debug Execution of a bkpt instruction all 0 s opcode results in illegal instruction exception 28 30 Reserved 31 FT Freeze Timer Debug Control 0 DBCR0FT owned by hardware debug No access by software 1 DBCR0FT owned by software debug DBCR0FT is software readable writeable Table 36 8 DBERC0 Resource Control DBCR0 EDM DBERC0 IDM DBERC0 RST DBERC0 UDE...

Page 902: ...CR2DAC2US DAC2ER DVC2M DVC2BE DBCR4DVC2C DBSRDAC2 DAC_OFST 1 1 1 1 DBCR2DAC12M 1 1 1 1 DBCR2DAC1LNK 1 1 1 1 DBCR2DAC2LNK 1 1 1 DBCR0RET DBSRRET 1 1 1 DBCR0DEVT1 DBSRDEVT1 1 1 1 DBCR0DEVT2 DBSRDEVT2 1 1 1 DBCR0CIRPT DBSRCIRPT 1 1 1 DBCR0CRET DBSRCRET 1 1 1 1 1 1 DBCR0FT Table 36 8 DBERC0 Resource Control continued DBCR0 EDM DBERC0 IDM DBERC0 RST DBERC0 UDE DBERC0 ICMP DBERC0 BRT DBERC0 IRPT DBERC0 ...

Page 903: ...on through the On Chip Emulation logic OnCE NOTE On the initial setting of DBCR0EDM to 1 other bits in DBCR0 will remain unchanged After DBCR0EDM has been set all debug register resources may be subsequently controlled through the OnCE interface The DBSR register should be cleared as part of the process of enabling external debug activity The CPU should be placed into debug mode via the OCRDR cont...

Page 904: ...in IEEE 1149 1 standard boundary cells on its interface as it is a building block for further integration It does not support the JTAG related boundary scan instruction functionality although JTAG public instructions may be decoded and signaled to external logic The OnCE logic provides for Nexus Class 1 static debug capability utilizing the same set of resources available to software while in inte...

Page 905: ...sters The OnCE controller is implemented as a 16 state FSM finite state machine with a one to one correspondence to the states defined for the JTAG TAP controller OnCE mapped Debug registers Auxiliary data registers External Data registers Bypass register TAP instruction register TAP controller j_trst_b j_tclk j_tms TDO mux logic j_tdi j_tdo j_tdo_en OnCE OCMD ...

Page 906: ...eference the desired memory location executing the load instruction and then scanning out the result of the load Other resources are accessed in a similar manner The initial entry by the CPU into the debug state or mode from normal waiting stopped halted or checkstop states all indicated via the OnCE Status Register OSR Section 36 12 5 1 e200z0h OnCE Status Register by assertion of one or more deb...

Page 907: ...continue execution If a processor resource is required an internal debug request dbg_dbgrq may be asserted to the CPU by the OnCE controller and causes the CPU to finish the current instruction being executed save the instruction pipeline information enter Debug Mode and wait for further commands Asserting dbg_dbgrq will cause the chip to exit the low power mode enabled by the setting of MSRWE as ...

Page 908: ...t and all other commands default to a Bypass command The OnCE Status register OSR is not visible when OnCE operation is disabled In addition OnCE Control register OCR functions are disabled as is the operation of the jd_de_b input Secure systems may choose to leave the jd_en_once signal negated until a security check has been performed Other systems should tie this signal asserted to enable full O...

Page 909: ...th the GO and EX bits set and a register specified as either No Register Selected or the CPUSCR This signal will remain asserted even though the CPU may enter and exit the debug state for each instruction executed under control of the e200z0h OnCE controller See Section 36 12 5 2 for more information on the function of the GO and EX bits This signal is not normally used by the CPU 36 12 4 4 e200z0...

Page 910: ...te of the e200z0h CPU is latched into the OnCE Status register when the OnCE controller state machine enters the Capture IR state When OnCE operation is enabled this information is provided on the j_tdo output in serial fashion when the Shift_IR state is entered following a Capture IR Information is shifted out least significant bit first MCLK ERR CHKSTOP RESET HALT STOP DEBUG WAIT 0 1 0 1 2 3 4 5...

Page 911: ...gnal after capture by j_tclk 1 ERR ERROR This bit is used to indicate that an error condition occurred during attempted execution of the last single stepped instruction GO NoExit with CPUSCR or No Register Selected in OCMD and that the instruction may not have been properly executed This could occur if an Interrupt all classes including External Critical machine check Storage Alignment Program etc...

Page 912: ...rites most registers are sampled in the Capture DR state into a 32 bit shift register and subsequently shifted out on j_tdo during the first 32 clocks of Shift DR 1 GO Go Command Bit 0 Inactive no action taken 1 Execute instruction in IR If the GO bit is set the chip will execute the instruction which resides in the IR register in the CPUSCR To execute the instruction the processor leaves the debu...

Page 913: ...thout execution of an instruction even though the EX bit was set Note that asynchronous interrupts are blocked on a GO Exit operation until the first instruction to be executed begins execution 3 9 RS Register Select The Register Select bits define which register is source destination for the read write operation Table 36 12 indicates the e200z0h OnCE register addresses Attempted writes to read on...

Page 914: ...ed The OSRERR bit is set to indicate this condition In these cases values in the CPUSCR will correspond to the first instruction of the exception handler 010 0111 Data Value Compare 2 DVC2 010 1000 010 1011 Reserved 010 1100 Reserved DBCNT 010 1101 010 1111 Reserved 011 0000 Debug Status Register DBSR 011 0001 Debug Control Register 0 DBCR0 011 0010 Debug Control Register 1 DBCR1 011 0011 Debug Co...

Page 915: ... 0 0 0 0 0 I_DMDIS 0 0 I_DVLE I_DI I_DM 0 I_DE W Reset1 1 0xo000_0000 on m_por j_trst_b or entering Test_logic_Reset state 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R D_DMDIS 0 0 D_DW D_DI D_DM D_DG D_DE 0 0 0 0 0 WKUP FDB DR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 36 15 OnCE Control Register Table 36 13 OnCE Control Register Bit Definitions Bit s Name ...

Page 916: ...lly When disabled for Data Accesses no address translation is performed 1 1 address mapping and the TLB WIMGE bits are taken from the OCR bits D_DW D_DI D_DM D_DG and D_DE bits The SR SW UR and UW access permission control bits are set to 1 to allow full access When disabled no TLB miss or TLB exceptions are generated for Data accesses External access errors can still occur 17 18 Reserved 19 D_DW1...

Page 917: ...istent the CPU should be placed into debug mode or multiple reads should be performed until consistent values have been obtained on consecutive reads 29 WKUP Wakeup Request Bit WKUP This control bit may be used to force the e200z0h p_wakeup output signal to be asserted This control function may be used by debug firmware to request that the chip level clock controller restore the m_clk input to nor...

Page 918: ...peration and the fact that updates are not synchronized to a particular clock instruction or bus cycle boundary therefore it is strongly recommended to ensure the processor is first placed into debug mode before updates to these registers are performed DAC2 Y Y Y N 1 DBCR02 2 DBCR0EDM access only requires jd_en_once asserted Y Y Y N 1 DBCR1 Y Y Y N 1 DBCR2 Y Y Y N 1 DBCR4 Y Y Y N 1 DBERC0 Y N Y N ...

Page 919: ...ropriate reset to be re asserted 36 12 7 2 Debug Request During RESET Asserting a debug request by setting the DR bit in the OCR during the assertion of p_reset_b causes the chip to enter debug mode In this case the chip may fetch the first instruction of the reset exception handler but does not execute an instruction before entering debug mode In this case all values in the debug scan chain will ...

Page 920: ...necessary by external debug firmware to ensure proper scan sequences occur to registers in the m_clk clock domain 36 12 7 5 Software Request During Normal Activity Upon executing a bkpt pseudo instruction for e200z0h defined to be an all 0 s instruction opcode when the OCR register s FDB bit is set debug mode enable control bit is true and DBCR0EDM 1 the CPU enters the debug mode after the instruc...

Page 921: ... value should be saved for later restoration if continuation of the normal instruction stream is desired On scan in in preparation for exiting debug mode this register is filled with an instruction opcode selected by debug control software By selecting appropriate instructions and controlling the execution of those instructions the results of execution may be used to examine or change memory locat...

Page 922: ... re enters the waiting state on a go exit 0 CPU was not in the waiting state when debug mode was entered 1 CPU was in the waiting state when debug mode was entered PCOFST PC Offset Field This field indicates whether the value in the PC portion of the CPUSCR must be adjusted prior to exiting debug mode Due to the pipelined nature of the CPU the PC value must be backed up by emulation software in ce...

Page 923: ...Error condition exists PC and IR are corrupted FFRA Feed Forward RA Operand Bit This control bit causes the content of the WBBRlow to be used as the RA This control bit causes the content of the WBBR to be used as the RA operand value RS for logical mtspr mtdcr cntlzw and shift operations RX for VLE se_ instructions RT for e_ logical_op 2i type instructions and the value to use as the PC for calcu...

Page 924: ...tion Address Compare 4 event occurred on the fetch of this instruction IRStat6 IR Status Bit 6 This control bit indicates a Parity Error status for the IR Note that this bit is reserved 0 No Parity Error occurred on the fetch of this instruction 1 Parity Error occurred on the fetch of this instruction IRStat7 IR Status Bit 7 This control bit indicates a Precise External Termination Error status fo...

Page 925: ... value it will generally point to the last completed instruction although that instruction will not be re executed The nop instruction is executed instead and instruction fetch and execution will resume at location PC 4 IRStat8 will be used to determine the type of instruction present in the IR thus should be cleared in this case Note that debug events which may occur on the nop ICMP will be gener...

Page 926: ... not writeback a result and due to control issues are not defined on lmw or branch instructions as well 36 12 8 5 Machine State Register MSR The MSR is a 32 bit register used to read write the Machine State Register Whenever the external command controller needs to save or modify the contents of the Machine State Register this register is used This register is affected by the operations performed ...

Page 927: ...ntered the Debug state This can be done in conjunction with a Read of the CPUSCR The OSR is shifted out during the Shift_IR state The CPUSCR will be shifted out during the Shift_DR state The debugger should save the scanned out value of CPUSCR for later restoration Table 36 15 Watchpoint Output Signal Assignments Signal Name Type Description jd_watchpt 0 IAC1 Instruction Address Compare 1 watchpoi...

Page 928: ...ue The debugger scans out the OSR with no register selected Go cleared and determines that the PCU has re entered the Debug state and that no ERR condition occurred To return the CPU to normal operation without disabling external debug mode The OCRDMDIS OCRDR control bits should be cleared leaving the OCRWKUP bit set The debugger restores the CPUSCR with a previously saved value of the CPUSCR with...

Page 929: ...ed the client is enabled by loading its NEXUS ENABLE instruction The NEXUS ENABLE instruction opcode for each Nexus client is listed in Table 36 17 Opcodes for all other instructions supported by Nexus clients can be found in the relevant sections of this chapter 36 15 2 Debug mode control On MPC5602P program breaks can be requested when a Nexus event is triggered Table 36 16 JTAGC Instruction opc...

Page 930: ...Chapter 36 Nexus Development Interface NDI MPC5602P Microcontroller Reference Manual Rev 4 930 Freescale Semiconductor ...

Page 931: ...PC5602P Microcontroller Reference Manual Rev 4 Freescale Semiconductor 931 Chapter 37 Document Revision History Table 37 1 summarizes revisions to this document Table 37 1 Revision history Date Revision Changes 10 Dec 2009 1 Initial release ...

Page 932: ...5602P system clock distribution Part B CR field descriptions Corrected field name was NDIVNDIV is NDIV Chapter 7 Mode Entry Module MC_ME Section 7 4 4 Protection of Mode Configuration Registers Added bullet The 4 MHz crystal oscillator must be on if the system PLL is on Therefore when writing a 1 to PLL0ON a 1 must also be written to XOSC0ON Chapter 6 Power Control Unit MC_PCU Unchanged from previ...

Page 933: ...s Chapter 19 DMA Channel Mux DMA_MUX Updated DMA channel mapping Chapter 20 Deserial Serial Peripheral Interface DSPI Minor formatting changes DSPI memory map Updated reset values DSPI Clock and Transfer Attributes Registers 0 7 DSPIx_CTARn Changed reset value of field FMSZ 3 0 from 0000 to 1111 Chapter 21 LIN Controller LINFlex Minor formatting changes Updated Table 21 1 Error calculation for pro...

Page 934: ... not being supported by the FCU_FFGR Register summary In FCU_FFR changed field SRF1 to read only with value 0 In FCU_FFFR changed field FRSRF1 to read only with value 0 Section 28 2 3 2 Fault Flag Register FCU_FFR Removed sentence referencing clearing the software fault flag SRF1 changed field SRF1 to read only with value 0 Hardware software fault description Marked SRF1 as Not used Section 28 2 3...

Page 935: ...n Reset POR Removed sentence The other LVD_DIG is placed in the standby domain and senses the standby 1 2 V supply level notifying that the 1 2 V output is stable Voltage Regulator Control register VREG_CTL Changed reset values of register bits 23 and 27 Voltage Regulator Status register VREG_STATUS Changed reset values of register bits 23 and 27 Section 34 2 Power supply strategy Updated descript...

Page 936: ... Lite SIUL chapter In the MCU ID Register MIDR2 section replaced reset value of EE x is now 0 renamed the bit field FR with FF In the MIDR2 field description table renamed the bit field FR with FF and replaced its description with N A e200z0 and e200z0h Core chapter In the Core registers and programmer s model section removed note concerning the register numbering Error Correction Status Module EC...

Page 937: ...Deleted Halt Stop in first paragraph In the FlexCAN module memory map table removed access and reset columns In the Message Buffer lock mechanism section updated a footnote Analog to Digital Converter ADC chapter In the Conversion timing registers CTR section removed footnote in the Device specific features section removed internal standard channels from Sampling and conversion time register bulle...

Page 938: ...tes column In the Hardware Implementation Dependent Register 0 HID0 register made the DOZE fiel as reserved In the NDI functional block diagram figure removed ownership trace and watchpoint trace blocks In the e200z0h OnCE Register Addressing table replaced Nexus2 3 Access and LSRL Select see Test Specification with Reserved In the OnCE Register Access Requirements table removed both Nexus2 3 Acce...

Page 939: ...crocontroller State Register FCCU_MCSR section Updated bit values Frozen MC State Register FCCU_FMCSR section Updated bit values SRF1 was not used is now FCU Software triggered error Switched the module of SFR2 with that of SFR4 Updated all registers according the Hardware software fault description table Wakeup Unit WKPU chapter In the External Signal description section added note about Wakeup p...

Page 940: ...RGIN bit Table 17 35 NVUSRO field descriptions removed OSCILLATOR_MARGIN field and updated UOx bit fields Figure 17 8 Data Flash module structure Changed Test Sector size from 16K to 8K Table 17 1 Flash related regions in the system memory map Changed Data Flash Array 0 Test Sector size from 16K to 8K Table 17 7 64 KB data Flash module sectorization changed reserved area from 0x0081_0000 to 0x00C0...

Page 941: ...now is a section Section 21 8 3 1 LIN timeout mode changed sentence Setting the LTOM bit with Resetting the LTOM bit Section 21 8 3 2 Output compare mode changed sentence Programming LINTCSR LTOM 0 enables the output compare mode with Programming LINTCSR LTOM 1 enables the output compare mode Chapter 23 Analog to Digital Converter ADC Renamed section Analog watchdog pulse width modulation bus with...

Page 942: ...4 1 1 High Power or Main Regulator HPREG Chapter 35 IEEE 1149 1 Test Access Port Controller JTAGC Updated Section 35 9 e200z0 OnCE controller to remove reference of Nexus2 configuration registers Updated Table 35 4 e200z0 OnCE register addressing Nexus 2 Access was replaced with Reserved Chapter 36 Nexus Development Interface NDI Removed the following sections All sections between Section 36 8 Int...

Page 943: ...Flash PFAPR 32 0x0024 bits 0 31 Data Flash Base address 0xC3F8_C000 1 register to protect Data Flash MCR 32 0x0000 bits 0 31 SIU lite Base address 0xC3F9_0000 97 registers to protect SIUL IRER 32 0x0018 bits 0 31 SIUL IREER 32 0x0028 bits 0 31 SIUL IFEER 32 0x002C bits 0 31 SIUL IFER 32 0x0030 bits 0 31 SIUL PCR0 16 0x0040 bits 0 15 SIUL PCR1 16 0x0042 bits 0 15 SIUL PCR2 16 0x0044 bits 0 15 SIUL ...

Page 944: ...7 16 0x0076 bits 0 15 SIUL PCR28 16 0x0078 bits 0 15 SIUL PCR29 16 0x007A bits 0 15 SIUL PCR30 16 0x007C bits 0 15 SIUL PCR31 16 0x007E bits 0 15 SIUL PCR32 16 0x0080 bits 0 15 SIUL PCR33 16 0x0082 bits 0 15 SIUL PCR48 16 0x00A0 bits 0 15 SIUL PCR49 16 0x00A2 bits 0 15 SIUL PCR50 16 0x00A4 bits 0 15 SIUL PCR51 16 0x00A6 bits 0 15 SIUL PCR52 16 0x00A8 bits 0 15 SIUL PCR53 16 0x00AA bits 0 15 SIUL P...

Page 945: ... bits 0 31 SIUL PSMI12_15 32 0x050C bits 0 31 SIUL PSMI16_19 32 0x0510 bits 0 31 SIUL PSMI20_23 32 0x0514 bits 0 31 SIUL PSMI24_27 32 0x0518 bits 0 31 SIUL PSMI28_31 32 0x051C bits 0 31 SIUL PSMI32_35 32 0x0520 bits 0 31 SIUL IFMC0 32 0x1000 bits 0 31 SIUL IFMC1 32 0x01004 bits 0 31 SIUL IFMC2 32 0x1008 bits 0 31 SIUL IFMC3 32 0x100C bits 0 31 SIUL IFMC4 32 0x1010 bits 0 31 SIUL IFMC5 32 0x1014 bi...

Page 946: ...egister to protect PMU VREG_CTL 32 0x0000 bits 0 31 MC Mode Entry Base address 0xC3FD_C000 39 registers to protect MC ME ME_ME 32 0x0008 bits 0 31 MC ME ME_IM 32 0x0010 bits 0 31 MC ME ME_TEST_MC 32 0x0024 bits 0 31 MC ME ME_SAFE_MC 32 0x0028 bits 0 31 MC ME ME_DRUN_MC 32 0x002C bits 0 31 MC ME ME_RUN0_MC 32 0x0030 bits 0 31 MC ME ME_RUN1_MC 32 0x0034 bits 0 31 MC ME ME_RUN2_MC 32 0x0038 bits 0 31...

Page 947: ...C ME ME_PCTL 5 8 0x00C5 bits 0 31 MC ME ME_PCTL 6 8 0x00C6 bits 0 31 MC ME ME_PCTL 16 8 0x00D0 bits 0 7 MC ME ME_PCTL 26 8 0xC0DA bits 0 7 MC ME ME_PCTL 32 8 0xC0E0 bits 0 7 MC ME ME_PCTL 35 8 0xC0E3 bits 0 7 MC ME ME_PCTL 38 8 0xC0E6 bits 0 7 MC ME ME_PCTL 41 8 0xC0E9 bits 0 7 MC ME ME_PCTL 48 8 0xC0F0 bits 0 7 MC ME ME_PCTL 49 8 0xC0F1 bits 0 7 MC ME ME_PCTL 92 8 0xC11C bits 0 7 MC Clock Generat...

Page 948: ...6 0x001C bits 0 15 MCPower Control Unit Base address 0xC3FE_8000 1 register to protect MC PCU PCONF2 32 0x0008 bits 0 31 PIT_RTI Base address 0xC3FF_0000 9 registers to protect PIT_RTI PIT_RTI_PITMCR 32 0x0000 32 bit PIT_RTI PIT_RTI_LDVAL0 32 0x0100 32 bit PIT_RTI PIT_RTI_TCTRL0 32 0x0108 32 bit PIT_RTI PIT_RTI_LDVAL1 32 0x0110 32 bit PIT_RTI PIT_RTI_TCTRL1 32 0x0118 32 bit PIT_RTI PIT_RTI_LDVAL2 ...

Page 949: ...30 16 bit eTimer 0 CH1_CTRL3 16 0x0032 16 bit eTimer 0 CH1_CCCTRL 16 0x003C 16 bit eTimer 0 CH2_CTRL 16 0x004E 16 bit eTimer 0 CH2_CTRL2 16 0x0050 16 bit eTimer 0 CH2_CTRL3 16 0x0052 16 bit eTimer 0 CH2_CCCTRL 16 0x005C 16 bit eTimer 0 CH3_CTRL 16 0x006E 16 bit eTimer 0 CH3_CTRL2 16 0x0070 16 bit eTimer 0 CH3_CTRL3 16 0x0072 16 bit eTimer 0 CH3_CCCTRL 16 0x007C 16 bit eTimer 0 CH4_CTRL 16 0x008E 1...

Page 950: ...FlexPWM SUB1_INTEN 16 0x006C 16 bit FlexPWM SUB1_DMAEN 16 0x006E 16 bit FlexPWM SUB1_TCTRL 16 0x0070 16 bit FlexPWM SUB1_DISMAP 16 0x0072 16 bit FlexPWM SUB1_DTCNT0 16 0x0074 16 bit FlexPWM SUB1_DTCNT1 16 0x0076 16 bit FlexPWM SUB2_CTRL2 16 0x00A4 16 bit FlexPWM SUB2_CTRL 16 0x00A6 16 bit FlexPWM SUB2_OCTRL 16 0x00B8 16 bit FlexPWM SUB2_INTEN 16 0x00BC 16 bit FlexPWM SUB2_DMAEN 16 0x00BE 16 bit Fl...

Page 951: ... 32 bit DSPI 0 DSPI_CTAR0 32 0x000C 32 bit DSPI 0 DSPI_CTAR1 32 0x0010 32 bit DSPI 0 DSPI_CTAR2 32 0x0014 32 bit DSPI 0 DSPI_CTAR3 32 0x0018 32 bit DSPI 0 DSPI_CTAR4 32 0x001C 32 bit DSPI 0 DSPI_CTAR5 32 0x0020 32 bit DSPI 0 DSPI_CTAR6 32 0x0024 32 bit DSPI 0 DSPI_CTAR7 32 0x0028 32 bit DSPI 0 DSPI_RSER 32 0x0030 32 bit DSPI 1 Base address 0xFFF9_4000 11 registers to protect DSPI 1 DSPI_MCR 32 0x0...

Page 952: ...024 32 bit DSPI 2 DSPI_CTAR7 32 0x0028 32 bit DSPI 2 DSPI_RSER 32 0x0030 32 bit FlexCAN Base address 0xFFFC_0000 7 registers to protect FlexCAN CANx_MCR 32 0x0000 32 bit FlexCAN CANx_CTRL 32 0x0004 32 bit FlexCAN CANx_RXGMASK 32 0x0010 32 bit FlexCAN CANx_RX14MASK 32 0x0014 32 bit FlexCAN CANx_RX15MASK 32 0x0018 32 bit FlexCAN CANx_IMASK2 32 0x0024 32 bit FlexCAN CANx_IMASK 32 0x0028 32 bit Safety...

Page 953: ...troller Reference Manual Rev 4 Freescale Semiconductor 953 Safety port CANx_IMASK2 32 0x0024 32 bit Safety port CANx_IMASK 32 0x0028 32 bit Table A 1 Registers under protection continued Module Register Register size bits Register offset Protected bitfields ...

Page 954: ...be validated for each customer application by customer s technical experts Freescale does not convey any license under its patent rights nor the rights of others Freescale sells products pursuant to standard terms and conditions of sale which can be found at the following address http www reg net v2 webservices Freescale Docs TermsandConditions htm How to Reach Us Home Page freescale com Web Suppo...

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