DACVAL * (VDDA-VSSA)
1023
V =
Comparator Block
903
SPRUH22I – April 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
Analog Subsystem
Since the DAC is also in the analog domain it does not require a clock to maintain its voltage output. A
clock is required, however, to modify the digital inputs that control the DAC.
10.4.5 Initialization
There are two steps that must be performed prior to using the comparator block:
1. Enable the Band Gap inside the ADC by writing a 1 to the ADCBGPWD bit inside ADCCTL1.
2. Enable the comparator block by writing a 1 to the COMPDACEN bit in the COMPCTL register.
10.4.6 Digital Domain Manipulation
At the output of the comparator there are two more functional blocks that can be used to influence the
behavior of the comparator output. They are:
1. Inverter circuit: Controlled by the CMPINV bit in the COMPCTL register; will apply a logical NOT to the
output of the comparator. This function is asynchronous, while its control requires a clock present in
order to change its value.
2. Qualification block: Controlled by the QUALSEL bit field in the COMPCTL register, and gated by the
SYNCSEL bit in the COMPCTL register. This block can be used as a simple filter to only pass the
output of the comparator once it is synchronized to the system clock. and qualified by the number of
system clocks defined in QUALSEL bit field.
NOTE:
Some downstream modules (such as the ePWM DC Submodule) may require a minimum
comparator output pulse-width for correct operation.
