Register Descriptions
1345
SPRUH22I – April 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
M3 Universal Serial Bus (USB) Controller
18.5.37 USB Receive Control and Status Endpoint n Low Register (USBRXCSRL[1]-
USBRXCSRL[15])
The USB receive control and status endpoint
n
low 8-bit register (USBCSRL[
n
]) provides control and
status bits for transfers through the currently selected receive endpoint.
For the specific offset for each register see
.
Mode(s):
OTG A or Host
OTG B or Device
The USBCSRL[
n
] registers in OTG A/Host mode are shown in
and described in
Figure 18-46. USB Receive Control and Status Endpoint n Low Register (USBCSRL[n])
in OTG A/Host Mode
7
6
5
4
3
2
1
0
CLRDT
STALLED
REQPKT
FLUSH
DATAERR /
NAKTO
ERROR
FULL
RXRDY
W1C-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; -
n
= value after reset
Table 18-49. USB Control and Status Endpoint n Low Register(USBCSRL[n])
in OTG A/Host Mode Field Descriptions
Bit
Field
Value
Description
7
NAKTO
Clear Data Toggle.
0
No effect
1
Writing a 1 to this bit clears the DT bit in the USBRXCSRH[
n
] register.
6
STALLED
Endpoint Stalled. Software must clear this bit.
0
No handshake has been received.
1
A STALL handshake has been received. The EP
n
bit in the USBRXIS register is also set.
5
REQPKT
Request Packet. This bit is cleared when the RXRDY bit is set.
0
No request
1
Requests an IN transaction.
4
FLUSH
Flush FIFO. If the FIFO is double-buffered, FLUSH may have to be set twice to completely clear the
FIFO.
Note:
This bit should only be set when the RXRDY bit is set. At other times, it may cause data to be
corrupted.
0
No effect
1
Flushes the next packet to be read from the endpoint receive FIFO. The FIFO pointer is reset and the
RXRDY bit is cleared.
3
DATAERR /
NAKTO
Data Error / NAK Timeout
0
Normal operation
1
Isochronous endpoints only: Indicates that RXRDY is set and the data packet has a CRC or bit-stuff
error. This bit is cleared when RXRDY is cleared.
Bulk endpoints only: Indicates that the receive endpoint is halted following the receipt of NAK responses
for longer than the time set by the NAKLMT field in the USBRXINTERVAL[
n
] register. Software must
clear this bit to allow the endpoint to continue.
2
ERROR
Error. Software must clear this bit.
Note:
This bit is only valid when the receive endpoint is operating in Bulk or Interrupt mode. In
Isochronous mode, it always returns zero.
0
No error
1
Three attempts have been made to receive a packet and no data packet has been received. The EP
n
bit in the USBRXIS register is set in this situation.
1
FULL
FIFO Full
0
The receive FIFO is not full.
1
No more packets can be loaded into the receive FIFO.
