RAM Control Module
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SPRUH22I – April 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
Internal Memory
Table 5-3. Mapping of ECC bits in Read Data from ECC/Parity Address Map
Data Bits Location in Read Data
Content (ECC Memory)
6:0
ECC Code for lower 16 bits of data
7
Not Used
14:8
ECC Code for upper 16 bits of data
15
Not Used
22:16
ECC Code for address
31:23
Not Used
Table 5-4. Mapping of Parity bits in Read Data from ECC/Parity Address Map
Data Bits Location in Read Data
Content (Parity Memory)
0
Parity for lower 16 bits of data
7:1
Not Used
8
Parity for upper 16 bits of data
15:9
Not Used
16
Parity for address
31:17
Not Used
5.1.1.9
RAM Initialization
To ensure that read/fetch (byte write in case of M3/uDMA) from uninitialized RAM locations do not cause
ECC or parity errors, the RAM_INIT feature is provided for each memory block. Using this feature, any
RAM block can be initialized with 0x0 data and respective ECC/parity bits accordingly. This can be
initiated by setting the RAMINIT bit to ‘1’ for the specific RAM block in RTESTINIT registers. To check the
status of RAM_INIT, SW should poll for the RAMINITDONE bit for that RAM block in the RINITDONE
register to be set. Unless this bit gets set, no access should be made to that RAM memory block.
In case of Sx memory, the CPU of the subsystem, which is configured as the master for the particular Sx
RAM block, can only initiate the RAM initialization.
