Flash Controller Memory Module
505
SPRUH22I – April 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
Internal Memory
ECC logic should be disabled before reading the ECC memory space and it can be enabled as needed
after reading the ECC memory space.
5.3.10.1 Single-Bit Data Error
This section provides information for both single-bit, bit data errors or single-bit ECC check bit errors. If
there is a single bit flip (0 to 1 or 1 to 0) in flash data or in ECC data, then it is considered as a single-bit
data error. The SECDED module detects and corrects single bit errors, if any, in the 64-bit flash data or
eight ECC check bits read from the flash/ECC memory map before the read data is provided to the CPU.
When SECDED finds and corrects single bit data errors, the following information is logged in ECC
registers if the ECC feature is enabled:
•
Address where the error occurred (SINGLE_ERR_ADDR register).
•
Whether error occurred in data bits or ECC bits (ERR_TYPE bit field in ERR_POS register)
•
Bit position at which error occurred (ERR_POS bit field in ERR_POS register)
•
Whether the error occurred in lower 64-bit data/ECC or in upper 64-bit data/ECC (ECC_L_OR_H field
in ERR_POS register)
•
Whether the corrected value is 0 (FAIL_0 flag in ERR_STATUS register)
•
Whether the corrected value is 1 (FAIL_1 flag in ERR_STATUS register)
•
A single bit error counter that increments on every single bit error occurrence (ERR_CNT register) until
a user configurable threshold (see ERR_THRESHOLD) is met
•
A flag that gets set when one more single bit error occurs after ERR_CNT equals ERR_THRESHOLD
(SINGLE_ERR_INT_FLG flag in ERR_INTFLG register)
When the ERR_CNT value equals TH1 value and a single bit error occurs, the
SINGLE_ERR_INT flag is set, and an interrupt (C28FLSINGERR on C28x PIE and M3 Flash Single Error
on M3 NVIC have to be enabled for interrupts, if needed ) is fired. The SINGLE_ERR interrupt will not be
fired again until the SINGLE_ERR_INT_FLG is cleared. If the single error interrupt flag is not cleared
using the corresponding error interrupt clear bit in the ERR_INTCLR register, the error interrupt will not
come again, as this is an edge-based interrupt.
5.3.10.2 Uncorrectable Error
Uncorrectable errors include address errors and double-bit errors in data/ECC. When SECDED finds
uncorrectable errors, the following information is logged in ECC registers if the ECC feature is enabled:
•
Address where the error occurred (UNC_ERR_ADDR register).
•
A flag is set indicating that an uncorrectable error occured (UNC_ERR flag in ERR_STATUS register)
•
A flag is set indicating that an uncorrectable error interrupt is fired (UNC_ERR_INT_FLG in
ERR_INTFLG register)
When an uncorrectable error occurs, the UNC_ERR_INT_FLG bit is set and an uncorrectable error
interrupt is fired. This uncorrectable error interrupt generates a bus fault on Cortex-M3 and an NMI on the
C28x core, if enabled. If an uncorrectable error interrupt flag is not cleared using the corresponding error
interrupt clear bit in the ERR_INTCLR register, an error interrupt will not come again, as this is an edge-
based interrupt.
Although the ECC is calculated on a 64-bit basis, a read of any address location within a 128-bit aligned
flash memory will cause the uncorrectable error flag to get set when there is an uncorrectable error in both
or in either one of the lower 64 and upper 64 bits (or corresponding ECC check bits) of that 128-bit data.
NMI will occur on C28x for a read of any address location within a 128-bit aligned flash memory when
there is an uncorrectable error in both or in either one of the lower 64 and upper 64 bits (or corresponding
ECC check bits) of that 128-bit data. However, the bus-fault on M3 will occur only when a memory
location from the particular 6 -bits (or corresponding ECC check bits) that have an uncorrectable error is
read. They will not occur for the other 64 bits that do not have an uncorrectable error in the 128-bit
memory aligned data.
