Analog-to-Digital Converter (ADC)
868
SPRUH22I – April 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
Analog Subsystem
10.3.6 Simultaneous Sampling Mode
In some applications it is important to keep the delay between the sampling of two signals minimal. The
ADC contains dual sample and hold circuits to allow two different channels to be sampled simultaneously.
Simultaneous sampling mode is configured for a pair of SOCx's with the ADCSAMPLEMODE register.
The even numbered SOCx and the following odd numbered SOCx (SOC0 and SOC1) are coupled
together with one enable bit (SIMULEN0, in this case). The coupling behavior is as follows:
•
Either SOCx’s trigger will start a pair of conversions.
•
The pair of channels converted will consist of the A-channel and the B-channel corresponding to the
value of the CHSEL field of the triggered SOCx. The valid values in this mode are 0-7.
•
Both channels will be sampled simultaneously.
•
The A channel will always convert first.
•
The even EOCx pulse will be generated based off of the A-channel conversion, the odd EOCx pulse
will be generated off of the B-channel conversion. See
for an explanation of the EOCx
signals.
•
The result of the A-channel conversion is placed in the even ADCRESULTx register and the result of
the B-channel conversion is written to the odd ADCRESULTx register.
NOTE:
If EOCx pulses are configured to generate interrupts, and ADC triggers are set up for both the
even and odd SOCs in the same pair, two interrupts will be generated. If this is not the desired behavior,
only configure the trigger for either the A channel or B channel in the pair to receive one interrupt.
For example, if the ADCSAMPLEMODE.SIMULEN0 bit is set, and SOC0 is configured as follows:
CHSEL = 2 (ADCINA2/ADCINB2 pair)
TRIGSEL = 5 (ADCTRIG1)
TRIG1SEL = 5 (ePWM1.ADCSOCA)
When the ePWM1 sends out an ADCSOCA trigger, both ADCINA2 and ADCINB2 will be sampled
simultaneously (assuming priority). Immediately after, the ADCINA2 channel will be converted and its
value will be stored in the ADCRESULT0 register. Depending on the ADCCTL1.INTPULSEPOS setting,
the EOC0 pulse will either occur when the conversion of ADCINA2 begins or completes. Then the
ADCINB2 channel will be converted and its value will be stored in the ADCRESULT1 register. Depending
on the ADCCTL1.INTPULSEPOS setting, the EOC1 pulse will either occur when the conversion of
ADCINB2 begins or completes.
Typically in an application it is expected that only the even SOCx of the pair will be used. However, it is
possible to use the odd SOCx instead, or even both. In the latter case, both SOCx triggers will start a
conversion. Therefore, caution is urged as both SOCx's will store their results to the same ADCRESULTx
registers, possibly overwriting each other.
The rules of priority for the SOCx’s remain the same as in sequential sampling mode.
shows the timing of simultaneous sampling mode.
10.3.7 EOC and Interrupt Operation
Just as there are 16 independent SOCx configuration sets, there are 16 EOCx pulses. In sequential
sampling mode, the EOCx is associated directly with the SOCx. In simultaneous sampling mode, the even
and the following odd EOCx pair are associated with the even and the following odd SOCx pair, as
described in
. Depending on the ADCCTL1.INTPULSEPOS setting, the EOCx pulse will
occur either at the beginning of a conversion or the end. See
for exact timings on the
EOCx pulses.
The ADC contains eight interrupts that can be flagged and/or passed on to the PIE and NVIC. Each of
these interrupts can be configured to accept any of the available EOCx signals as its source. The
configuration of which EOCx is the source is done in the INTSELxNy registers. Additionally, the ADCINT1
and ADCINT2 signals can be configured to generate an SOCx trigger. This is beneficial to creating a
continuous stream of conversions.
There are a total of 8 interrupts available for both ADC1 and ADC2. Each ADC does not have its own set
of 8 interrupts. These resources must be shared.
