Transmitter Configuration
1100
SPRUH22I – April 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
C28 Multichannel Buffered Serial Port (McBSP)
15.9.5.1 Clock Stop Mode
The clock stop mode supports the SPI master-slave protocol. If you do not plan to use the SPI protocol,
you can clear CLKSTP to disable the clock stop mode.
In the clock stop mode, the clock stops at the end of each data transfer. At the beginning of each data
transfer, the clock starts immediately (CLKSTP = 10b) or after a half-cycle delay (CLKSTP = 11b). The
CLKXP bit determines whether the starting edge of the clock on the MCLKX pin is rising or falling. The
CLKRP bit determines whether receive data is sampled on the rising or falling edge of the clock shown on
the MCLKR pin.
summarizes the impact of CLKSTP, CLKXP, and CLKRP on serial port operation. In the clock
stop mode, the receive clock is tied internally to the transmit clock, and the receive frame-synchronization
signal is tied internally to the transmit frame-synchronization signal.
Table 15-51. Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme
Bit Settings
Clock Scheme
CLKSTP = 00b or 01b
Clock stop mode disabled. Clock enabled for non-SPI mode.
CLKXP = 0 or 1
CLKRP = 0 or 1
CLKSTP = 10b
Low inactive state without delay: The McBSP transmits data on the rising edge of CLKX and
receives data on the falling edge of MCLKR.
CLKXP = 0
CLKRP = 0
CLKSTP = 11b
Low inactive state with delay: The McBSP transmits data one-half cycle ahead of the rising
edge of CLKX and receives data on the rising edge of MCLKR.
CLKXP = 0
CLKRP = 1
CLKSTP = 10b
High inactive state without delay: The McBSP transmits data on the falling edge of CLKX and
receives data on the rising edge of MCLKR.
CLKXP = 1
CLKRP = 0
CLKSTP = 11b
High inactive state with delay: The McBSP transmits data one-half cycle ahead of the falling
edge of CLKX and receives data on the falling edge of MCLKR.
CLKXP = 1
CLKRP = 1
