Flash Controller Memory Module
497
SPRUH22I – April 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
Internal Memory
The AGP value is programmed by a set of programmable counters (FBAC and FPAC2) which keep the
flash bank or charge pump in active mode until the counter expires, at which time the bank or charge
pump reverts to its fallback power mode as defined in the FBFALLBACK and FPAC1 registers. The
application software can program the fallback power mode to be standby or sleep mode to reduce power
consumption, or program it to be active mode to keep the bank active regardless of counter settings
(default). The charge pump AGP counter remains in its initialized state when any one of the banks is
active, including the AGP counter of the bank. The charge pump AGP counter begins counting when both
banks have become inactive.
The charge pump can be put into sleep mode only when both the M3-bank and the C28x bank are put to
sleep first. The PMPPWR bit in the FPAC1 register of both M3-FMC and C28x-FMC have to be configured
for sleep mode for the pump to go to sleep mode. Note that each core has to gain the pump semaphore to
be able to write to their respective FMC’s PMPPWR bit. As the pump is shared between M3-FMC and
C28x-FMC, the effective PAGP value used when powering down the pump will be of the FMC (out of M3-
FMC and C28x-FMC) which owns the pump. The pump will become active if an access is made either to
the M3-bank or the C28x-bank. Note that the PUMPRDY bit in the M3-FMC register space can be used by
the application software to identify the current power mode status of the pump and that PUMPRDY bit
(and also PMPPWR bit) in C28x-FMC cannot be used for that purpose. See register descriptions for
detailed information.
5.3.7 Flash and OTP Performance
Once flash bank and pump are in the active power state, then a read or fetch access to the bank memory
map area can be classified as a flash access (access to an address location in flash) or an OTP access
(access to an address location in OTP). Once the CPU throws an access to a flash memory address, data
is returned after RWAIT+1 number of core-specific SYSCLK cycles. For an OTP access, data is returned
after RWAIT+2 number of core-specific SYSCLK cycles.
RWAIT defines the number of random access wait states and is configurable using the RWAIT bit-field in
the FRDCNTL register. At reset, the RWAIT bit-field value defaults to a worst-case wait state count (15)
and thus, needs to be initialized for the appropriate number of wait states to improve performance, based
on the CPU clock rate and the access time of the flash.
The flash supports 0-wait accesses when the RWAIT bits are set to zero. This assumes that the CPU
speed is low enough to accommodate the access time.
For a given system clock frequency, RWAIT must be configured using the below formula:
RWAIT =[(SYSCLK/FCLK)-1] round up to the next highest integer or 1, whichever is larger
where
SYSCLK is the system operating frequency
FCLK is flash clock frequency. FCLK should be
≤
FCLKmax, allowed maximum flash clock frequency with
RWAIT=0.
If RWAIT results in a fractional value when calculated using the above formula, RWAIT has to be rounded
up to the nearest integer.
5.3.8 Flash Read Interface
This section provides details about the data read modes to access flash bank/OTP and the configuration
registers which control the read interface. In addition to a standard read mode, FMCs have built-in
prefetch and cache mechanisms to allow increased clock speeds and CPU throughput wherever
applicable.
5.3.8.1
M3-FMC Flash Read Interface
5.3.8.1.1 Standard Read Mode
Standard read mode is defined as the read mode in effect when program cache/prefetch-mechanism and
data cache are disabled. It is also the default read mode after reset. During this mode, each read access
to flash is decoded by the flash wrapper to fetch the data from the addressed location and the data is
returned after the RWAIT+1 number of cycles.
