Flash Controller Memory Module
500
SPRUH22I – April 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
Internal Memory
lock bits are not all 1s and the respective zone is not unlocked.
•
When the Code Security Module (CSM) is secured, reads to the flash/OTP memory map area from
outside the secure zone take the same number of cycles as a normal access. However, the read
operation returns a zero.
•
The arbitration scheme in M3-FMC prioritizes Cortex-M3 accesses in the fixed priority order of data
space access (DCODE), program space access (ICODE)/program space prefetch.
•
When FSM interface is active for erase/program operations, data in the program cache and data cache
in FMC will be invalidated.
5.3.8.2
C28x-FMC Flash Read Interface
5.3.8.2.1 Standard Read Mode
Standard read mode is defined as the read mode in effect when code prefetch-mechanism and data
cache are disabled. It is also the default read mode after reset. During this mode, each read access to
flash is decoded by the flash wrapper to fetch the data from the addressed location and the data is
returned after the RWAIT+1 number of cycles.
Prefetch buffers associated with the prefetch mechanism and data cache are bypassed in standard read
mode; therefore, every access to the flash/OTP is used by the CPU immediately and every access creates
a unique flash bank access.
Standard read mode is the recommended mode for lower system frequency operation in which RWAIT
can be set to zero to provide single cycle access operation. The FMC can operate at higher frequencies
using standard read mode at the expense of adding wait states. At higher system frequencies, it is
recommended to enable the code prefetch mechanism and data cache to improve performance. Please
refer to the device specific data manual to determine maximum flash frequency allowed in standard read
mode (that is, maximum flash clock frequency with one wait state - FCLKmax).
5.3.8.2.2 Prefetch Mode
Flash memory is typically used to store application code. During code execution, instructions are fetched
from sequential memory addresses, except when a discontinuity occurs. Usually the portion of the code
that resides in sequential addresses makes up the majority of the application code and is referred to as
linear code. To improve the performance of linear code execution, a flash prefetch-mechanism has been
implemented in FMC.
illustrates how this mode functions.
This prefetch mechanism does a look-ahead prefetch on linear address increments starting from the
address of the last instruction fetch. The flash prefetch mechanism is disabled by default. Setting the
PREFETCH_EN bit in the FRD_INTF_CTRL register enables this prefetch mode.
An instruction fetch from the flash or OTP reads out 128 bits per access. The starting address of the
access from flash is automatically aligned to a 128-bit boundary, such that the instruction location is within
the 128 bits to be fetched. With flash prefetch mode enabled, the 128 bits read from the instruction fetch
are stored in a 128-bit wide by 2-level deep instruction prefetch buffer. The contents of this prefetch buffer
are then sent to the CPU for processing as required.
Up to four 32-bit instructions or up to eight 16-bit instructions can reside within a single 128-bit access.
The majority of C28x instructions are 16 bits, so for every 128-bit instruction fetch from the flash bank, it is
likely that there are up to eight instructions in the prefetch buffer ready to process through the CPU.
During the time it takes to process these instructions, the flash prefetch mechanism automatically initiates
another access to the flash bank to prefetch the next 128 bits. In this manner, the flash prefetch
mechanism works in the background to keep the instruction prefetch buffers as full as possible. Using this
technique, the overall efficiency of sequential code execution from flash or OTP is improved significantly. If
the prefetch mechanism is enabled, then the last row of 128-bits in the bank should not be used, because
the prefetch logic which does a look-ahead prefetch, will try to fetch from outside the bank and would
result in ECC error.
The flash prefetch is aborted only on a PC discontinuity caused by executing an instruction such as a
branch, BANZ, call, or loop. When this occurs, the prefetch is aborted and the contents of the prefetch
buffer are flushed. There are two possible scenarios when this occurs:
