4
μs
μs
4
μs
2x(13x(9
))
------------------------------------------------------
-
min TSeg1 TSeg2
,
(
)
2x(13x(bit_time-TSeg2))
---------------------------------------------------------------------
0,1
0,1
μs
μs))
2
x
13x( 1 s
μ
)
-----------------------------------------------------------
min TSeg1 Tseg2
,
(
)
2x (13x(bit_time-TSeg2))
-----------------------------------------------------------------------
Message Interface Register Sets
1537
SPRUH22I – April 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
M3 Controller Area Network (CAN)
t
q
100 ns
=
t
CAN_CLK
delay of bus driver
90 ns
=
delay of receiver circuit
40 ns
=
delay of bus line (40m)
220 ns
=
t
Prop
700 ns
=
2*delays = 7 • t
q
t
SJW
100 ns
=
1 • t
q
t
TSeg1
800 ns
=
t
Prop
+ t
SJW
t
TSeg2
100 ns
=
Information Processing Time + 1 • t
q
t
Sync-Seg
100 ns
=
1 • t
q
bit time
1000 ns
=
t
Sync-Seg
+ t
TSeg1
+ t
TSeg2
tolerance for CAN_CLK
0.43 %
=
=
In this example, the concatenated bit time parameters are (1-1)
3
&(8-1)
4
&(1-1)
2
&(1-1)
6
, so the Bit Timing
register is programmed to = 0x00000700.
23.12.2.3 Example for Bit Timing at low Baudrate
In this example, the frequency of CAN_CLK is 2 MHz, BRP is 1, the bit rate is 100 KBit/s.
t
q
1
μ
s
=
2 • t
CAN_CLK
delay of bus driver
200 ns
=
delay of receiver circuit
80 ns
=
delay of bus line (40m)
220 ns
=
t
Prop
1
μ
s
=
1 • t
q
t
SJW
4
μ
s
=
4 • t
q
t
TSeg1
5
μ
s
=
t
Prop
+ t
SJW
t
TSeg2
4
μ
s
=
Information Processing Time + 4 • t
q
t
Sync-Seg
1
μ
s
=
1 • t
q
bit time
10
μ
s
=
t
Sync-Seg
+ t
TSeg1
+ t
TSeg2
tolerance for CAN_CLK
3.08 %
=
=
In this example, the concatenated bit time parameters are (4-1)
3
&(5-1)
4
&(4-1)
2
&(2-1)
6
, so the Bit Timing
register is programmed to = 0x000034C1.
23.13 Message Interface Register Sets
The interface register sets control the CPU read and write accesses to the Message RAM. There are two
interface register sets for read or write access (IF1 and IF2) and one Interface Register Set for read
access only (IF3).
