Texas Instruments Concerto F28M35 Series, Technical Reference Manual

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Ethernet MAC Register Descriptions
1393 SPRUH22I – April 2012 – Revised November 2019
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Copyright © 2012–2019, Texas Instruments Incorporated
M3 Ethernet Media Access Controller (EMAC)
19.6.5 Ethernet MAC Data (MACDATA) Register, offset 0x010
The Ethernet MAC Data (MACDATA) register enables software to access the TX and RX FIFOs. Reads
from this register return the data stored in the RX FIFO from the location indicated by the read pointer.
The read pointer is then auto incremented to the next RX FIFO location. Reading from the RX FIFO when
a frame has not been received or is in the process of being received returns indeterminate data and does
not increment the read pointer.
Writes to this register store the data in the TX FIFO at the location indicated by the write pointer. The write
pointer is then auto incremented to the next TX FIFO location. Writing more data into the TX FIFO than
indicated in the length field results in the data being lost. Writing less data into the TX FIFO than indicated
in the length field results in indeterminate data being appended to the end of the frame to achieve the
indicated length. Attempting to write the next frame into the TX FIFO before transmission of the first has
completed results in the data being lost.
Bytes may not be randomly accessed in either the RX or TX FIFOs. Data must be read from the RX FIFO
sequentially and stored in a buffer for further processing. Once a read has been performed, the data in the
FIFO cannot be re-read. Data must be written to the TX FIFO sequentially. If an error is made in placing
the frame into the TX FIFO, the write pointer can be reset to the start of the TX FIFO by writing the TXER
bit of the MACIACK register and then the data re-written.
READS
Figure 19-8. Ethernet MAC Data (MACDATA) Register (READ)
31 0
RXDATA
R-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 19-7. Ethernet MAC Data (MACDATA) Register (READ) Field Descriptions
Bit Field Value Description
31-0 RXDATA 0x0000.
0000
Receive FIFO Data
The RXDATA bits represent the next word of data stored in the RX FIFO.
WRITES
Figure 19-9. Ethernet MAC Data (MACDATA) Register (WRITE)
31 0
TXDATA
R-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 19-8. Ethernet MAC Data (MACDATA) Register (WRITE) Field Descriptions
Bit Field Value Description
31-0 TXDATA 0x0000.
0000
Transmit FIFO Data
The TXDATA bits represent the next word of data stored in the TX FIFO for transmission.