Flash Registers
518
SPRUH22I – April 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
Internal Memory
5.4.2 Master Subsystem Flash ECC/Error Log Registers
5.4.2.1
ECC Enable Register (ECC_Enable)
Figure 5-92. ECC Enable Register (ECC_Enable)
31
4
3
0
Reserved
ENABLE
R-0
R/W-0xA
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 5-96. ECC Enable Register (ECC_Enable) Field Descriptions
Bit
Field
Value
Description
31-4
Reserved
Reserved
3-0
ENABLE
0xA
ECC enable. A value of 0xA would enable ECC. Any other value would disable ECC.
5.4.2.2
Single Error Address Register (SINGLE_ERR_ADDR)
Figure 5-93. Single Error Address Register (SINGLE_ERR_ADDR)
31
0
ERR_ADDR
R-0
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 5-97. Single Error Address Register (SINGLE_ERR_ADDR) Field Descriptions
Bit
Field
Value
Description
31-0
ERR_ADDR
Address at which a single bit error occurred, aligned to a 64-bit boundary.
5.4.2.3
Uncorrectable Error Address Register (UNC_ERR_ADDR)
Figure 5-94. Uncorrectable Error Address Register (UNC_ERR_ADDR)
31
0
UNC_ERR_ADDR
R-0
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 5-98. Uncorrectable Error Address Register (UNC_ERR_ADDR) Field Descriptions
Bit
Field
Value
Description
31-0
UNC_ERR_ADD
R
Address at which an un-correctable error occurred, aligned to a 64-bit boundary